ENCODE AINA 10-Bit, 40/65/80/105 MSPS Dual Converter AD9218
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FEATURES Dual 10-Bit, MSPS, MSPS, MSPS, MSPS Power: MSPS Channel On-Chip Reference Track/Holds Analog Bandwidth Each Channel MHz, Encode MSPS Analog Input Range Each Channel Single Supply Operation (2.7 Power-Down Mode Single Channel Operation Twos Complement Offset Binary Output Mode Output Data Alignment Mode Compatible with 8-Bit AD9288 Crosstalk between Channels APPLICATIONS Battery-Powered Instruments Hand-Held Scopemeters Cost Digital Oscilloscopes Communications Ultrasound Equipment
ENCODE AINA
10-Bit, 40/65/80/105 MSPS Dual Converter AD9218
FUNCTIONAL BLOCK DIAGRAM
TIMING
AD9218
OUTPUT REGISTER D9A-D0A USER SELECT USER SELECT DATA FORMAT/ GAIN
AINA AINB AINB ENCODE TIMING
OUTPUT REGISTER
D9B-D0B
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD9218 dual 10-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits optimized cost, power, small size ease use. product operates MSPS conversion rate with outstanding dynamic performance over full operating range. Each channel operated independently. requires only single (2.7 power supply encode clock full operation. external reference driver components required many applications. digital outputs TTL/CMOS compatible separate output power supply supports interfacing with logic. clock input TTL/CMOS-compatible 10-bit digital outputs operated from (2.5 supplies. User-selectable options available offer combination power-down modes, digital data formats digital data timing schemes. power-down mode, digital outputs driven high impedance state. Fabricated advanced CMOS process, AD9218 available 48-lead Profile Quad Flat Package LQFP) specified over industrial temperature range (-40C +85C).
Power. Just power dissipation channel MSPS. Other speed grade proportionally scaled down while maintaining high performance. Compatibility Upgrade. Allows easy migration from 8-bit 10-bit. compatible with 8-bit AD9288 dual ADC. Ease Use. On-chip reference user controls provide flexibility system design. High Performance. Maintains MSPS with Nyquist input. Channel Crosstalk. Very dBc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD9218-SPECIFICATIONS
SPECIFICATIONS
Parameter
external reference, unless otherwise noted.)
Temp Test Level AD9218BST-40/-65 AD9218BST-80/-105 Unit
RESOLUTION ACCURACY Missing Codes1 Offset Error2 Gain Error2 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error2 Reference REFERENCE Internal Reference Voltage (REFOUT) Input Resistance (REFIN ANALOG INPUTS Differential Input Voltage Range (AIN, Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLY Supply Currents IVDD (VDD Power Dissipation Power-Down Current6 Power Supply Rejection Ratio Full Full Full Full Full Full
Guarenteed Tested 0.3/± 1/1.3 -1/-1.6 0.3/± +1/1.6
Guarenteed Tested +3.5 0.5/± 1.2/1.7 0.6/± -1.35/-2.7 0.75/± +1.35/2.7
Bits
ppm/C ppm/C ppm/C
Full
1.18
1.24
1.28
1.18
1.24
1.28
Full Full Full Full Full Full Full Full
VD/3 108/117 7/11 325/350
VD/3 172/183 13/17 515/550
mV/V
113/122 340/365
175/188 525/565
NOTES missing codes across industrial temperature range guaranteed MSPS, MSPS, MSPS grades. missing codes room temperature guaranteed MSPS grade. Gain error gain temperature coefficients based only (with fixed 1.25 external reference) Grade range, -40, -85, -105 Grades range. (AIN range (full scale), range (full scale). power dissipation measured with rated encode 10.3 analog input dBFS, LOAD power dissipation measured with rated encode analog input (Outputs Static, power-down state typical (all grades). Specifications subject change without notice.
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AD9218 DIGITAL SPECIFICATIONS
Parameter DIGITAL INPUTS Encode Input Common Mode Encode Voltage Encode Voltage Encode Input Resistance Logic Voltage-S1, Logic Voltage-S1, Logic Current-S1 Logic Current-S1 Logic Current-S2 Logic Current-S2 Logic Current-DFS Logic Current-DFS Input Capacitance-S1, Encode Inputs Input Capacitance DIGITAL OUTPUTS Logic Voltage Logic Voltage Output Coding
Specifications subject change without notice.
(VDD external reference, unless otherwise noted.)
Test Temp Level Full Full Full Full Full Full Full Full Full Full Full Full Full Full AD9218BST-40/-65 VD/2 -400 -400 -230 -230 -400 -400 -230 -230 AD9218BST-80/-105 VD/2 Unit
2.45 0.05 0.05 Twos Complement Offset Binary Twos Complement Offset Binary
2.45
SPECIFICATIONS
Parameter
(VDD external reference, unless otherwise noted.)
Temp Test Level AD9218BST-40/-65 AD9218BST-80/-105 Unit
DYNAMIC PERFORMANCE1 Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3 Nyquist2 Signal-to-Noise Ratio (SINAD) (With Harmonics) 10.3 Nyquist2 Effective Number Bits 10.3 Nyquist2 Second Harmonic Distortion 10.3 Nyquist2 Third Harmonic Distortion 10.3 Nyquist2 Spurious Free Dynamic Range SFDR 10.3 Nyquist2 Two-Tone Intermod Distortion (IMD) fIN1 MHz, fIN2 dBFS fIN1 MHz, fIN2 dBFS Analog Bandwidth, Full Power Crosstalk
58/55 -/54
59/57 59/56
57/53 55/52
58/55 57/54
58/54 -/53 9.4/8.8 -/8.6 -72/-66 -/-63 -68/-62 -/-60 -68/-62 -/-60
59/56 59/55 9.6/9.1 9.6/8.9 -89/-77 -89/-72 -79/-68 -78/-64 -79/-67 -78/-64 -74/-73 -73/-73
56/52 55/51 9.1/8.4 9/8.3 -69/-60 -65/-57 -62/-57 -63/-57 -62/-57 -63/-57
58/53 57/53 9.4/8.6 9.3/8.6 -77/-68 -76/-66 -71/-63 -73/-69 -69/-62 -70/-63
Bits Bits
-77/-67
NOTES specs based analog input voltage -0.5 dBFS 10.3 unless otherwise noted. specs -40, -80, -105 grades tested range driven differentially. specs grade tested range driven differentially. -65, -80, -105 grades tested close Nyquist that grade: MHz, MHz, -65, -80, -105 grades respectively. Specifications subject change without notice.
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AD9218 SWITCHING SPECIFICATIONS
Parameter ENCODE INPUT PARAMETERS Maximum Encode Rate Minimum Encode Rate Encode Pulsewidth High (tEH) Encode Pulsewidth (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) DIGITAL OUTPUT PARAMETERS Output Valid Time (tV)* Output Propagation Delay (tPD)* Output Rise Time (tR) Output Fall Time (tF) Range Recovery Time Transient Response Time Recovery Time from Power-Down Pipeline Delay
external reference, unless otherwise noted.)
Test Level AD9218BST-40/-65 40/65 20/20 5/3.8 5/3.8 AD9218BST-80/-105 80/105 20/20 Unit MSPS MSPS Cycles Cycles
Temp Full Full Full Full Full Full Full
measured from level ENCODE input 50%/50% levels digital outputs swing. digital output load during test exceed load current Rise fall times measured from 90%. Specifications subject change without notice.
SAMPLE
SAMPLE
SAMPLE
SAMPLE
AINB
ENCODE
SAMPLE 1/fS
SAMPLE
SAMPLE
D9A-D0A DATA DATA DATA DATA DATA DATA
D9B-D0B
DATA
DATA
DATA
DATA
DATA
DATA
Figure Normal Operation, Same Clock Channel Timing
REV.
AD9218
SAMPLE AINB SAMPLE SAMPLE SAMPLE SAMPLE
ENCODE
SAMPLE SAMPLE SAMPLE SAMPLE 1/fS
ENCODE
D9A-D0A
DATA N-10
DATA
DATA
DATA
DATA
DATA
DATA
D9B-D0B
DATA
DATA
DATA
DATA
DATA
DATA
Figure Normal Operation with Clock Sources Channel Timing
SAMPLE AINB
SAMPLE SAMPLE
SAMPLE SAMPLE
ENCODE
SAMPLE SAMPLE SAMPLE SAMPLE 1/fS
ENCODE
D9A-D0A
DATA N-10
DATA
DATA
DATA
DATA
DATA
DATA
D9B-D0B
DATA N-11
DATA
DATA
DATA
DATA
DATA
DATA
Figure Data Align with Clock Sources Channel Timing
REV.
AD9218
ABSOLUTE MAXIMUM RATINGS
Analog Inputs -0.5 Digital Inputs -0.5 REFIN Inputs -0.5 Digital Output Current Operating Temperature -55C +125C Storage Temperature -65C +150C Maximum Junction Temperature 150C Maximum Case Temperature 150C qJA2 57C/W
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability. Measured 4-layer board with solid ground plane.
EXPLANATION TEST LEVELS Test Level
100% production tested.
100% production tested sample tested specified temperatures. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested 25C; guaranteed design characterization testing industrial temperature range; 100% production tested temperature extremes military devices.
ORDERING GUIDE
Model AD9218BST-40 AD9218BST-65 AD9218BST-80 AD9218BST-105 AD9218BST-RL40 AD9218BST-RL65 AD9218BST-RL80 AD9218BST-RL105 AD9218-65PCB AD9218-105PCB
Temperature Range -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
Package Description Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Profile Quad Flat Pack (1.4 thick: LQFP) Evaluation Board (Supports -40/-65 Grade) Evaluation Board (Supports -80/-105 Grade)
Package Option ST-48 ST-48 ST-48 ST-48 ST-48 ST-48 ST-48 ST-48
Table User Select Modes
User Select Options Power-Down Both Channel Power-Down Channel Only. Normal Operation (Data Align Disabled). Data Align Enabled (data from both channels available rising edge Clock Channel data delayed clock cycle.)
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9218 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD9218
CONFIGURATION
(MSB)
ENCA
AINA AINA DFS/GAIN REFINA REFOUT REFINB AINB AINB
IDENTIFIER
AD9218
VIEW (Not Scale)
(MSB)
FUNCTION DESCRIPTIONS
Number
Mnemonic AINA DFS/GAIN
Description Ground. Analog Input Channel Analog Input Channel (Complementary). Data Format Select Analog Input Gain Mode. (Low offset binary output available, supported; high twos complement output available, supported; floating offset binary output available, supported; VREF twos complement output available, supported.) Reference Voltage Input Channel Internal Reference Voltage. Reference Voltage Input Channel User Select (Refer Table User Select (Refer Table Analog Input Channel (Complementary). Analog Input Channel Analog Supply Clock Input Channel Digital Supply (2.5 Digital Output Channel (D9B MSB). Digital Output Channel (D9A MSB). Clock Input Channel
17-26 35-44
REFINA REFOUT REFINB AINB AINB ENCB D9B-D0B D0A-D9A ENCA
REV.
ENCB
AD9218
TERMINOLOGY Analog Bandwidth Harmonic Distortion, Second
analog input frequency which spectral power fundamental frequency determined analysis) reduced
Aperture Delay
ratio signal amplitude value second harmonic component, reported dBc.
Harmonic Distortion, Third
ratio signal amplitude value third harmonic component, reported dBc.
Integral Nonlinearity
delay between point rising edge ENCODE command instant which analog input sampled.
Aperture Uncertainty (Jitter)
deviation transfer function from reference line measured fractions using "best straight line" determined least-square curve fit.
Minimum Conversion Rate
sample-to-sample variation aperture delay.
Crosstalk
Coupling onto channel being driven level (-40 dBFS) signal when adjacent interfering channel driven full-scale signal.
Differential Analog Input Resistance, Differential Analog Input Capacitance, Differential Analog Input Impedance
encode rate which lowest analog signal frequency drops more than below guaranteed limit.
Maximum Conversion Rate
encode rate which parametric testing performed.
Output Propagation Delay
real complex impedances measured each analog input port. resistance measured statically capacitance differential input impedances measured with network analyzer.
Differential Analog Input Voltage Range
delay between level crossing ENCODE ENCODE level crossing respective channel's output data bit.
Noise (for Range within ADC)
peak-to-peak differential voltage that must applied converter generate full-scale response. Peak differential voltage computed observing voltage single subtracting voltage from other pin, which degrees phase. Peak-to-peak differential computed rotating input phase degrees again taking peak measurement. difference then computed between both peak measurements.
Differential Nonlinearity
VNOISE
0.001
FSdBm -SNRdBc -Signal dBFS
Where input impedance, full scale device frequency question, value particular input level, Signal signal level within reported below full scale. This value includes both thermal quantization noise.
Power Supply Rejection Ratio
deviation code width from ideal step.
Effective Number Bits
ratio change input offset voltage change power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
effective number bits (ENOB) calculated from measured based equation: ENOB SNRMEASURED 1.76 6.02
ratio signal amplitude (set below full scale) value other spectral components, including harmonics excluding
Signal-to-Noise Ratio (without Harmonics)
ENCODE Pulsewidth/Duty Cycle
Pulsewidth high minimum amount time that ENCODE pulse should left Logic state achieve rated performance; pulsewidth minimum time ENCODE pulse should left state. timing implications changing tENCH text. given clock rate, these specifications define acceptable ENCODE duty cycle.
Full-Scale Input Power
ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics
Spurious-Free Dynamic Range (SFDR)
ratio signal amplitude value peak spurious spectral component. peak spurious component harmonic. reported (i.e., degrades signal level lowered), dBFS (always related back converter full scale).
Two-Tone Intermodulation Distortion Rejection
Expressed dBm. Computed using following equation: Full Scale INPUT 0.001
ratio value either input tone value worst third order intermodulation product; reported dBc.
Two-Tone SFDR
PowerFull -Scale
Gain Error
Gain error difference between measured ideal full-scale input voltage range ADC.
ratio value either input tone value peak spurious component. peak spurious component product. reported (i.e., degrades signal level lowered), dBFS (always related back converter full scale).
REV.
AD9218
Worst Other Spur
ratio signal amplitude value worst spurious component (excluding second third harmonic) reported dBc.
Transient Response Time
Transient response defined time takes reacquire analog input after transient from above negative full scale below positive full scale.
Out-of-Range Recovery Time
Out-of-range recovery time time takes reacquire analog input after transient from above positive full scale above negative full scale, from below negative full scale below positive full scale.
EQUIVALENT CIRCUITS
Figure Reference Inputs
Figure Input
Figure Analog Input Stage
2.6k
ENCODE
Figure Input
2.6k
Figure Encode Inputs
DFS/GAIN
VREF
Figure DFS/Gain Input
Figure Reference Output Stage
Figure Digital Output Stage
REV.
AD9218 -Typical Performance Characteristics
ENCODE 105MSPS 50.1MHz -0.5dBFS 53.8dB SINAD 53.4dB -69dB -65.8dB
-100
ENCODE 40MSPS 19.75MHz -0.5dBFS 58.4dB SINAD 58.3dB -87dB -81dB
-100 52.5
FFT: MSPS, 50.1 -0.5 dBFS, Differential, Input Range
FFT: MSPS, 19.7 -0.5 dBFS, Differential, Input Range
ENCODE 80MSPS 39MHz -0.5dBFS 56.1dB SINAD 55.5dB -71.8dB -66.2dB
-100 ENCODE 105MSPS 70MHz -0.5dBFS 51.9dB SINAD 51.8dB -70.5dB -76.3dB
-100
FFT: MSPS, -0.5 dBFS, Differential, Input Range
FFT: MSPS, -0.5 dBFS, Differential, Input Range
-100 32.5 ENCODE 65MSPS 30.3MHz -0.5dBFS 56.1dB SINAD 55.9dB SFDR 72dB -83.2dB -79dB
-100 32.5 ENCODE 65MSPS 15MHz -0.5dBFS 56.4dB SINAD 55.9dB -73.9dB -71.7dB
FFT: MSPS, 30.3 -0.5 dBFS, Differential, Input Range
FFT: MSPS, -0.5 dBFS; with AD8138 Driving Inputs, Input Range
-10-
REV.
AD9218
ENCODE 31MSPS 8MHz -0.5dBFS 59.23dB SINAD 59.1dB -87dB -81dB
-100
ENCODE 31MSPS 8MHz -0.5dBFS 59dB SINAD 58.8dB -78.7dB -72.9dB
-100 15.5
15.5
FFT: MSPS, -0.5 dBFS, Differential, Input Range
FFT: MSPS, -0.5 dBFS; with AD8138 Driving Inputs, Input Range
SFDR SECOND
THIRD -100 FREQUENCY 52.5 ENCODE 105MSPS AIN1 30.1MHz -7dBFS 31.1MHz -7dBFS SFDR -67dBFS
Harmonic Distortion (Second Third) SFDR Frequency p-p, MSPS)
Two-Tone Intermodulation Distortion MHz; p-p, MSPS)
SFDR
THIRD SECOND -100 FREQUENCY ENCODE 80MSPS AIN1 29.3MHz -7dBFS 30.3MHz -7dBFS SFDR -77dBFS
Harmonic Distortion (Second Third) SFDR Frequency p-p, MSPS)
Two-Tone Intermodulation Distortion (29.3 MHz, 30.3 MHz; p-p, MSPS)
REV.
-11-
AD9218
DIFFERENTIAL DRIVE
ENCODE 65MSPS AIN1 28.1MHz -7dBFS 29.1MHz -7dBFS SFDR -72.9dBFS
SFDR
SFDR
SINGLE-ENDED DRIVE
-100 32.5
FREQUENCY
Harmonic Distortion (Second Third) SFDR Frequency MSPS)
Two-Tone Intermodulation Distortion MHz, MHz; p-p, MSPS)
SECOND THIRD
ENCODE 40MSPS AIN1 10MHz -7dBFS AIN2 11MHz -7dBFS SFDR 74dBc
SFDR
FREQUENCY
-100
Harmonic Distortion (Second Third) SFDR Frequency p-p, MSPS)
Two-Tone Intermodulation Distortion MHz, MHz; p-p, MSPS)
SFDR
SFDR
SINAD
ENCODE RATE MSPS
SINAD
ENCODE RATE
SINAD SFDR Encode Rate (fIN 10.3 MHz, MSPS Grade) -0.5 dBFS Differential, Analog Input Range
SINAD SFDR Encode Rate (AIN 10.3 MHz, MSPS Grade) -0.5 dBFS Differential, Analog Input Range
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AD9218
SFDR
SFDR
SINAD
SINAD ENCODE POSITIVE PULSEWIDTH
ENCODE POSITIVE PULSEWIDTH
SINAD SFDR Encode Pulsewidth High, -0.5 dBFS Single-Ended, Analog Input Range MSPS
SINAD SFDR Encode Pulsewidth High, -0.5 dBFS Single Ended, Analog Input Range MSPS
-105
GAIN -105
IVDD
GAIN
-65/-105 IVDD ENCODE CLOCK RATE MSPS
TEMPERATURE
IVDD Encode Rate (AIN 10.3 MHz, -0.5 dBFS), MSPS/-105 MSPS Grade
Gain Error Temperature, 10.3 MHz, MSPS Grade, -105 MSPS Grade,
1.231 1.229 1.227
SFDR
SFDR -105
1.225 1.223 1.221 1.119
SINAD
-105 SINAD -105
TEMPERATURE
TEMPERATURE
VREF Output Voltage Temperature (ILOAD
SNR, SINAD, SFDR Temperature, 10.3 MSPS Grade, -105 MSPS Grade,
REV.
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AD9218
1.50 1.45 1.40 1.35 1.30
SFDR dBFS SFDR
1.25 1.20 1.15 1.10 1.05 1.00 -1.0 -0.5 ILOAD
INPUT LEVEL dBFS LINE
VREF ILOAD
SFDR Input Level, 10.3 MSPS
-0.5 -1.0
-0.2 -0.4 -0.6
-1.5 -2.0 CODES 1024
-0.8 -1.0 CODES 1024
Typical Plot, 10.3 MSPS
Typical Plot, 10.3 MSPS
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AD9218
THEORY OPERATION
ANALOG SIGNAL SOURCE AVDD VOCM AD8138 15pF
AD9218 architecture bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine seven MSBs drive 3-bit flash. Each stage provides sufficient overlap error correction, allowing optimization comparator accuracy. input buffers differential, both sets inputs internally biased. This allows most flexible ac-coupled dc-coupled differential single-ended input modes. output staging block aligns data, carries error correction, feeds data output buffers. output buffers powered from separate supply, allowing adjustment output voltage swing. There discernible difference performance between channels.
USING AD9218 ENCODE Input
AD9218
Figure Using AD8138 Drive AD9218
Voltage Reference
high speed converter extremely sensitive quality sampling clock provided user. track/hold circuit essentially mixer. noise, distortion, timing jitter clock will combined with desired signal output. that reason, considerable care been taken design ENCODE input AD9218, user advised give commensurate thought clock source. ENCODE input fully TTL/CMOS compatible.
Digital Outputs
stable accurate 1.25 voltage reference built into AD9218 (VREF OUT). normal operation, internal reference used strapping (REFINA) (REFINB) (REFOUT). input range each channel adjusted independently varying reference voltage inputs applied AD9218. appreciable degradation performance occurs when reference adjusted full-scale range tracks reference voltage, which changes linearly.
Timing
digital outputs TTL/CMOS compatible lower power consumption. During power-down, output buffers transition high impedance state. data format selection option supports either twos complement (set high) offset binary output (set low) formats.
Analog Input
AD9218 provides latched data outputs, with five pipeline delays. Data outputs available propagation delay (tPD) after rising edge encode command (see timing diagrams). length output data lines loads placed them should minimized reduce transients within AD9218. These transients detract from converter's dynamic performance. minimum guaranteed conversion rate AD9218 MSPS. clock rates below MSPS, dynamic performance will degrade.
User Select Options
analog input AD9218 differential buffer. best dynamic performance, impedance should match. Special care taken design analog input section AD9218 prevent damage corruption data when input overdriven. nominal input range 1.024 p-p. Optimum performance obtained when part driven differentially where common-mode noise minimized even-order harmonics reduced. example driving AD9218 differentially wideband transformer ac-coupled applications shown Figure Applications that require dc-coupled differential drive accommodated using AD8138 differential output amp, shown Figure
ANALOG SIGNAL SOURCE
pins available combination operational modes. These options allow user power down both channels, excluding reference, just channel. Both modes place output buffers high impedance state. Recovery from power-down state accomplished clock cycles following power-on. other option allows user skew channel output data one-half clock cycle. other words, clocks AD9218 degrees phase, enabling data align will allow Channel output data available rising edge Clock same encode clock provided both channels data align enabled, output data from Channel will degrees phase with respect Channel same encode clock provided both channels data align disabled, both outputs delivered same rising edge clock.
AD9218
Figure Using Wideband Transformer Drive AD9218
REV.
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AD9218
APPLICATIONS
wide analog bandwidth AD9218 makes attractive variety high performance receiver encoder applications. Figure shows dual typical cost demodulator implementation cable, satellite, wireless modem receivers. excellent dynamic performance higher analog input frequencies encode rates empowers users employ direct sampling techniques. sampling eliminates simplifies analog mixer filter stages reduce total system cost power.
AD9218
wideband transformer allowing performance differential inputs measured using single-ended source. this mode, resistors R35, R33, R39, should place. Each analog input terminated board with ground. Each input ac-coupled board through capacitor on-chip resistor divider that provides bias. Single-ended performance measured bypassing transformers using connectors (Channel (Channel this mode, place resistor Channel) place (Channel Note that inverting analog inputs terminated board with (optimized differential operation). When driving board single-ended, these resistors (R1, changed provide balanced inputs. operational amplifier used connecting (Channel (Channel ac-coupling capacitors level should removed from board operational amplifier. components should placed bottom board. Bill Materials list values.
Encode
Figure Typical Demodulation Scheme
EVALUATION BOARD
AD9218 evaluation board offers easy test AD9218. provides means drive analog inputs singleendedly differentially. Differential drive tested through wideband transformer differential output operational amplifier, AD8138. encode clocks accessible on-board connectors These clocks buffered board provide clocks on-board latches. digital outputs output clocks available 40-pin connectors, board several different modes operation, shipped following configuration: Differential Analog Input Transformer Mode) Normal Operation Timing Mode Internal Voltage Reference
Power Connector
encode clock Channel uses connector Channel encode uses connector Each clock input terminated board with ground. input clocks directly buffers which drive latches. clock inputs compatible.
Voltage Reference
AD9218 internal 1.25 voltage reference. external reference each channel employed instead. evaluation board configured internal reference (use jumpers E18-E1 E17-E19). external references, connect VREFA VREFB pins power connector jumpers E20-E18 E19-E21.
Normal Operation Mode
this mode, both converters clocked same encode clock, latency five clock cycles (see timing diagrams). Signal (Pin held high signal (Pin held low. This with jumpers labeled (near analog input).
Data Align Mode
Power supplied board detachable 12-pin power strip. Optional Supply Operational Amplifier Optional Supply Operational Amplifier VREFA Optional External Reference Input VREFB Optional External Reference Input Supply Support Logic Supply Outputs Supply Analog
Analog Inputs
this mode, channel output delayed additional one-half cycle. Signals (Pin signal (Pin both held high. This with jumpers labeled (near analog input).
Data Format Select
evaluation board accepts analog input signal centered ground each analog input. connectors used respectively. These signals each drive
Data format select sets output data format gain ADC. Setting (Pin sets output format offset binary gain setting high sets output twos complement gain Removing jumper sets output data format offset binary gain setting middle selection sets output data format twos complement gain
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AD9218
Bill Materials
REFDES C3-C15, C20-C25, C27-C35 C16, C17, C18, C19, C26, C37,
Device Capacitor Capacitor Capacitor Connector 4-Pin Power Connector
Package 0603 0603 TAJD
Value Wieland 25.531.3425.0 Z5.602.5453.0 Mini-Circuits®
R1-R4, R22-R24, R5-R12, R34, R13, R15, R17, R18, R26, R29, R16, R19, R20, R32, R33, R35, R36, R38-R40 R21, U11,
HEADER40 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Transformer AD9218 74LCX821 AD9763 74LCX86 Resistor Array AD8138
0603 0603 0603 0603 0603 0603 0603 0603 ADT-1-1WT LQFP48 SO24M3 LQFP48 SO14 CTS20 SO8NB
R22, R23, R24, R30, R32, R33, R35, R36, R38, R39, R40, placed board.
Data Outputs
Outputs
digital outputs latched board LCX821s, latch outputs available 40-pin connectors Pins 23-33 (Channel Pins 23-33 (Channel latch output clocks (data ready) available (Channel (Channel data ready signal Channel aligned with Clock input connecting E43-E42 aligned with Clock input connecting E42-E33.
Each channel reconstructed on-board dual channel DAC, AD9763. This intended assist debug only. should used measure performance ADC. current output with on-board termination resistors. Figure representative output with full-scale analog input. scope setting bandwidth, termination.
(CLOCK)
(DATA)
500mV
50.0ns
380mV
2.00V 2.00V 10.0ns
40mV
Figure Output
Figure Data Output Clock 80-Pin Connector
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AD9218
VREFA VREFB
CLOCK SELECTABLE DIRECT BUFFERED
ENCA ENCODE
74LCX86
TIEA
TIEA
ENCA
CLKDACA
CLKLATA
VREFA
VREFB
OPTIONAL INPUT PATH SINGLE-ENDED AINA SINGLE-ENDED AMPINA AINA REFOUT
ENCA
ENCA
AINA AINA
AINA DIFFERENTIAL AINB DIFFERENTIAL
AINAB
DFS/GAIN REFINA
VREFA REFOUT VREFB REFINB AINBB AINB AINB AINB
AD9218
ENCB
AMPINB AINB SINGLE-ENDED
ENCB
OPTIONAL INPUT PATH SINGLE-ENDED REFINA
CLOCK SELECTABLE DIRECT BUFFERED REFINB
ENCB ENCODE TIEB
74LCX86
HOLE6
HOLE6
HOLE6
HOLE6
TIEB
ENCB
CLKLATB
CLKDACB
Figure 17a. Schematic
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REV.
74LCX821 74LCX821
REV.
CT520 VALUE HEADER40 CLKLATA CT520 VALUE CLKLATD
CT520 VALUE
Figure 17b. Schematic
-19-
CLKLATA
CT520 VALUE
HEADER40
AD9218
AD9218
OUTPUT OUTPUT R13, R12, R14, POWER-DOWN OPTION (OPTIONAL)
SLEEP
IB2IA2
FSADJ1
REFIO
FSADJ2
REFLO
ACOM
MODE
AVDD
CLK2/IQRESET
WRT1/IQWRT
WRT2/IQSEL
CLK1/IQCLK
CONNECT
DB9-P2 DB8-
DCOM1
DVDD
DCOM2
DB8-P1 DB7-P1 DB6-P1 DB5-P1 DB4-P1 DB3-P1 DB2-P1 DB1-P1 DB0-P1
DB0-P2
AD9763
DB1-P2 DB2-P2 DB3-P2 DB4-P2 DB5-P2 DB6-P2 DB7-P2
CLKDACB CLKDACB CLKDACA CLKDACA +OUT VOCM AINA VOCM +OUT
AINBB
AD8138 -OUT CONNECT AMPINA
15pF
AD8138 CONNECT -OUT
15pF
AIINAB AMPINB
AINB
Figure 17c. Schematic
-20-
REV.
AD9218
Figure Side Silkscreen
Figure Side Copper
REV.
-21-
AD9218
Figure Ground Layer
Figure Split Power Plane
-22-
REV.
AD9218
Figure Bottom Side Copper
Figure Bottom Side Silkscreen
REV.
-23-
AD9218
Troubleshooting
board does seem working correctly, following: Verify power pins. Check that jumpers correct position desired mode operation. Verify VREF 1.23
running encode clock analog inputs speeds MSPS/1 MHz) monitor LCX821 outputs, outputs, outputs toggling. AD9218 Evaluation Board provided design example customers Analog Devices, Inc. makes warranties, express, statutory, implied, regarding merchantability fitness particular purpose.
OUTLINE DIMENSIONS
48-Lead Profile Quad Flat Package [LQFP] (ST-48)
Dimensions shown millimeters
0.75 0.60 0.45
1.60
9.00
1.45 1.40 1.35
SEATING PLANE
0.20 0.09 0.08 COPLANARITY
VIEW
(PINS DOWN)
7.00
VIEW
0.15 0.05
SEATING PLANE
VIEW
ROTATED
0.50
0.27 0.22 0.17
COMPLIANT JEDEC STANDARDS MS-026BBC
Revision History
Location 7/03-Data Sheet changed from REV. REV. Page
Updated ORDERING GUIDE Changes TERMINOLOGY section Changes Figure Updated OUTLINE DIMENSIONS
-24-
REV.
C02001-0-7/03(A)
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