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Cyclone Device Handbook, Volume
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com
CIII5V1-1.0 Preliminary
Copyright 2007 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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Chapter Revision Dates
Chapter Cyclone Device Family Overview Revised: March 2007 Part number: CIII51001-1.0 Chapter Logic Elements Logic Array Blocks Cyclone Devices Revised: March 2007 Part number: CIII51002-1.0 Chapter MultiTrack Interconnect Cyclone Devices Revised: March 2007 Part number: CIII51004-1.0 Chapter Memory Blocks Cyclone Devices Revised: March 2007 Part number: CIII51005-1.0 Chapter Embedded Multipliers Cyclone Devices Revised: March 2007 Part number: CIII51006-1.0 Chapter Clock Networks PLLs Cyclone Devices Revised: March 2007 Part number: CIII51007-1.0 Chapter Cyclone Device Features Revised: March 2007 Part number: CIII51003-1.0 Chapter High-Speed Differential Interfaces Cyclone Devices Revised: March 2007 Part number: CIII51008-1.0 Chapter External Memory Interfaces Cyclone Devices Revised: March 2007 Part number: CIII51009-1.0 Chapter Configuring Cyclone Devices Revised: March 2007 Part number: CIII51010.1.0
Altera Corporation Preliminary
Chapter Revision Dates
Cyclone Device Handbook, Volume
Chapter Socketing Power-On Reset Cyclone Devices Revised: March 2007 Part number: CIII51011-1.0 Chapter Remote System Upgrade With Cyclone Devices Revised: March 2007 Part number: CIII51012-1.0 Chapter Mitigation Cyclone Devices Revised: March 2007 Part number: CIII51013-1.0 Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Cyclone Devices Revised: March 2007 Part number: CIII51014-1.0 Chapter Package Information Cyclone Devices Revised: March 2007 Part number: CIII51015-1.0
Altera Corporation
Contents
Chapter Revision Dates About this Handbook xiii
Contact Altera xiii Typographic Conventions xiii
Section Device Core
Chapter Cyclone Device Family Overview
Cyclone III: Lowest System-Cost FPGAs Features Reduced Cost Lowest-Power 65-nm FPGA Increased System Integration Cyclone Device Architecture LABs MultiTrack Interconnect Memory Blocks Embedded Multipliers Digital Signal Processing Support Features Clock Networks PLLs High-Speed Differential Interfaces 1-10 Auto-Calibrating External Memory Interfaces 1-10 Quartus Software Support 1-11 Nios World's Most Versatile Embedded Processor 1-11 Configuration 1-11 Remote System Upgrades 1-12 Socketing Power-On-Reset 1-12 Mitigation 1-13 JTAG Boundary Scan Testing 1-13 Reference Ordering Information 1-13 Document Revision History 1-14
Chapter Logic Elements Logic Array Blocks Cyclone Devices
Introduction Overview Logic Elements Features
Altera Corporation
Contents
Cyclone Device Handbook, Volume
Operating Modes Logic Array Blocks Topology Interconnects Control Signals Conclusion 2-11 Document Revision History 2-11
Chapter MultiTrack Interconnect Cyclone Devices
Introduction MultiTrack Interconnect Interconnects Column Interconnects Device Routing Local Interconnects Routing Interface Embedded Multiplier Routing Interface 3-10 Conclusion 3-11 Document Revision History 3-11
Chapter Memory Blocks Cyclone Devices
Introduction Overview Control Signals Parity Support Byte Enable Support Packed Mode Support Address Clock Enable Support Mixed Width Support Asynchronous Clear Memory Modes 4-10 Single-Port Mode 4-10 Simple Dual-Port Mode 4-12 True Dual-Port Mode 4-13 Shift Register Mode 4-15 Mode 4-17 FIFO Buffer Mode 4-17 Clocking Modes 4-17 Independent Clock Mode 4-18 Input/Output Clock Mode 4-20 Read/Write Clock Mode 4-23 Single-Clock Mode 4-25 Design Considerations 4-28 Read-During-Write Operations 4-28 Conflict Resolution 4-31 Power-Up Conditions Memory Initialization 4-32 Power Management 4-32
Altera Corporation
Contents
Conclusion 4-32 Document Revision History 4-32
Chapter Embedded Multipliers Cyclone Devices
Introduction Embedded Multiplier Block Overview Architecture Input Registers Multiplier Stage Output Registers Operational Modes 18-Bit Multipliers 9-Bit Multipliers Software Support 5-10 Conclusion 5-11 Document Revision History 5-11
Chapter Clock Networks PLLs Cyclone Devices
Introduction Clock Networks Global Clock Network Clock Control Block Global Clock Network Clock Source Generation Global Clock Network Power Down 6-10 Clkena Signals 6-11 PLLs Cyclone Devices 6-13 Cyclone 6-16 Cyclone Hardware Overview 6-16 Cyclone Software Overview 6-19 Clock Feedback Modes 6-21 Source-Synchronous Mode 6-21 Compensation Mode 6-22 Normal Mode 6-23 Zero Delay Buffer (ZDB) Mode 6-23 Hardware Features 6-24 Clock Multiplication Division 6-24 Post-scale Counter Cascading 6-25 Programmable Duty Cycle 6-26 Control Signals 6-26 Clock Switchover 6-27 Manual Override 6-30 Phase-Shift Implementation 6-33 Cascading 6-35 Reconfiguration 6-37 Reconfiguration Hardware Implementation 6-37 Spread-Spectrum Clocking 6-47 Specifications 6-47
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Contents
Cyclone Device Handbook, Volume
Board Layout VCCA GNDA VCCD Conclusion Document Revision History
6-47 6-47 6-48 6-49 6-50
Section External Memory Interfaces
Chapter Cyclone Device Features
Introduction Overview Cyclone Element Element Features Programmable Current Strength Slew Rate Control 7-11 Open-Drain Output 7-11 Hold 7-12 Programmable Pull-Up Resistor 7-12 Programmable Delay 7-13 PCI-Clamp Diode 7-14 LVDS Transmitter Programmable Pre-Emphasis 7-14 On-Chip Termination Support 7-15 On-Chip Termination With Calibration 7-15 On-Chip Termination Without Calibration 7-17 Standards 7-20 Termination Scheme Standards 7-22 Voltage-Referenced Standard Termination 7-22 Differential Standard Termination 7-24 Banks 7-26 High-Speed Differential Interfaces 7-31 External Memory Interfacing 7-32 Placement Guidelines 7-32 Differential Placement Guidelines 7-32 VREF Placement Guidelines 7-34 Guidelines 7-37 Conclusion 7-38 Document Revision History 7-38
Chapter High-Speed Differential Interfaces Cyclone Devices
Introduction Cyclone High-Speed Banks Cyclone High-Speed
viii
Altera Corporation
Contents
Interface High-Speed Standards Support LVDS Standard Support Cyclone Devices RSDS Standard Support Cyclone Devices mini-LVDS Standard Support Cyclone Devices 8-12 PPDS Standard Support Cyclone Devices 8-14 LVPECL Support Cyclone Devices 8-16 Differential SSTL Standard Support Cyclone Devices 8-17 Differential HSTL Standard Support Cyclone Devices 8-18 Feature Dedicated Output Buffer 8-19 High-Speed Timing Cyclone Devices 8-20 Design Guidelines 8-22 Differential Placement Guidelines 8-22 Board Design Considerations 8-22 Software Overview 8-23 Conclusion 8-24 Document Revision History 8-24
Chapter External Memory Interfaces Cyclone Devices
Introduction Cyclone Memory Support Overview Cyclone Memory Interfaces Support Data Data Clock/Strobe Pins Optional Parity, Pins 9-13 Address Control/Command Pins 9-14 Memory Clock Pins 9-14 Cyclone Memory Interfaces Features 9-15 Input Registers 9-15 Output Registers 9-16 On-Chip Termination (OCT) 9-18 9-18 Conclusion 9-19 Document Revision History 9-19
Section III. Configuration, Socketing, Remote Upgrades, Mitigation
Chapter Configuring Cyclone Devices
Introduction Configuration Devices Configuration Schemes Configuration File Format 10-1 10-2 10-2 10-7
Altera Corporation
Contents
Cyclone Device Handbook, Volume
Configuration Features 10-8 Configuration Data Decompression 10-9 Remote System Upgrade 10-11 Configuration Requirements 10-12 Power-On Reset Circuit 10-12 Configuration JTAG Requirements 10-13 Active Serial Configuration (Serial Configuration Devices) 10-14 Single Device Configuration 10-15 Multi-Device Configuration 10-20 Configuring Multiple Cyclone Devices with Same Design 10-22 Estimating Configuration Time 10-26 Programming Serial Configuration Devices 10-26 Active Parallel Configuration (Supported Flash Memories) 10-29 Configuration Supported Flash Memories 10-31 Single Device Configuration 10-33 Multi-Device Configuration 10-38 Configuring With Multiple Masters 10-42 Estimating Configuration Time 10-43 Programming Parallel Flash Memories 10-44 Passive Serial Configuration 10-46 Configuration Using Device External Host 10-46 Configuration Using Microprocessor 10-55 Configuration Using Download Cable 10-56 Fast Passive Parallel Configuration 10-61 Configuration Using Device External Host 10-62 Configuration Using Microprocessor 10-70 JTAG Configuration 10-70 STAPL 10-78 Configuring Cyclone Devices with JRunner 10-79 Combining JTAG Active Serial Configuration Schemes 10-79 Cyclone JTAG Instructions 10-81 Reconfiguration 10-81 Overriding Internal Oscillator 10-85 Changing Start Boot Address Flash 10-86 Device Configuration Pins 10-87 Conclusion 10-96 Document Revision History 10-96
Chapter Socketing Power-On Reset Cyclone Devices
Introduction Cyclone Hot-Socketing Specifications Devices Driven Before Power-Up Pins Remain Tri-Stated During Power-Up Hot-Socketing Feature Implementation Cyclone Devices Power-On Reset Circuitry Wake-Up Time Cyclone Devices Conclusion 11-1 11-1 11-2 11-2 11-3 11-5 11-5 11-7
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Contents
Document Revision History 11-8
Chapter Remote System Upgrade With Cyclone Devices
Introduction 12-1 Functional Description 12-1 Configuration Image Types 12-5 Remote System Upgrade Mode 12-5 Overview 12-5 Remote Update Mode 12-5 Dedicated Remote System Upgrade Circuitry 12-8 Remote System Upgrade Registers 12-10 Remote System Upgrade State Machine 12-15 User Watchdog Timer 12-16 Interface Signals between Remote System Upgrade Circuitry Cyclone Device Logic Array 12-17 Quartus Software Support 12-20 altremote_update Megafunction 12-20 Remote System Upgrade Atom 12-20 Conclusion 12-20 Document Revision History 12-21
Chapter Mitigation Cyclone Devices
Introduction 13-1 Error Detection Fundamentals 13-1 Configuration Error Detection 13-2 User Mode Error Detection 13-2 Automated Single Event Upset Detection 13-3 Error Detection Description 13-4 CRC_ERROR 13-4 Error Detection Block 13-4 Error Detection Registers 13-5 Error Detection Timing 13-6 Software Support 13-8 Recovering from Errors 13-9 Conclusion 13-10 Document Revision History 13-11
Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Cyclone Devices
Introduction 14-1 IEEE Std. 1149.1 Architecture 14-2 IEEE Std. 1149.1 Boundary-Scan Register 14-4 Boundary-Scan Cells Cyclone Device 14-5 IEEE Std. 1149.1 Operation Control 14-7 SAMPLE/PRELOAD Instruction Mode 14-13 EXTEST Instruction Mode 14-14 BYPASS Instruction Mode 14-16
Altera Corporation
Contents
Cyclone Device Handbook, Volume
IDCODE Instruction Mode USERCODE Instruction Mode CLAMP Instruction Mode HIGHZ Instruction Mode CONFIG_IO Instruction Mode Voltage Support JTAG Chain Using IEEE Std. 1149.1 Circuitry Configured Devices Disabling IEEE Std. 1149.1 Circuitry Guidelines IEEE Std. 1149.1 Boundary-Scan Testing Boundary-Scan Description Language (BSDL) Support Conclusion References Document Revision History
14-17 14-18 14-18 14-18 14-19 14-19 14-20 14-21 14-21 14-22 14-23 14-23 14-23 14-23
Section Packaging Information
Chapter Package Information Cyclone Devices
Introduction Thermal Resistance Package Outlines Document Revision History 15-1 15-2 15-2 15-2
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About this Handbook
This handbook provides comprehensive information about Altera® Cyclone® family devices.
Contact Altera
Information Type
Technical support
most up-to-date information about Altera products, Altera world-wide site www.altera.com. technical support this product, www.altera.com/mysupport. additional information about Altera products, consult sources shown below. Canada
www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. 5:00 p.m. Pacific Time)
Other Locations
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Product literature Altera literature services Non-technical customer service site
www.altera.com literature@altera.com (800) 767-3753
ftp.altera.com
Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design.
Italic Type with Initial Capital Letters
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xiii Preliminary
Typographic Conventions
Cyclone Device Handbook, Volume
Visual
Italic type
Meaning
Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters "Subheading Title"
Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Courier type
etc.
Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution indicates required information that needs special consideration understanding should read prior starting continuing with procedure process. warning indicates information that should read prior starting continuing procedure processes. angled arrow indicates should press Enter key. feet direct more information particular topic.
Preliminary
Altera Corporation Preliminary
Section Device Core
This section provides complete overview features relating Stratix® device family, which most architecturally advanced, high performance, power FPGA market place. This section includes following chapters:
Chapter Cyclone Device Family Overview Chapter Logic Elements Logic Array Blocks Cyclone Devices Chapter MultiTrack Interconnect Cyclone Devices Chapter Memory Blocks Cyclone Devices Chapter Embedded Multipliers Cyclone Devices Chapter Clock Networks PLLs Cyclone Devices
Revision History
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears full handbook.
Altera Corporation- Preliminary
Section
Device Core
Cyclone Device Handbook, Volume
Section
Altera Corporation
Cyclone Device Family Overview
CIII51001-1.0
Cyclone III: Lowest System-Cost FPGAs Features
Cyclone® FPGA family offered Altera® cost-optimized, memory-rich FPGA family. Cyclone FPGAs built TSMC's 65-nm low-power (LP) process technology with additional silicon optimizations software features minimize power consumption. With this third generation Cyclone series, Altera broadens number high volume, cost-sensitive applications that benefit from FPGAs. Cyclone devices designed offer low-power consumption increased system integration reduced cost.
Reduced Cost
Cyclone devices deliver lowest device system costs based following facts:
Staggered ring lower area Wide range cost packages Support low-cost serial flash commodity parallel flash devices configuration
Lowest-Power 65-nm FPGA
Cyclone devices lowest-power 65-nm FPGAs designed TSMC's 65-nm power process Altera's power aware design flow. Cyclone devices support hot-socketing operation, hence, unused banks powered down when devices which they connected turned off. Cyclone device power operation:
Extends battery life portable handheld applications Enables operation thermally challenged environments Eliminates reduces cooling system costs
Increased System Integration
Cyclone devices provide increased system integration offering following features:
Altera Corporation-Preliminary March 2007
Density 119,088 logic elements (LEs) memory Mbits. Table page 1-3. High memory logic ratio embedded applications
Preliminary
Cyclone Device Family Overview
Highest multiplier-to- logic ratio industry every density; multiplier performance High count, range density devices user constrained applications four phase-locked loops (PLLs) provide robust clock management synthesis device clocks, external system clocks, interfaces five outputs Cascadable save I/Os, ease routing, reduce number external reference clocks needed Dynamically reconfigurable change phase shift, frequency multiplication/division, input frequency in-system without reconfiguring device Support high-speed external memory interfaces including DDR, DDR2, SDRAM, QDRII SRAM Mbps Auto-calibrating physical layer (PHY) feature accelerates timing closure process eliminates variations over process, voltage temperature (PVT) DDR, DDR2, SDRAM, QDRII SRAM interfaces user pins arranged banks that support wide range industry standards Mbps receive Mbps transmit LVDS communications LVDS, RSDS, mini-LVDS PPDS transmission without external resistors Supported standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS, PPDS; Express Serial Rapid supported using external devices Multi-value on-chip termination (OCT) support with calibration feature eliminate variations over Adjustable slew rates improve signal integrity Support low-cost Altera serial flash commodity parallel flash configuration devices from Intel Spansion Remote system upgrade feature without requiring external controller Dedicated Cyclic Redundancy Code (CRC) checker circuitry detect single event upset (SEU) conditions Nios® embedded processors Cyclone devices offer cost custom-fit embedded processing solutions Broad portfolio pre-built verified intellectual property cores from Altera Altera Megafunction Partners Program (AMPPSM) partners
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Features
Table displays Cyclone device family features.
Table 1-1. Cyclone FPGA Device Family Features Feature
Logic Elements Memory (Kbits) Multipliers PLLs Global Clock Networks
EP3C5
5,136
EP3C10 EP3C16
10,320 15,408
EP3C25 EP3C40
24,624 39,600 1,134
EP3C55
55,856 2,340
EP3C80
81,264 2,745
EP3C120
119,088 3,888
Cyclone devices support vertical migration within same package. Vertical migration means that migrate devices whose dedicated pins, configuration pins, power pins same given package across device densities. This allows designers optimize density cost design evolves. Table lists Cyclone device package options user counts. highest count family delivered EP3C40.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Cyclone Device Family Overview
Table 1-2. Cyclone FPGA Package Options Counts Note (1), (2), 144-pin Plastic Enhanced Quad Flat Pack (EQFP)
Device
240-pin Plastic Quad Flat Pack (PQFP)
256-pin FineLine Ball-Grid Array (FBGA)
256-pin Ultra FineLine Ball-Grid Array (UBGA)(6)
324-pin 484-pin FineLine FineLine Ball-Grid Ball-Grid Array Array (FBGA) (FBGA)
484-pin Ultra FineLine Ball-Grid Array (UBGA)(6)
780-pin FineLine Ball-Grid Array (FBGA)
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
Note Table 1-2:
more information Device Packaging Specifications, refer support section Altera website. numbers maximum counts (including clock input pins) supported device-package combination affected configuration scheme selected device. packages available lead-free leaded options. EP3C40 device F780 package supports restricted vertical migration. Maximum user restricted I/Os enable migration EP3C120 using voltage referenced standards. using voltage referenced standards maximum number I/Os increased. E144 package exposed bottom package. This exposed ground that must connected ground plane your PCB. This exposed used electrical connectivity thermal purposes. UBGA packages will supported starting Quartus v7.1 except UBGA packages EP3C16 which will supported starting Quartus v7.2
Table lists Cyclone FPGA package sizes.
Table 1-3. Cyclone FPGA Package Sizes Dimensions
Pitch (mm) Nominal Area (mm2)
144-pin EQFP
240-pin PQFP
1197
256-pin FBGA
256-pin UBGA
324-pin FBGA
484-pin FBGA
484-pin UBGA
780-pin FBGA
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Cyclone Device Architecture
Table 1-3. Cyclone FPGA Package Sizes Dimensions
Length Width Height (mm)
144-pin EQFP
240-pin PQFP
34.6 34.6 4.10
256-pin FBGA
256-pin UBGA
324-pin FBGA
484-pin FBGA
484-pin UBGA
780-pin FBGA
1.60
1.55
2.20
2.20
2.60
2.20
2.60
Cyclone devices available three speed grades: with being fastest. Table shows Cyclone device speed grade offerings.
Table 1-4. Cyclone Devices Speed Grades Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
144-pin EQFP
240-pin PQFP
256-pin FBGA
256-pin UBGA
324-pin FBGA
484-pin FBGA
484-pin UBGA
780-pin FBGA
Cyclone Device Architecture
Cyclone FPGAs include customer-defined feature optimized cost-sensitive applications offer wide range density, memory, embedded multiplier, I/O, packaging options. Cyclone FPGAs support numerous external memory interfaces protocols common high volume applications. Figure shows floor plan view Cyclone device architecture.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Cyclone Device Family Overview
Figure 1-1. Cyclone Device Architecture Overview Note
Staggered Ring
M-bit Embedded Memory Blocks
Embedded Multipliers High-Throughput 119,088
User With Integrated
200-MHz Memory Interfaces
Dynamically Configurable PLLs
Note Figure 1-1:
EP3C5 EP3C10 have only PLLs
LABs
logic array block (LAB) consists logic elements (LEs) LABwide control block. smallest unit logic Cyclone device architecture. Each four inputs, 4-input Look-Up-Table (LUT), register, output logic. 4-input function generator that implement function four variables.
more information, refer Logic Elements (LE) Logic Array Blocks (LAB) chapter Cyclone Device Handbook.
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Cyclone Device Architecture
MultiTrack Interconnect
Cyclone device architecture, interconnections between LEs, LABs, memory blocks, embedded multipliers, device pins provided MultiTrackinterconnect structure which fabric routing wires. MultiTrack interconnect structure consists performance-optimized routing lines different speeds used interand intra-design block connectivity. Quartus® software automatically optimizes designs placing critical path fastest interconnects.
more information, refer MultiTrack Interconnect chapter Cyclone Device Handbook.
Memory Blocks
Each Cyclone FPGA memory block provides kbits on-chip memory capable operation MHz. embedded memory structure consists columns memory blocks that configured RAM, first-in first-out (FIFO) buffers, ROM. Cyclone memory blocks optimized applications such high throughput packet processing, high definition (HD) line buffers video processing functions, embedded processor program data storage. Quartus software allows take advantage memory blocks instantiating memory using dedicated megafunction wizard, inferring memory directly from VHDL Verilog source code.
Table 1-5. Cyclone Memory Modes Port Mode
Single Port Simple Dual Port True Dual Port
Port Width Configuration
x16, x18, x16, x18,
more information, refer Memory Blocks chapter Cyclone Device Handbook.
Embedded Multipliers Digital Signal Processing Support
Cyclone devices offer embedded multiplier blocks support following modes: individual 18-bit x18-bit multiplier block, individual 9-bit 9-bit multipliers block. Quartus software includes megafunctions that used control mode
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Cyclone Device Family Overview
operation embedded multiplier blocks based user parameter settings. Multipliers also inferred directly from VHDL Verilog source code. addition embedded multipliers, Cyclone FPGAs include combination on-chip resources external interfaces that make them ideal increase performance, reduce system cost, lower power consumption digital signal processing (DSP) systems. Cyclone FPGAs used alone device co-processors improve price-to-performance ratios systems. Cyclone FPGA system design support includes following features:
cores; which include: Common processing functions such finite impulse response (FIR), fast Fourier transform (FFT), numerically controlled oscillator (NCO) functions Suite common video image processing functions Complete reference designs end-market applications Builder interface tool between MathWorks Simulink® MATLAB® design environment, Quartus software development kits
more information, refer Embedded Multipliers chapter Cyclone Device Handbook.
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Cyclone Device Architecture
Features
Cyclone devices contain eight banks. banks support single-ended differential standards listed Table 1-6.
Table 1-6. Cyclone FPGA Standards Support Note Type
Single-Ended
Standard
LVTTL LVCMOS SSTL HSTL PCI-X SSTL HSTL LVPECL LVDS mini-LVDS RSDS PPDS
Differential
Note Table 1-6:
Express Serial Rapid supported using external device.
Cyclone device also supports programmable hold, programmable pull-up pull-down resistors, programmable slew rate control optimize signal integrity, socketing. Cyclone devices support calibrated on-chip series termination (OCT) driver impedance matching (Rs) single-ended standards with calibration block side.
more information, refer Device Features chapter Cyclone Device Handbook.
Clock Networks PLLs
Cyclone FPGAs include global clock networks. Global clock signals driven from dedicated clock pins, dual purpose clock pins, user logic, phase-locked loops. Cyclone FPGAs include four PLLs with five outputs provide robust clock management synthesis. PLLs used device clock management, external system clock management, interfaces. Cyclone PLLs dynamically reconfigured enable auto-calibration external memory interfaces while device operation. This feature also enables support multiple input source
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Cyclone Device Family Overview
frequencies corresponding multiplication, division, phase shift requirements. PLLs Cyclone devices cascaded generate internal clocks external clocks output pins from single external clock source.
specifications information, please refer Switching Characteristics Clock Networks PLLs chapters Cyclone Device Handbook.
High-Speed Differential Interfaces
Cyclone FPGAs support high-speed differential interfaces, such LVDS, mini-LVDS, RSDS, PPDS. These high-speed standards Cyclone FPGAs ideal low-cost applications providing high data throughput using relatively small number pins. device banks contain LVDS receivers that operate Mbps data rates. Dedicated differential output drivers left right banks transmit Mbps data rates without need external resistors save board space simplify routing. bottom banks support differential transmit functionality with addition external resistor network Mbps data rates.
more information, refer High-Speed Differential Interfaces chapter Cyclone Device Handbook.
Auto-Calibrating External Memory Interfaces
Cyclone devices support common memory types including DDR, DDR2, SDRAM, QDRII SRAM. DDR2 SDRAM memory interfaces support data rates Mbps. Memory interfaces supported sides Cyclone FPGA. Cyclone FPGA contains features such on-chip termination, output registers, 36-bit programmable group widths enable rapid robust implementation different memory standards. auto-calibrating megafunction available Quartus software memory interface PHYs. megafunction optimized take advantage Cyclone structure, simplify timing closure requirements, take advantage Cyclone dynamic reconfiguration feature calibrate over process, voltage temperature changes.
more information, refer External Memory Interfaces chapter Cyclone Device Handbook.
1-10 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Quartus Software Support
Quartus software number design software performance productivity. industry's only complete design solution CPLDs, FPGAs, structured ASICs. Quartus software includes integrated development environment accelerate system-level design seamless integration with leading third-party software tools flows. Cyclone FPGAs supported both subscription free Quartus Edition software.
Quartus Handbook more information Quartus software features.
Nios World's Most Versatile Embedded Processor
Cyclone devices support Nios® embedded processor which allows implement custom-fit embedded processing solutions. Cyclone devices also expand peripheral set, memory, I/O, performance embedded processors. Single multiple Nios embedded processors designed into Cyclone device provide additional co-processing power even replace existing embedded processors your system. Using Cyclone Nios together allows low-cost, high-performance embedded processing solutions which allow extend your product's life cycle improve time market over standard product solutions.
Configuration
Cyclone devices SRAM cells store configuration data. Configuration data downloaded Cyclone devices each time device powers Low-cost configuration options include Altera EPCS family serial flash devices, well parallel flash configuration options using commodity Intel Spansion devices. These options provide flexibility general-purpose applications ability meet
Cyclone Device Family Overview
specific configuration wake time requirements applications, such requirement many automotive applications. Wake time adjusted choosing configuration option selecting fast standard power-on-reset time.
more information, refer Configuring Cyclone Devices chapter Cyclone Device Handbook.
Remote System Upgrades
Cyclone devices offer remote system upgrade without external controller. Remote system upgrade capability Cyclone devices allows deployment system upgrades from remote location. Soft logic (either Nios embedded processor user logic) implemented Cyclone device download configuration image from remote location, store configuration memory, direct dedicated remote system upgrade circuitry initiate reconfiguration cycle. dedicated circuitry performs error detection during after configuration process, recover from error condition reverting back safe configuration image, provides error status information. This feature supports serial parallel flash configuration topologies.
more information, refer Remote System Upgrade chapter Cyclone Device Handbook.
Socketing Power-On-Reset
Cyclone devices feature socketing, also known plug-in swap, power sequencing support without external devices. insert remove board populated with more Cyclone devices during system operation without causing undesirable effects running system board that inserted into system. socketing feature allows FPGAs printed circuit boards (PCBs) that also contain mixture devices. Cyclone devices socketing feature eliminates power-up sequence requirements other devices board proper FPGA operation.
more information, refer Socketing Power-On Reset chapter Cyclone Device Handbook.
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Altera Corporation-Preliminary March 2007
Reference Ordering Information
Mitigation
Cyclone devices offer built-in error detection circuitry detect data corruption soft errors configuration random-access memory (CRAM) cells. This feature allows CRAM contents read verified match configuration-computed value. Quartus software activates Cyclone built-in 32-bit checker.
more information, refer Mitigation chapter Cyclone Device Handbook.
JTAG Boundary Scan Testing
Cyclone devices support JTAG IEEE Std. 1149.1 specification. Boundary-Scan Test (BST) architecture offers capability test connections without using physical test probes capture functional data while device operating normally. Boundary-scan cells Cyclone device force signals onto pins capture data from pins logic array signals. Forced test data serially shifted into boundary-scan cells. Captured data serially shifted externally compared expected results. addition BST, IEEE Std. 1149.1 controller Cyclone device in-circuit reconfiguration (ICR).
more information, refer IEEE 1149.1 (JTAG) Boundary-Scan Testing chapter Cyclone Device Handbook. Figure describes ordering codes Cyclone devices.
Reference Ordering Information
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1-13 Cyclone Device Handbook, Volume
Cyclone Device Family Overview
Figure 1-2. Cyclone Device Packaging Ordering Information
EP3C Family Signature EP3C: Cyclone Optional Suffix Indicates specific device options shipment method. Engineering sample Lead-free devices Speed Grade (fastest) Operating Temperature Commercial temperature Industrial temperature -40° 100° Count Number pins particular package:
Device Type
Package Type Plastic Enhanced Quad Flat Pack (EQFP) Plastic Quad Flat Pack (PQFP) FineLine Ball-Grid Array (FBGA) Ulltra FineLine Ball-Grid Array (UBGA)
Document Revision History
Table shows revision history this document.
Table 1-7. Document Revision History Date Document Version
March 2007 v1.0
Changes Mode
Initial Release
Summary Changes
1-14 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Logic Elements Logic Array Blocks Cyclone Devices
CIII51002-1.0
Introduction
This chapter contains feature definitions logic elements (LEs) logic array blocks (LABs). provides details works, LABs contain groups LEs, LABs interface with other blocks Cyclone® devices. logic array consists LABs, with each LAB. small unit logic providing efficient implementation user logic functions. LABs grouped into rows columns across device. Cyclone devices range from 5,136 119,088 LEs. smallest unit logic Cyclone architecture, compact provides advanced features with efficient logic utilization. Each features:
Overview
Logic Elements
four-input look-up table (LUT), which implement function four variables programmable register carry chain connection register chain connection ability drive types interconnects: local, row, column, register chain, direct link interconnects Support register packing Support register feedback
Figure shows Cyclone
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Preliminary
Logic Elements Logic Array Blocks Cyclone Devices
Figure 2-1. Cyclone
Register Chain Routing from previous Carry-In
Register Bypass LAB-Wide Synchronous LAB-Wide Programmable Synchronous Load Register Clear
data data data data
Look-Up Table Carry Chain (LUT)
Synchronous Load Clear Logic
Row, Column, Direct Link Routing
CLRN
labclr1 labclr2 Chip-Wide Reset (DEV_CLRn) Asynchronous Clear Logic
Row, Column, Direct Link Routing
Local Routing
Register Feedback
Clock Clock Enable Select Carry-Out labclk1 labclk2 labclkena1 labclkena2
Register Chain Output
Features
configure each LE's programmable register operation. Each register data, clock, clock enable, clear inputs. Signals that global clock network, general-purpose pins, internal logic drive register's clock clear control signals. Either general-purpose pins internal logic drive clock enable. combinational functions, output bypasses register drives directly outputs. Each three outputs that drive local, row, column routing resources. register output drive these three outputs independently. outputs drive column direct link routing connections drives local interconnect resources. This allows drive output while register drives another output. This feature, called register packing, improves device utilization because device register unrelated
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Logic Elements
functions. When using register packing, LAB-wide synchronous load control signal available. Refer "LAB Control Signals" section more information synchronous load control signal. Another special packing mode allows register output feed back into same that register packed with fan-out LUT, providing another mechanism improved fitting. also drive registered unregistered versions output. addition three general routing outputs, within have register chain outputs. Register chain outputs allow registers within same cascade together. register chain output allows LUTs used combinational functions registers used unrelated shift register implementation. These resources speed connections between LABs while saving local interconnect resources. Figure shows register cascading among Cyclone III.
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Figure 2-2. Register Cascade
Register chain connection
general local routing
Register chain output
general local routing
Register chain output
general local routing
Register chain output
carry chain connect other LUTs from different LEs. carry chain feature achieved connecting carry-out next carry-in. carry chains span more than using carry-in carry-out. Figure shows carry chains.
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Operating Modes
Figure 2-3. Carry Chains
data1 data2 from cout previous data4
cout
data1 data2 data4
cout
data1 data2 data4
cout
Operating Modes
Cyclone operates normal arithmetic mode. operating modes resources differently. each mode, there available inputs These inputs include four data inputs from local interconnect, carry-in from previous carry-chain register chain connection. Each input directed different destinations implement desired logic function. LABwide signals provide clock, asynchronous clear, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Quartus® software, conjunction with parameterized functions such library parameterized modules (LPM) functions, automatically chooses appropriate mode common functions such counters, adders, subtractors, arithmetic functions. required, also create special-purpose functions that specify which operating mode optimal performance.
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Normal Mode
normal mode suitable general logic applications combinational functions. normal mode, four data inputs from local interconnect inputs four-input (see Figure 2-4). Quartus Compiler automatically selects carry-in (cin) data3 signal inputs LUT. normal mode support packed registers register feedback. Figure 2-4. Normal Mode
Register Chain Connection Packed Register Input sload sclear (LAB Wide) (LAB Wide)
data1 data2 data3 (from cout previous data4
CLRN
Row, Column, Direct Link Routing Row, Column, Direct Link Routing
Four-Input
clock (LAB Wide) (LAB Wide) aclr (LAB Wide)
Local Routing
Register Bypass
Register Feedback
Register Chain Output
Arithmetic Mode
arithmetic mode ideal implementing adders, counters, accumulators, comparators. arithmetic mode implements 2-bit full adder basic carry chain (Figure 2-5). arithmetic mode drive registered unregistered versions output. Register feedback register packing supported when used arithmetic mode.
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Operating Modes
Figure 2-5. Arithmetic Mode
Packed Register Input
Register chain connection sload sclear (LAB Wide) (LAB Wide)
data4
data1 data2
Three-Input
Row, column, direct link routing Row, column, direct link routing
data3
(from cout previous
Three-Input
CLRN
clock (LAB Wide) (LAB Wide) aclr (LAB Wide)
Local routing
cout
Register chain output
Register Bypass
Register Feedback
Quartus Compiler automatically creates carry chain logic during design processing, create manually during design entry. Parameterized functions such functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than automatically linking LABs same column. enhanced fitting, long carry chain runs vertically, which allows fast horizontal connections memory blocks embedded multipliers through direct link interconnects. example, design long carry chain column next column memory blocks, output feed adjacent memory block through direct link interconnect. Whereas carry chains horizontally, next column memory blocks would other column interconnects drive memory block. carry chain continues full column.
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Logic Elements Logic Array Blocks Cyclone Devices
Logic Array Blocks
Topology
Each consists following:
control signals carry chains Register chains Local interconnect
local interconnect transfers signals between same LAB. Register chain connections transfer output register adjacent register within LAB. Quartus Compiler places associated logic within adjacent LABs, allowing local, register chain connections performance area efficiency. Figure shows Cyclone LAB. Figure 2-6. Cyclone Structure
Interconnect
Column Interconnect
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect adjacent block
Direct link interconnect adjacent block
Local Interconnect
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Control Signals
Interconnects
local interconnect driven column interconnects outputs within same LAB. Neighboring LABs, PLLs, blocks, embedded multipliers from left right also drive local interconnect through direct link connection. direct link connection feature minimizes column interconnects, providing higher performance flexibility. Each drive through fast local direct link interconnects. Figure shows direct link connection. Figure 2-7. Direct Link Connection
Direct link interconnect from left LAB, memory block, embedded multiplier, PLL, output Direct link interconnect from right LAB, memory block, embedded multiplier, PLL, output
Direct link interconnect left Local Interconnect
Direct link interconnect right
Control Signals
Each contains dedicated logic driving control signals LEs. control signals include:
clocks clock enables asynchronous clears synchronous clear synchronous load
eight control signals time. Register packing synchronous load cannot used simultaneously. Each have four non-global control signals. additional control signals long they global signals.
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Synchronous clear load signals useful implementing counters other functions. synchronous clear synchronous load signals LAB-wide signals that affect registers LAB. Each clocks clock enable signals. Each LAB's clock clock enable signals linked. example, particular using labclk1 signal also uses labclkena1. uses both rising falling edges clock, also uses both LAB-wide clock signals. Deasserting clock enable signal turns LAB-wide clock. clocks [5.0] local interconnect generate LAB-wide control signals. MultiTrackinterconnect's inherent skew allows clock control signal distribution addition data distribution. Figure shows control signal generation circuit. Figure 2-8. LAB-Wide Control Signals
Dedicated Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclkena1 labclkena2 labclr1 synclr
labclk1
labclk2
syncload
labclr2
LAB-wide signals control logic register's clear signal. directly supports asynchronous clear function. Each supports asynchronous clear signals (labclr1 labclr2). LAB-wide asynchronous load signal control logic register's preset signal available. register preset achieved using gate push-back technique. Cyclone devices only support either preset asynchronous clear signal.
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Conclusion
addition clear port, Cyclone devices provide chip-wide reset (DEV_CLRn) that resets registers device. option before compilation Quartus software controls this pin. This chip-wide reset overrides other control signals.
Conclusion
Cyclone device LABs enable keep pace with increasing design complexity using low-cost FPGA device family. Quartus software makes easy implement Cyclone device designs LABs, making process invisible you, thus freeing from complexity LABs. Table shows revision history this document.
Document Revision History
Table 2-1. Document Revision History Date Document Version
March 2007 v1.0
Changes Made
Initial Release
Summary Changes
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Logic Elements Logic Array Blocks Cyclone Devices
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MultiTrack Interconnect Cyclone Devices
CIII51004-1.0
Introduction
This Cyclone® handbook chapter, MultiTrack Interconnect Cyclone Devices, provides in-depth information about routing architecture Cyclone devices. This document explains connections between each functional block Cyclone devices. Cyclone device architecture, connections between LEs, memory blocks, embedded multipliers, device pins provided MultiTrack interconnect structure with DirectDrivetechnology. MultiTrack interconnect consists continuous, performance-optimized routing lines different speeds used inter- intra-design block connectivity. Quartus® Compiler automatically places critical paths faster interconnects improve design performance. DirectDrive technology deterministic routing technology that ensures identical routing resource usage function regardless placement within device. MultiTrack interconnect DirectDrive technology simplify integration stage block-based designing eliminating re-optimization cycles that typically follow design changes additions. MultiTrack interconnect consists (direct link, R24) column (register chain, C16) interconnects that span fixed distances. routing structure with fixed-length resources devices allows predictable repeatable performance when migrating through different device densities.
MultiTrack Interconnect
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Interconnects
interconnects route signals from logic array blocks (LABs), phase-locked loops (PLLs), memory blocks, embedded multipliers within same row. These resources include:
Direct link interconnects between LABs adjacent blocks interconnects traversing four blocks right left interconnects high-speed access across length device
direct link interconnect allows blocks drive into local interconnect left right neighbors. direct link interconnect provides fast communication between adjacent blocks without using interconnect resources. interconnects span four LABs, three LABs, memory block, three LABs embedded multiplier right left source LAB. These resources used fast connections four-LAB region. Every interconnects drive either left right. Figure shows interconnect connections from LAB. interconnects drive driven LABs, memory blocks, embedded multipliers, PLLs, input/output elements (IOEs). interfacing, primary neighbor (see Figure 3-1) drive given interconnect. interconnects that drive right, primary right neighbor drive interconnect. interconnects that drive left, primary left neighbor drive interconnect. interconnects drive other interconnects extend range LABs they drive. Additionally, interconnects drive interconnects, interconnects connections from another.
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Figure 3-1. Interconnect Connections Notes (1), (2),
Adjacent Drive onto Another LAB's Interconnect Interconnect Driving Left Column Interconnects Interconnect Driving Right
Neighbor
Primary
Neighbor
Notes Figure 3-1:
interconnects drive interconnects. This pattern repeated every row. interconnects span LABs provide fastest resource long connections between non-adjacent LABs, memory blocks, dedicated multipliers, IOEs. interconnects drive other column interconnects every fourth LAB. interconnects drive local interconnects interconnects drive directly local interconnects. interconnects drive R24, C16, interconnects.
Column Interconnects
column interconnect operates similar interconnect. Each column LABs served dedicated column interconnect, which vertically routes signals from LABs, memory blocks, embedded multipliers, column elements. These column resources include:
Register chain interconnects within interconnects traversing distance four blocks down direction interconnects high-speed vertical routing through device
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Cyclone devices include enhanced interconnect structure within LABs route logic element (LE) outputs input connections faster using register chain connections. register chain connection allows register output connect directly register input next fast shift registers. Quartus® compiler automatically takes advantage these resources improve utilization performance. Figure shows register chain interconnects. Figure 3-2. Register Chain Interconnects
Local Interconnect Routing Among Carry Chain Routing Adjacent
Register Chain Routing Adjacent LE's Register Input
Local Interconnect
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interconnects span four blocks down from source LAB, block, embedded multiplier. Every LAB, block, embedded multiplier interconnects drive either down. Figure shows interconnect connections from column. interconnects drive driven types architecture blocks, including memory blocks, embedded multiplier blocks, column elements. interconnect driven neighboring LABs blocks (see Figure 3-3). interconnects drive both blocks extend their range drive blocks left right column-to-column connections.
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Figure 3-3. Interconnect Connections Notes (1),
Interconnect Drives Local Interconnects Four Rows
Interconnect Driving
Interconnect
Adjacent drive onto neighboring LAB's interconnect Neighbor
Local Interconnect
Primary
Interconnect Driving Down
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Notes Figure 3-3:
Each interconnect drive either down four rows. column interconnects span length LABs provide fastest resource long column connections between LABs, memory blocks, embedded multipliers, elements. column interconnects drive other column interconnects every fourth LAB. column interconnects drive local interconnects interconnects drive local interconnects directly. interconnects drive R24, C16, interconnects.
Device Routing
embedded blocks communicate with logic array similar LAB-to-LAB interfaces. Each block (for example, memory, embedded multiplier, PLL) connects column interconnects local interconnect regions driven column interconnects. These blocks also have direct link interconnects fast connections from neighboring LAB. Table shows Cyclone device routing scheme.
Table 3-1. Cyclone Device Routing Scheme Destination Source Direct Local Chain Link
Embd MultiBlock plier
Register Chain Local Interconnect Direct Link Interconnect Interconnect Interconnect Interconnect Interconnect Memory Block Embedded Multipliers Column Element Element
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Local Interconnects
local interconnect drive within same LAB. local interconnect driven column interconnects outputs within same LAB. Neighboring blocks from left right also drive LAB's local interconnect through direct link connection. direct link connection feature minimizes column interconnects, providing higher performance flexibility. Each drive through fast local direct link interconnects. Figure shows direct link connection. Figure 3-4. Direct Link Connection
Direct link interconnect from left LAB, memory block, embedded multiplier, PLL, output Direct link interconnect from right LAB, memory block, embedded multiplier, PLL, output
Direct link interconnect left
Direct link interconnect right
Local Interconnect
Logic Elements Logic Array Blocks Cyclone Devices chapter volume Cyclone Device Handbook more information about Cyclone LABs LEs.
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Routing Interface
direct link interconnects from adjacent LABs blocks drive block local interconnect. blocks communicate with LABs blocks either left right side through these resources, with columns either left right with column resources. direct link input connections block possible from left adjacent another possible from right adjacent LAB. block outputs also connect left right LABs through each direct link interconnects. Figure shows block logic array interface. Figure 3-5. Block Interface
Interconnects Interconnects
Direct link interconnect adjacent
Direct link interconnect adjacent dataout
Direct link interconnect from adjacent
Block Byte enable Control Signals Clocks
Direct link interconnect from adjacent
address
datain
Block Local Interconnect Region Clocks
Embedded Memory Blocks Cyclone Devices Chapter volume Cyclone Device Handbook more information about Cyclone embedded memory blocks.
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Embedded Multiplier Routing Interface
direct link interconnects from adjacent LABs drive embedded multiplier interface interconnect. embedded multipliers communicate with LABs either left right side through these resources with columns either right left with column resources. direct link input connections embedded multiplier possible from left adjacent LABs another possible from right adjacent LAB. Embedded multiplier outputs also connect left right LABs through direct link interconnects each. Figure shows embedded multiplier logic array interface. Figure 3-6. Embedded Multiplier Interface
Interconnects Direct Link Interconnect from Adjacent Interconnects Direct Link Outputs Adjacent LABs Direct Link Interconnect from Adjacent
Embedded Multiplier
Control [35.0] [35.0]
Interface Block
Block Interconect Region
Embedded Multiplier Interface Block Interconnect Region
Inputs
Outputs
Block Interconect Region
Interconnects
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Conclusion
There five dynamic control input signals that feed embedded multiplier:
signa signb clkena aclr
signa signb signal registered match data signal input path. clk, clkena, aclr signals feed registers within single embedded multiplier.
Embedded Multipliers Cyclone Devices Chapter volume Cyclone Device Handbook more information about Cyclone embedded multipliers. Cyclone device provides fast optimal performance interconnections between LEs, memory blocks, embedded multipliers, device pins. Quartus software provides most suitable routing interconnects your design deliver optimum performance.
Conclusion
Document Revision History
Table 3-2. Document Revision History Date Document Version
March 2007 v1.0 Initial Release
Changes Made
Summary Changes
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Introduction
Cyclone® devices feature embedded memory structures address on-chip memory needs Altera® Cyclone device designs. embedded memory structure consists columns memory blocks that configure provide various memory functions, such RAM, shift registers, ROM, first-in first-out (FIFO) buffers. memory blocks provide 3.98 Mbit maximum synchronous operation (see Table total bits-per-density). blocks support following features:
Overview
3.98 Mbit available without reducing available logic 8,192 memory bits block (9,216 bits block including parity) Independent read-enable write-enable signals each port Packed mode which memory block split into single-port RAMs Variable port configurations Single-port simple dual-port modes support port widths True dual-port (one read write, reads, writes) operation Byte enables data input masking during writes clock-enable control signals each port (port port Initialization file pre-load content memory modes synchronous only operation
Table summarizes features supported memory.
Table 4-1. Summary Memory Features (Part Feature
Maximum performance Total bits (including parity bits)
Blocks
9,216
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Table 4-1. Summary Memory Features (Part
Configurations (depth width) 8192 4096 2048 1024 1024 Outputs cleared Read address registers output registers only Output latches only Write Read: Rising clock edges Outputs "Old Data" "New Data" Outputs "Old Data" "Don't Care"
Parity bits Byte enable Packed mode Address clock enable Single-port mode Simple dual-port mode True dual-port mode Embedded shift register mode mode FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode Power-up condition Register asynchronous clears Latch asynchronous clears Write/Read operation triggering Same-port read-during-write Mixed-port read-during-write Notes Table 4-1:
FIFO buffers embedded shift registers that require external logic elements (LEs) implementing control logic. Width modes available.
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Overview
Table shows capacity distribution memory blocks each Cyclone device family member.
Table 4-2. Number Blocks Cyclone Devices Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
Number Blocks
Total Bits
423,936 423,936 516,096 608,256 1,161,216 2,396,160 2,810,880 3.981,312
Control Signals
Figure shows register clocks, clears, control signals implemented Cyclone memory block. clock-enable control signal controls clock entering entire memory block, just input output registers. This signal disables clock that memory block does clock edges will perform operations. read-enable (rden) write-enable (wren) control signals control read write operations each port memory blocks. disable read-enable write-enable signals independently save power whenever operation required.
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Figure 4-1. Control Signal Selection
Dedicated Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect
clock_b
clocken_b rden_a
rden_b wren_a
wren_b aclr_a
aclr_b
addressstall_b
byteena_b
clock_a
clocken_a
addressstall_a
byteena_a
Parity Support
Parity checking error detection possible using parity along with internal logic resources. Cyclone memory blocks support parity each storage byte. this optionally parity additional data bit. parity function actually performed this bit.
Byte Enable Support
Cyclone memory blocks support byte enables that mask input data that only specific bytes data written. unwritten bytes retain previous written value. write enable (wren) signals, along with byte enable (byteena) signals, control block's write operations. default value byte-enable signals high
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Overview
(enabled), which case writing controlled only write-enable signals. There clear port byte-enable registers. blocks support byte enables when write port data width bits. Byte enables operate one-hot manner, with least significant (LSB) byteena signal corresponding least significant byte data bus. example, using block mode, with byteena data[8.0] enabled data[17.9] disabled. Similarly, byteena both data[8.0] data[17.9] enabled. Byte enables active high. Table summarizes byte selection.
Table 4-3. Byte Enable Cyclone Blocks byteena[3.0]
Note Table 4-3:
combination byte enables possible.
Affected Bytes
[8.0] [17.9]
[7.0] [15.8] [23.16] [31.24]
[8.0] [17.9] [26.18] [35.27]
[7.0] [15.8]
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Memory Blocks Cyclone Devices
Figure shows wren byteena signals control operations RAM. Figure 4-2. Cyclone Byte Enable Functional Waveform
inclock
wren
rden
address
data
XXXX
ABCD
XXXX
byteena
contents
FFFF
ABFF
contents
FFFF
FFCD
contents
FFFF
ABCD
(asynch)
doutn
ABFF
FFCD
ABCD
ABFF
FFCD
ABCD
Note Figure 4-2:
this functional waveform, "New Data" mode selected.
When byte-enable de-asserted during write cycle, data memory appears corresponding data-byte output. When byteenable asserted during write cycle, corresponding data-byte output depends setting chosen Quartus® software. either newly written data data that location.
Packed Mode Support
Cyclone memory blocks support packed mode. implement single-port memory blocks single block under following conditions:
Each independent block sizes less than equal half block size. maximum data width each independent block 18-bits wide. Each single-port memory blocks configured single-clock mode.
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Overview
"Single-Port Mode" page 4-10 "Single-Clock Mode" page 4-25 more information.
Address Clock Enable Support
Cyclone memory blocks support address clock enable, which holds previous address value long signal enabled addressstall active high (addressstall '1'). When configure memory blocks dual-port mode, each port independent address clock enable. Figure shows address clock enable block diagram. address register output feeds back input multiplexer. multiplexer output selected address clock enable (addressstall) signal. Figure 4-3. Cyclone Address Clock Enable Block Diagram
address[0]
address[0] register
address[0]
address[N] addressstall clock
address[N] register
address[N]
address clock enable typically used cache memory applications improve efficiency during cache-miss. default value address clock enable signals (disabled). Figures show address clock enable waveforms during read write cycles, respectively.
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Figure 4-4. Cyclone Address Clock Enable During Read Cycle Waveform
inclock rdaddress rden addressstall latched address (inside memory) doutn dout0 dout0 dout1 dout1 dout1 dout1 dout1 dout1 dout4 dout4 dout5
(synch) doutn-1 (asynch) doutn
Figure 4-5. Cyclone Address Clock Enable During Write Cycle Waveform
inclock wraddress data wren addressstall latched address (inside memory) contents contents contents contents contents contents
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Overview
Mixed Width Support
memory blocks support mixed data widths. When using simple dual-port, true dual-port, FIFO modes, mixed width support allows read write different data widths memory block. "Memory Modes" page 4-10 details different widths supported memory mode.
Asynchronous Clear
Cyclone devices support asynchronous clears read address registers, output registers output latches only. Input registers other than read address registers supported. When applied output registers, asynchronous clear signal clears output registers. effects immediately. your does output registers, still clear outputs output latch asynchronous clear. Asserting asynchronous clear read address register duringa read operation could corrupt memory content.
Figure shows functional waveform this feature. Figure 4-6. Output Latch Asynchronous Clear Waveform
aclr
aclr latch
selectively enable asynchronous clears logical memory Quartus MegaWizard®.
Megafunction User Guide more details. There three ways reset registers blocks: power device, aclr signal output register only, assert device-wide reset signal using DEV_CLRn option.
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Memory Blocks Cyclone Devices
Memory Modes
Cyclone memory blocks allow implement fully synchronous SRAM memory multiple modes operation. Cyclone memory does support asynchronous (unregistered) memory inputs. memory blocks support following modes:
Single-port Simple dual-port True dual-port Shift-register FIFO Violating setup hold time memory block input registers could corrupt memory contents. This applies both read write operations.
Single-Port Mode
Single-port mode supports non-simultaneous read write operations from single address. Figure shows single-port memory configuration Cyclone memory blocks. Figure 4-7. Single-Port Memory (1),
data[ address[ wren byteena[] addressstall inclock inclocken rden aclr
outclock outclocken
Notes Figure 4-7:
implement single-port memory blocks single block. "Packed Mode Support" more details.
During write operation, behavior outputs configurable. activate read enable during write operation, outputs will show either data being written data that address. perform write operation with read enable deactivated, outputs retain values they held during most recent active read enable. choose desired behavior, Read-During-Write option
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Memory Modes
either "New Data" "Old Data" MegaWizard Quartus software. "Read-During-Write Operations" page 4-28 more information about read-during-write mode. port width configurations blocks single-port mode follows:
8192 4096 2048 1024 1024
Figure shows timing waveforms read write operations single-port mode with unregistered outputs. Registering RAM's outputs would simply delay output clock cycle. Figure 4-8. Cyclone Single-Port Mode Timing Waveforms
clk_a
wren_a rden_a address_a
data_a
(old data)
a0(old data)
a1(old data)
(new data)
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Memory Blocks Cyclone Devices
Simple Dual-Port Mode
Simple dual-port mode supports simultaneous read write operation different locations. Figure shows simple dual-port memory configuration. Figure 4-9. Cyclone Simple Dual-Port Memory
data[ wraddress[ wren byteena[] wr_addressstall wrclock wrclocken aclr rdaddress[ rden rd_addressstall rdclock rdclocken
Note Figure 4-9:
Simple dual-port supports input/output clock mode addition read/write clock mode shown.
Cyclone memory blocks support mixed-width configurations, allowing different read write port widths. Table shows mixed-width configurations.
Table 4-4. Cyclone Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port 8192 4096 2048 1024 1024 Write Port 8192 4096 2048 1024 1024
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Memory Modes
simple dual-port mode, memory blocks support separate write-enable read-enable signals. save power keeping read-enable signal (inactive) when reading. Read-during-write operations same address either output "Don't Care" data that location output "Old Data". choose desired behavior, Read-During-Write option either "Don't Care" "Old Data" MegaWizard Quartus software. "Read-During-Write Operations" page 4-28 more details about this behavior. Figure 4-10 shows timing waveforms read write operations simple dual-port mode with unregistered outputs. Registering RAM's outputs would simply delay output clock cycle. Figure 4-10. Cyclone Simple Dual-Port Timing Waveforms
wrclock wren wraddress data rdclock rden rdaddress (asynch) doutn-1 doutn dout0 an-1 din-1 din4 din5 din6
True Dual-Port Mode
True dual-port mode supports combination two-port operations: reads, writes, read write, different clock frequencies. Figure 4-11 shows Cyclone true dual-port memory configuration.
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Memory Blocks Cyclone Devices
Figure 4-11. Cyclone True Dual-Port Memory
data_a[ address_a[ wren_a byteena_a[] addressstall_a clock_a clocken_a rden_a aclr_a q_a[]
data_b[ address_b[] wren_b byteena_b[] addressstall_b clock_b clocken_b rden_b aclr_b q_b[]
Note Figure 4-11:
True dual-port memory supports input/output clock mode addition independent clock mode shown.
widest configuration blocks true dual-port mode 16-bit (18-bit with parity).
Table lists possible block mixed-port width configurations.
Table 4-5. Cyclone Block Mixed-Width Configurations (True Dual-Port Mode)
Read Port 8192 4096 2048 1024 1024 Write Port 8192 4096 2048 1024 1024
true dual-port mode, memory blocks support separate write-enable read-enable signals. save power keeping read-enable signal (inactive) when reading. Read-during-write operations same address either output "New Data" that location "Old Data". choose desired behavior, Read-During-Write option either "New Data" "Old Data" MegaWizard Quartus software. "Read-During-Write Operations" page 4-28 more details this behavior.
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Memory Modes
true dual-port mode, access memory location time from either port port When accessing same memory location from both ports, must avoid possible write conflicts. write conflict happens when attempt write same address location from both ports same time. This will result unknown data being stored that address location. There conflict resolution circuitry built into Cyclone memory blocks. must handle address conflicts external block. Figure 4-12 shows true dual-port timing waveforms write operation port read operation port Registering RAM's outputs would simply delay outputs clock cycle. Figure 4-12. Cyclone True Dual-Port Timing Waveforms
clk_a wren_a address_a data_a rden_a (asynch) clk_b wren_b address_b rden_b (asynch) doutn-1 doutn dout0 dout1 dout2 din-1 dout0 dout1 dout2 dout3 din4 din5 an-1 din-1 din4 din5 din6
Shift Register Mode
Cyclone memory blocks implement shift registers digital signal processing (DSP) applications, such finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, auto-correlation cross-correlation functions. These other applications require local data storage, traditionally implemented with standard flip-flops that quickly exhaust many logic cells large shift registers. more efficient alternative embedded memory shift register block, which saves logic cell routing resources. size shift register determined input data width (w), length taps (m), number taps (n), must less than equal maximum number memory bits, which
Altera Corporation-Preliminary March 2007
4-15 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
9,216 bits. addition, size must less than equal maximum width block, which bits. larger shift register required, cascade memory blocks. Figure 4-13 shows Cyclone memory block shift register mode. Figure 4-13. Cyclone Shift Register Mode Configuration
Shift Register m-Bit Shift Register
m-Bit Shift Register
Number Taps
m-Bit Shift Register
m-Bit Shift Register
4-16 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Clocking Modes
Mode
Cyclone memory blocks support mode. memory initialization file (.mif) initializes contents these blocks. address lines registered. outputs registered unregistered. read operation identical read operation singleport configuration.
FIFO Buffer Mode
Cyclone memory blocks support single clock dual clock FIFO buffer. Dual clock FIFO buffers useful when transferring data from clock domain another clock domain. Cyclone memory blocks support simultaneous read write from empty FIFO buffer.
Refer Single- Dual-Clock FIFO Megafunctions User Guide more information FIFO buffers. will find this Altera site Cyclone memory blocks support following clocking modes:
Clocking Modes
Independent Input/output Read/write Single-clock Violating setup hold time memory block input registers could corrupt memory contents. This applies both read write operations. Asynchronous clears available read address registers, output registers output latches only.
Table shows clocking mode versus memory mode support matrix.
Table 4-6. Cyclone Memory Clock Modes
Clocking Mode Independent Input/output Read/write Single-clock True Dual-Port Mode Simple Dual-Port Mode Single-Port Mode Mode FIFO Mode
Altera Corporation-Preliminary March 2007
4-17 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
Independent Clock Mode
Cyclone memory blocks implement independent clock mode true dual-port memories. this mode, separate clock available each port (port port Clock controls registers port side, while clock controls registers port side. Each port also supports independent clock enables port registers. Figure 4-14 shows memory block independent clock mode.
4-18 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Clocks
Data
Altera Corporation-Preliminary March 2007
Data Memory Block 1,024 2,048 4,096 Byte Enable
data_a[
data_b[
byteena_a[
Byte Enable
byteena_b[
address_a[
Address Address
address_b[
addressstall_a
Address Clock Enable
Address Clock Enable
addressstall_b
rden_a
Read Enable Read Enable
rden_b
wren_a Write Enable Data
wren_b Write Enable Data
Figure 4-14. Cyclone Memory Block Independent Clock Mode
enable_b clock_b
enable_a
clock_a
4-19 Cyclone Device Handbook, Volume
q_a[ q_b[
Clocking Modes
Memory Blocks Cyclone Devices
Input/Output Clock Mode
Cyclone memory blocks implement input/output clock mode FIFO, single-port, true, simple dual-port memories. this mode, input clock controls input registers memory block including data, address, byte enables, write enables also read-enable registers. output clock controls data-output registers. Each memory block port also supports independent clock enables input output registers. Figures 4-15, 4-16, 4-17 show memory block input/output clock mode true dual-port, simple dual-port, single-port modes, respectively.
4-20 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Clocks
Altera Corporation-Preliminary March 2007
Data
data_b[
data_a[ Data
Memory Block 1,024 2,048 4,096 Byte Enable
byteena_a[
Byte Enable
byteena_b[
address_a[
Address Address
address_b[
addressstall_a wren_a
Address Clock Enable
Address Clock Enable
addressstall_b wren_b
inclocken
Write Enable Read Enable Data
Write Enable Read Enable Data
inclock outclocken outclock
Figure 4-15. Cyclone Input/Output Clock Mode True Dual-Port Mode
4-21 Cyclone Device Handbook, Volume
q_a[ q_b[
Clocking Modes
Memory Blocks Cyclone Devices
Figure 4-16. Cyclone Input/Output Clock Mode Simple Dual-Port Mode
Clocks Memory Block Data 1,024 2,048 4,096 Read Address
data[
rdaddress[
Data byteena[ Byte Enable
MultiTrack Interconnect
wraddress[
Write Address
rd_addressstall
Read Address Clock Enable
wr_addressstall
Write Address Clock Enable
rden wren Write Enable outclocken Read Enable
inclocken inclock
outclock
Note Figure 4-16:
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
4-22 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Clocking Modes
Figure 4-17. Cyclone Input/Output Clock Mode Single-Port Mode
Clocks Memory Block Data 1,024 2,048 4,096 Address
data[
address[
Data byteena[ Byte Enable
MultiTrack Interconnect
addressstall rden
Address Clock Enable Read Enable
wren
outclocken
Write Enable
inclocken inclock
outclock
Note Figure 4-17:
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
Read/Write Clock Mode
Cyclone memory blocks implement read/write clock mode FIFO simple dual-port memories. this mode, write clock controls data inputs, write address, write-enable registers. Similarly, read clock controls data outputs, read address, readenable registers. memory blocks support independent clock enables both read write clocks. Figure 4-18 shows memory block read/write clock mode.
Altera Corporation-Preliminary March 2007
4-23 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
Figure 4-18. Cyclone Read/Write Clock Mode
Clocks Memory Block Data 1,024 2,048 4,096 Read Address
data[
rdaddress[
Data byteena[ Byte Enable
MultiTrack Interconnect
wraddress[
Write Address
rd_addressstall
Read Address Clock Enable
wr_addressstall
Write Address Clock Enable
rden wren Write Enable rdclocken Read Enable
wrclocken wrclock
rdclock
Note Figure 4-18:
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
4-24 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Clocking Modes
Single-Clock Mode
Cyclone memory blocks implement single-clock mode FIFO, ROM, true dual-port, simple dual-port, single-port memories. this mode, control registers memory block with single clock together with clock enable. Figures 4-19, 4-20, 4-21 show memory block single-clock mode true dual-port, simple dual-port, single-port modes, respectively.
Altera Corporation-Preliminary March 2007
4-25 Cyclone Device Handbook, Volume
Clocks
Note Figure 4-19:
Data
data_b[
Memory Blocks Cyclone Devices
data_a[ Data
Memory Block 1,024 2,048 4,096 Byte Enable
4-26 Cyclone Device Handbook, Volume
byteena_a[
Byte Enable
byteena_b[
address_a[
Address Address
address_b[
addressstall_a rden_a
Address Clock Enable Address Clock Enable Read Enable Read Enable
addressstall_b
rden_b
wren_a
wren_b Write Enable enable
Write Enable Data Data
Figure 4-19. Cyclone Single-Clock Mode True Dual-Port Mode
clock
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
q_a[ q_b[
Altera Corporation-Preliminary March 2007
Clocking Modes
Figure 4-20. Cyclone Single-Clock Mode Simple Dual-Port Mode
Clocks Memory Block Data 1,024 2,048 4,096 Read Address
data[
rdaddress[
Data byteena[ Byte Enable
MultiTrack Interconnect
wraddress[
Write Address
rd_addressstall
Read Address Clock Enable
wr_addressstall
Write Address Clock Enable
rden wren Read Enable
Write Enable
enable clock
Note Figure 4-20:
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
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4-27 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
Figure 4-21. Cyclone Single-Clock Mode Single-Port Mode
Clocks Memory Block Data 1,024 2,048 4,096 Address
data[
address[
Data byteena[ Byte Enable
MultiTrack Interconnect
addressstall rden
Address Clock Enable Read Enable
wren
Write Enable
enable clock
Note Figure 4-21:
Cyclone Device Family Data Sheet Cyclone Device Handbook, Volume more information MultiTrack interconnect.
Design Considerations
Read-During-Write Operations
"Same-Port Read-During-Write Mode" page 4-29 "Mixed-Port Read-During-Write Mode" page 4-30 describe functionality various configurations when reading from address during write operation that same address. There read-during-write data flows: same-port mixed-port.
4-28 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Design Considerations
Figure 4-22 shows difference between these flows. Figure 4-22. Cyclone Read-During-Write Data Flow
write_a write_b
Port data
Port data
Mixed-port data flow Same-port data flow read_a
Port data
Port data
read_b
Same-Port Read-During-Write Mode
This mode applies single-port same port true dual-port RAM. same port read-during-write mode, there output choices: "New Data" mode flow-through) "Old Data" mode. "New Data" mode, data available rising edge same clock cycle which written. "Old Data" mode, outputs reflect data that address before write operation proceeds. When using Data mode together with byte enable (byteena), control output RAM. When byte enable high, data written into memory passes output (flow-through). When byte enable low, masked-off data written into memory data memory appears outputs. Therefore, output combination data determined byte enable. Figures 4-23 4-24 show sample functional waveforms same port read-during-write behavior with both "New Data" "Old Data" modes, respectively.
Altera Corporation-Preliminary March 2007
4-29 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
Figure 4-23. Same Port Read-During Write: Data Mode
clk_a
wren_a rden_a address_a
data_a
(asynch)
Figure 4-24. Same Port Read-During-Write: Data Mode
clk_a
wren_a rden_a address_a
data_a
(asynch)
a0(old data)
a1(old data)
Mixed-Port Read-During-Write Mode
This mode applies simple true dual-port mode, which port reading other port writing same address location with same clock. this mode, also have output choices: "Old Data" "Don't Care". "Old Data" mode, read-during-write operation different ports causes outputs reflect data that address location. "Don't Care" mode, same operation results "Don't Care" unknown value outputs.
4-30 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Design Considerations
Refer Megafunction User Guide more details implement desired behavior. Figure 4-25 shows sample functional waveform mixed port read-during-write behavior "Old Data" mode. "Don't Care" mode, data shown figure simply replaced with "Don't Care".
Figure 4-25. Mixed Port Read-During-Write: Data Mode
clk_a&b
wren_a address_a
data_a
rden_a
address_b
(asynch)
(old data)
(old data)
Cyclone memory blocks support mixed-port read-during-write when different clocks used dual-port RAM. output value unknown during dual-clock mixed-port read-during-write operation.
Conflict Resolution
When using memory blocks true dual-port mode, possible attempt write operations same memory location (address). Since there conflict resolution circuitry built into memory blocks, this results unknown data being written that location. Therefore, need implement conflict-resolution logic external memory block.
Altera Corporation-Preliminary March 2007
4-31 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
Power-Up Conditions Memory Initialization
Cyclone memory block outputs power zero (cleared) regardless whether output registers used bypassed. memory blocks support initialization memory initialization file (.mif) file. create .mifs Quartus software specify their MegaWizard when instantiating memory your design. Even memory pre-initialized (via .mif file, example), still powers with outputs cleared. Only subsequent read after power outputs pre-initialized values.
more information files, refer Megafunction User Guide well Quartus Handbook. will find these documents Altera site respectively.
Power Management
Cyclone memory block clock enables allow control clocking each memory block reduce power consumption. read-enable signal ensure that read operations only occur when necessary. your design does require read-during-write, reduce power consumption de-asserting read-enable signal during write operations, period when there memory operations. Quartus software automatically powers down unused memory blocks order save static power.
Conclusion
Cyclone embedded memory structure provides flexible memory architecture with high memory bandwidth. addresses needs different memory applications Cyclone device designs with features such different memory modes, byte enables, parity storage, address clock enables, mixed clock mode, mixed-port width support. these configurations possible Quartus MegaWizard.
Document Revision History
4-32 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Document Revision History
Table 4-7. Document Revision History Date Document Version
March 2007 v1.0 Initial Release
Changes Made
Summary Changes
Altera Corporation-Preliminary March 2007
4-33 Cyclone Device Handbook, Volume
Memory Blocks Cyclone Devices
4-34 Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Embedded Multipliers Cyclone Devices
CIII51006-1.0
Introduction
Cyclone® devices offer embedded multiplier blocks support following modes: individual multiplier block, individual multipliers block. addition embedded multipliers, Cyclone FPGAs include combination on-chip resources external interfaces that helps increase performance, reduce system cost, lower power consumption digital signal processing (DSP) systems. Cyclone FPGAs alone device processors improve price-to-performance ratios systems. Particular focus been placed optimizing Cyclone FPGAs applications benefiting from abundance parallel processing resources including video image processing, modems used wireless communications systems, multi-channel communications video systems. Cyclone FPGA system design support includes:
multipliers 2,811 Kbit on-chip embedded memory blocks High-speed interfaces external memory such DDR2 SDRAM Intellectual Property (IP) cores that include: Common processing functions like finite impulse response (FIR), fast Fourier transform (FFT), numerically controlled oscillator (NCO) functions Video image processing suite Complete reference designs market applications Builder interface between Mathworks Simulink MATLAB design environment Altera® Quartus® software optimized development kits
This chapter focuses Cyclone embedded multiplier blocks. Quartus software makes easy take advantage embedded multipliers instantiating multipliers using dedicated megafunction wizard interfaces inferring multipliers directly VHDL Verilog code. more information about Quartus software support Cyclone embedded multipliers, refer "Software Support" page 5-10.
Altera Corporation-Preliminary March 2007
Preliminary
Embedded Multipliers Cyclone Devices
Embedded Multiplier Block Overview
Each Cyclone device four columns embedded multipliers that implement multiplication functions. Figure shows embedded multiplier columns with surrounding logic array blocks (LABs). configure each embedded multiplier multiplier multipliers. multiplication greater than Quartus software cascades multiple embedded multiplier blocks together. There restriction data width multiplier, greater data width, slower multiplication process. Figure 5-1. Embedded Multipliers Arranged Columns with Adjacent LABs
Embedded Multiplier Column
Embedded Multiplier
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Embedded Multiplier Block Overview
number embedded multipliers column number columns available increases with device density. Table shows number embedded multipliers each Cyclone device multiplier modes that implement.
Table 5-1. Number Embedded Multipliers Cyclone Devices Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 Note Table 5-1:
These columns show number multipliers each device. total number multipliers each device multipliers.
Embedded Multipliers
Multipliers
Multipliers
addition embedded multipliers, also implement soft multipliers using Cyclone memory blocks. blocks look-up tables (LUTs) that contain partial results from multiplication input data with coefficients that implements variable depth/width high-performance soft multipliers low-cost, high-volume applications. availability soft multipliers increases number multipliers available within device. Table shows total number multipliers available Cyclone devices using embedded multipliers soft multipliers.
Table 5-2. Number Multipliers Cyclone Devices (Part Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40
Embedded Multipliers
Soft Multipliers
Total Multipliers
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
Table 5-2. Number Multipliers Cyclone Devices (Part Device
EP3C55 EP3C80 Notes Table 5-2:
Soft multipliers implemented multiplication mode. memory blocks configured with 18-bit data widths support 16-bit coefficients. coefficients requires 18-bits resolution account overflow. total number multipliers vary according multiplier mode use.
Embedded Multipliers
Soft Multipliers
Total Multipliers
Refer Cyclone Memory Blocks chapter volume Cyclone Device Handbook more information Cyclone memory blocks. Refer 306: Techniques Implementing Multipliers FPGA Devices more information about soft multipliers. Each embedded multiplier consists following elements:
Architecture
Multiplier stage Input output registers Input output interfaces
Figure shows multiplier block architecture.
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Architecture
Figure 5-2. Multiplier Block Architecture
signa signb aclr clock
Data
Data
CLRN
CLRN
Data
Input Register Output Register
CLRN
Embedded Multiplier Block
Input Registers
send each multiplier input signal into input register directly into multiplier 18-bit sections, depending operational mode multiplier. send each multiplier input signal through register independently each other (for example, send multiplier's data signal through register send data signal directly multiplier). following control signals available each input register within embedded multiplier:
clock clock enable asynchronous clear
input output registers within single embedded multiplier same clock, clock enable, asynchronous clear signals.
Multiplier Stage
multiplier stage embedded multiplier block supports multipliers well other multipliers between these configurations. Depending data width operational mode multiplier, single embedded multiplier perform multiplications parallel.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
Refer "Operational Modes" page multiplier details. Each multiplier operand unique signed unsigned number. signals, signa signb, control input multiplier determine value signed unsigned. signa signal high, data operand signed number. signa signal low, data operand unsigned number. Table shows sign multiplication result various operand sign representations. result multiplication signed operands signed value.
Table 5-3. Multiplier Sign Representation Data signa Value
Unsigned Unsigned Signed Signed
Data Logic Level
High High
Result Logic Level
High High Unsigned Signed Signed Signed
signb Value
Unsigned Signed Unsigned Signed
Each embedded multiplier block only signa signb signal control sign representation input data block. embedded multiplier block multipliers, data input both multipliers share same signa signal, data input both multipliers share same signb signal. change signa signb signals dynamically modify sign representation input operands time. send signa signb signals through dedicated input register. multiplier offers full precision, regardless sign representation. When signa signb signals unused, Quartus software sets multiplier perform unsigned multiplication default.
Output Registers
choose register embedded multiplier output using output registers 36-bit sections, depending operational mode multiplier. following control signals available each output register within embedded multiplier:
clock clock enable asynchronous clear
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Operational Modes
input output registers within single embedded multiplier same clock, clock enable, asynchronous clear signals.
Refer MultiTrack Interconnect Cyclone Devices chapter volume Cyclone Device Handbook more information embedded multiplier routing interface. embedded multiplier block operational modes, depending application needs:
Operational Modes
18-bit multiplier 9-bit independent multipliers
Quartus software includes megafunctions used control operational modes multipliers. After have made appropriate parameter settings using megafunction's MegaWizard® Plug-In Manager, Quartus software automatically configures embedded multiplier. also Cyclone embedded multipliers implement multiplier adder multiplier accumulator functions where multiplier portion function implemented using embedded multipliers adder accumulator function implemented logic elements (LEs).
more information about Quartus support Cyclone embedded multipliers, refer "Software Support" page 5-10.
18-Bit Multipliers
configure each embedded multiplier support single multiplier input widths bits. Figure shows embedded multiplier configured support 18-bit multiplier.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
Figure 5-3. 18-Bit Multiplier Mode
signa signb aclr clock
Data [17.0]
Data [35.0]
CLRN
CLRN
Data [17.0]
CLRN
Multiplier Embedded Multiplier
18-bit multiplier inputs results sent independently through registers. multiplier inputs accept signed integers, unsigned integers, combination both. Additionally, change signa signb signals dynamically send these signals through dedicated input registers.
9-Bit Multipliers
configure each embedded multiplier support independent multipliers input widths bits. Figure shows embedded multiplier configured support 9-bit multipliers.
Cyclone Device Handbook, Volume
Altera Corporation-Preliminary March 2007
Operational Modes
Figure 5-4. 9-Bit Multiplier Mode
signa signb aclr clock
Data [8.0]
Data [17.0]
CLRN
CLRN
Data [8.0]
CLRN
Multiplier
Data [8.0]
Data [17.0]
CLRN
CLRN
Data [8.0]
CLRN
Multiplier Embedded Multiplier
9-bit multiplier inputs results sent independently through registers. multiplier inputs accept signed integers, unsigned integers, combination both. multipliers same embedded multiplier block share same signa signb signal. Therefore, data inputs feeding same embedded multiplier must have same sign representation. Similarly, data inputs feeding same embedded multiplier must have same sign representation.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
Software Support
Altera provides methods implementing multipliers your design using embedded multiplier resources: instantiation inference. Both methods following four Quartus megafunctions:
lpm_mult altmult_add altmult_accum altfp_mult
first method, lpm_mult, altmult_add, altfp_mult megafunctions implement multipliers. Additionally, altmult_add megafunction multiplier-adders where embedded multipliers used multiply function configured adders. altfp_mult megafunction floating point multiplier. implements embedded multiplier floating point numbers multiplication. altmult_accum megafunction implements multiply accumulate functions where embedded multiplier implements multiplier accumulator function implemented LEs.
Refer Quartus On-Line Help instructions using megafunctions MegaWizard Plug-In Manager. second method, infer megafunctions creating design synthesizing using Quartus Native Synthesis, third-party synthesis tool such Cadence Synplify, which recognizes infers appropriate multiplier megafunction. With both options, Quartus software maps multiplier functionality embedded multipliers during compilation.
information complete Design Intellectual Property offerings, refer Altera site (www.altera.com). Refer Synthesis section volume Quartus Handbook more information.
5-10 Cyclone Device Handbook, Volume
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Conclusion
Conclusion
Cyclone embedded multipliers optimized support multiplierintensive applications such filters, functions, encoders. configure these embedded multipliers implement multipliers various widths 18-bits suit particular application, resulting efficient resource utilization improved performance data throughput. Quartus software, together with Synplify software, provide complete easy-to-use flow implementing multiplier functions using embedded multipliers.
Document Revision History
Table shows revision history this document.
Table 5-4. Document Revision History Date Document Version
March 2007 v1.0 Initial Release
Changes Made
Summary Changes
Altera Corporation-Preliminary March 2007
5-11 Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
5-12 Cyclone Device Handbook, Volume
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Clock Networks PLLs Cyclone Devices
CIII51007-1.0
Introduction
Cyclone® devices provide large number global clock resources combination with clock synthesis precision provided phase-locked loops (PLLs). This provides complete clock-management solution. Cyclone devices provide dedicated global clock networks (GCLK). Clock networks that being used design automatically turned Quartus® software reduce overall power consumption. Cyclone devices include four PLLs device five outputs PLL. additional global clock networks additional outputs compared Cyclone devices enables more efficient resources. independently program every output, creating unique, customizable clock frequency with fixed relation other input output clock. Inherent jitter filtration fine granularity control over multiply, divide ratios, dynamic phase shift reconfiguration provide high performance precision required today's high-speed applications. Cyclone device PLLs feature rich, supporting advanced capabilities such clock switchover, dynamic phase shifting, reconfiguration. Dynamic phase reconfiguration allows implementation high performance, easy implement, self calibrating external memory interfaces. Dynamic phase reconfiguration allows support advanced display applications where input frequency known ahead time change. Cyclone PLLs also support spread-spectrum tracking support clock sources that lower EMI. Altera® Quartus software enables features without requiring external devices. following sections describe Cyclone clock networks PLLs detail.
Clock Networks
Cyclone devices provide dedicated clock pins (CLK[15.0]) that drive global clock networks. smaller Cyclone devices (EP3C5 EP3C10) support four dedicated clock pins left right sides device, capable driving total global clock networks. larger devices (EP3C16 devices larger) support four dedicated clock pins each side device. These clock pins drive global clock networks.
Altera Corporation-Preliminary March 2007
Clock Networks PLLs Cyclone Devices
Table shows number global clocks available across Cyclone family members.
Table 6-1. Number Global Clocks Available Cyclone Devices Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80
Number Global Clocks
Global Clock Network
Global clocks drive throughout entire device, feeding device quadrants. resources within device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks, memory blocks) global clock networks clock sources. these clock network resources control signals, such clock enables clears external pin. Internal logic also drive global clock networks internally generated global clocks asynchronous clears, clock enables, other control signals with high fan-out.
Cyclone Device Handbook, Volume
Altera Corporation- Preliminary March 2007
Clock Networks
Table shows connectivity clock sources global networks.
Table 6-2. Global Clock Network Connections (Part Global Clock Network Clock Sources
CLK0/DIFFCLK_0p CLK1/DIFFCLK_0n CLK2/DIFFCLK_1p CLK3/DIFFCLK_1n CLK4/DIFFCLK_2p CLK5/DIFFCLK_2n CLK6/DIFFCLK_3p CLK7/DIFFCLK_3n CLK8/DIFFCLK_5n CLK9/DIFFCLK_5p CLK10/DIFFCLK_4n CLK11/DIFFCLK_4p CLK12/DIFFCLK_7n CLK13/DIFFCLK_7p CLK14/DIFFCLK_6n CLK15/DIFFCLK_6p PLL1_c0 PLL1_c1 PLL1_c2 PLL1_c3 PLL1_c4 PLL2_c0 PLL2_c1 PLL2_c2 PLL2_c3 PLL2_c4 PLL3_c0 PLL3_c1
Global Clock Networks Cyclone Devices
EP3C16 through EP3C80 Devices Only
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Clock Networks PLLs Cyclone Devices
Table 6-2. Global Clock Network Connections (Part Global Clock Network Clock Sources
PLL3_c2 PLL3_c3 PLL3_c4 PLL4_c0 PLL4_c1 PLL4_c2 PLL4_c3 PLL4_c4 DPCLK0 DPCLK1 DPCLK7 CDPCLK0 CDPCLK7 DPCLK2 CDPCLK1 CDPCLK2 DPCLK5 DPCLK7 DPCLK4 DPCLK6 DPCLK6 DPCLK5 DPCLK6 DPCLK3 CDPCLK4 CDPCLK3 DPCLK8 DPCLK11 DPCLK9 DPCLK10 DPCLK5 DPCLK2 DPCLK4
Global Clock Networks Cyclone Devices EP3C16 through EP3C80 Devices Only
Cyclone Device Handbook, Volume
Altera Corporation- Preliminary March 2007
Clock Networks
Table 6-2. Global Clock Network Connections (Part Global Clock Network Clock Sources
DPCLK3
Note Table 6-2:
EP3C5 EP3C10 have only PLLs This only applies EP3C5 EP3C10 devices. These pins only apply EP3C16 devices larger. Only CDPCLK pins feed clock control block. other used regular pin.
Global Clock Networks Cyclone Devices EP3C16 through EP3C80 Devices Only
dedicated clock pins feed global clock networks, them general-purpose input pins feed logic array. However, when using them general-purpose input pins, they have support register must LE-based registers place register.
Altera Corporation-Preliminary March 2007
Cyclone Device Handbook, Volume
Clock Networks PLLs Cyclone Devices
Clock Control Block
clock control block drives global clock networks. Clock control blocks located each side device, close dedicated clock input pins. Global clock networks optimized minimum clock skew delay. Table lists sources that feed clock control block, which turn feeds global clock networks.
Table 6-3. Clock Control Block Inputs Input
Dedicated clock inputs
Description
Dedicated clock input pins drive clocks global signals, such synchronous asynchronous clears, presets, clock enables onto given global clock networks.
Dual-purpose clock (DPCLK CDPCLK) inputs
DPCLK CDPCLK pins bidirectional
dual function pins that used high fanout control signals, such protocol signals, TRDY IRDY signals PCI, DDR, global clock network. Clock control blocks which have inputs driven internal logic will able drive inputs. counter outputs drive global clock network. drive global clock network through logic array routing enable internal logic (Logic Elements) drive high fan-out, skew signal path. Clock control blocks which have inputs driven internal logic will able drive inputs.
outputs Internal logic
Cyclone devices, dedicated clock input pins, counter outputs, dual-purpose clock inputs, internal logic feed clock control block each global clock network. output from clock control block turn feeds corresponding global clock network. This global clock drive input clock control block inputs outputs another dedicated clock input pins. clock control blocks device periphery there maximum clock control blocks available Cyclone device.
Cyclone Device Handbook, Volume
Altera Corporation- Preliminary March 2007
Clock Networks
control block functions:
Dynamic global clock network clock source selection Global clock network power-down (dynamic enable disable)
Figure shows clock control block. Figure 6-1. Clock Control Block Notes (1), (2), (3),
Clock Control Block Internal Logic DPCLK CDPCLK Static Clock Select Enable/ Disable Global Clock
CLK[n CLK[n CLK[n CLK[n]
inclk1 inclk0 CLKSWITCH
Static Clock Select
CLKSELECT[1.0]
Internal Logic
Notes Figure 6-1:
clkswitch signal either through configuration file dynamically when using manual switchove
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