Cyclonefield programmable gate array family based 1.5-V, 0.13-µm, all-
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C51001-1.2
Cyclonefield programmable gate array family based 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities 20,060 logic elements (LEs) Kbits RAM. With features like phaselocked loops (PLLs) clocking dedicated double data rate (DDR) interface meet SDRAM fast cycle (FCRAM) memory requirements, Cyclone devices cost-effective solution data-path applications. Cyclone devices support various standards, including LVDS data rates megabits second (Mbps), 33-MHz, 32-bit peripheral component interconnect (PCI), interfacing with supporting ASSP ASIC devices. Altera also offers low-cost serial configuration devices configure Cyclone devices. following shows main sections Cyclone FPGA Family Data Sheet: Section Page
Features Functional Description Logic Array Blocks. Logic Elements MultiTrack Interconnect 2-12 Embedded Memory. 2-18 Global Clock Network Phase-Locked Loops. 2-29 Structure 2-39 Power Sequencing Socketing 2-55 IEEE Std. 1149.1 (JTAG) Boundary Scan Support SignalTap Embedded Logic Analyzer Configuration Operating Conditions Power Consumption Timing Model Software. Device Pin-Outs Ordering Information
Altera Corporation October 2003
Preliminary
Cyclone Device Handbook, Volume
Features
Cyclone device family offers following features:
2,910 20,060 LEs, Table 294,912 bits (36,864 bytes) Supports configuration through low-cost serial configuration device Support LVTTL, LVCMOS, SSTL-2, SSTL-3 standards Support 33-MHz, 32-bit standard High-speed (640 Mbps) LVDS support Low-speed (311 Mbps) LVDS support 311-Mbps RSDS support PLLs device provide clock multiplication phase shifting eight global clock lines with clock resources available logic array block (LAB) Support external memory, including SDRAM (133 MHz), FCRAM, single data rate (SDR) SDRAM Support multiple intellectual property (IP) cores, including Altera MegaCore functions Altera Megafunctions Partners Program (AMPPSM) megafunctions.
Table 1-1. Cyclone Device Features Feature
blocks (128 bits) Total bits PLLs Maximum user pins Note Table 1-1:
This parameter includes global clock pins.
EP1C3
2,910 59,904
EP1C4
4,000 78,336
EP1C6
5,980 92,160
EP1C12
12,060 239,616
EP1C20
20,060 294,912
Preliminary
Altera Corporation October 2003
Features
Cyclone devices available quad flat pack (QFP) space-saving FineLine packages (see Table through 1-3).
Table 1-2. Cyclone Package Options Counts Device
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Notes Table 1-2:
TQFP: thin quad flat pack. PQFP: plastic quad flat pack. Cyclone devices support vertical migration within same package (i.e., designers migrate between EP1C3 device 144-pin TQFP package EP1C6 device same package)
100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin 324-Pin 400-Pin (1), FineLine FineLine FineLine
Table 1-3. Cyclone FineLine Package Sizes Dimension
Pitch (mm) Area (mm2) Length width
100-Pin TQFP
144-Pin TQFP
240-Pin PQFP
1,024 34.6 34.6
256-Pin FineLine
324-Pin FineLine
400-Pin FineLine
Altera Corporation October 2003
Preliminary
Cyclone Device Handbook, Volume
Preliminary
Altera Corporation October 2003
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