Designing Programming Complete HiSeCTM-based System This applicat

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Designing Programming Complete HiSeCTM-based System This applicat

Datasheet Thumbnail

Top Searches for this datasheet

AN-985
Designing Programming Complete HiSeCTM-based System
This application note explains design, program implement complete high security (remote keyless entry) system based Fairchild Semiconductor NM95HS01/02 HiSeC Rolling Code Generator MM57HS HiSeC Rolling Code Decoder. broken down into several sections which provide detailed information developing constituent subsystems such transmitter, receiver decoder. last section provides information programming system microcontroller EEPROM, integrating system components. This application note also provides necessary circuit schematics, board layouts, code listings assist designer developing complete system.
Fairchild Application Note
KEY1 KEY2 RFEN
Transmitter Design
This section briefly discusses important design points consider when implementing transmitter based NM95HS01 HiSec Generator.
BASIC HARDWARE
Figure shows simple transmitter based NM95HS01 HiSeC Rolling Code Generator chip. This version HiSeC device clocked with network; NM95HS02 version clocked with crystal oscillator. switch inputs connected directly grounded, single pole switches. These device inputs have internal pull-up resistors reduce external component count. indicator used transmitter design provide visual device transmitting. output controls base transistor, which forms tuned amplifier based filter. RFEN output used ground tuned circuit.
RFEN
FIGURE Transmitter using NM95HS01 HiSeC Rolling Code Generator
coding formats type formats which relatively easy decode. format duty cycle, which allows transmitter achieve higher peak power. formats modulated versions coding format more suitable transmitter applications. duty cycle number pulses these modes allow user refine circuit power usage.
CODING TRANSMISSION FORMATS
HiSeC device eleven coding formats available transmitting data-seven applications four applications. Complete waveform details coding formats given data sheet NM95HS01/02 HiSeC Rolling Code Generator. details their particular usage transmitter applications discussed here. coding format narrow bandwidth, require clock recovery circuit ease signal decoding; however, once clock signal been recovered, data decoding achieved exclusive-ORing data clock streams. This format-like format 2-has level that independent data transmitted. coding format formats, provide constant transmit energy message, assuming signal transmission during logic HIGH. user should note that high times these formats different, which important consideration when designing transmission preamble sync timing.
Windows® registered trademark Microsoft Corporation.
CODING TIMING BLOCK
prescalers HiSeC generator timing block configurable, allow user time base coding formats. Either prescaler output used time base coding format external clock sufficiently frequency, scaled properly. However, output first prescaler generally intended with transmitter, while second prescaler divides signal further with transmitter. complete explanation prescalers, examples choosing scaling factors, found data sheet NM95HS01/02 HiSeC Generator.
1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
AN-985
DATA FIELD USAGE TRANSMISSION FRAMES
implement efficient transmitter decoder designs, important understand purpose individual fields transmission frame. These discussed briefly below. preamble field, enabled, transmitted once with first frame provide known, recognizable signal "wake microcontroller receiver-decoder circuit. fixed format times logic HIGH, time logic LOW, eight zeroes encoded user-selected format. desired, this field separated completely from frame eight times. This achieved enabling sync field mode with zeroes (byte 0h). sync field, enabled, sent every frame. provides known timing reference pattern rest frame. eight bits sent sync frame fully programmable, encoded either standard coding format coding. desired, part sync field could used send extra identifier data replace extend fixed identifier field. field, enabled, sent every frame. length bits. field sent selected coding format. contents fully programmable, provides unique identifier each facilitate decoding, identify particular applications where decoder used with several keys. also used basis fixed code generator application. data field sent every frame. This 4-bit field transmitted using selected coding format. indicates which keys have been pressed, whether sync frame being sent, whether battery level transmitter low. dynamic code field sent every frame. length bits. Increasing field length provides additional security. field sent selected coding format, provides secure rolling code which changes with each transmission. sync frame, this field replaced initialization field. parity field, enabled, 8-bit field sent with each frame using selected coding format. bytewise exclusive ORing bytes frame from sync field dynamic code field, serves check data integrity. stop present frames. used delimit frame coding formats that require definite end. formats need this delimiter distinguish between penultimate frame. coding modes where delimiting required, stop read "1".
timeout EEPROM enabled, device will enter HALT mode after approximately seconds.
TRANSMISSION INDICATION
Either RFEN outputs NM95HS01/02 used indicate device transmission. output active during pause, whereas RFEN output active during frame transmission.
Receiver Decoder Design
This section describes design HiSeC receiver-decoder system using 8-bit microcontroller receiver. begin considering general receiver designs, then this discussion starting point more specific HiSeC receiver-decoder system. receiver-decoder system discussed here designed with Fairchild Semiconductor COP888CG microcontroller MM57HS HiSeC Rolling Code Decoder. System design will considered four major sections: general RF/IR receiver design, decoder logic design, decoder software design, detailed explanation implement HiSeC rolling code algorithm with sample software code provided.
GENERAL RF/IR RECEIVER DESIGN
This section discusses several basic design issues, example receiver system designs described some detail. Since most systems utilize transmission, most design focus here systems.
Receivers
Some design parameters engineers encounter with receiver circuit design discussed below. receivers applications typically high frequency circuits that operate over range MHz. These circuits generally have power consumption requirements mA), must operate over wide temperature range (-40°C +85°C). modulation scheme most commonly used applications amplitude modulation, usually form pulse width modulation (PWM). This because transmitters that provide bursts pulses, instead transmitting energy continuously, designed radiate more power while still meeting requirements. receivers also tend high-Q circuits which helps improve error rates. receiver example presented Figure superregenerative type receiver. This means oscillator turns itself predetermined rate, allowing power consumption reduced. This super-regenerative receiver uses groundedbase amplifier (Q1) increase sensitivity reduce detector radiation. functions detector, which basically oscillator that turns itself rate. detected signal conditioned dual operational amplifier, half which used amplify low-level signal, other half used comparator drive decoder this circuit,a µVpeak input signal yields approximately signal output With these levels, peak signalto-RMS noise figure output approximately which allows satisfactory decoding.
TRANSMISSION OUTPUT POLARITY
TxPol EEPROM determines quiescent state output line. this "0", quiescent output level will logic LOW. "1", quiescent output level will logic HIGH, coding formats will inverted. TxPol should used drive base transistor, shown example transmitter circuit Figure TxPol should used drive diode series with current limiting resistor.
TRANSMITTER TIME-OUT
Transmitters based HiSeC device protected against premature battery drain caused held period time causing continuous transmission data frames.
www.fairchildsemi.com
AN-985
+12V
LM317 VOUT
47µF 240k 8.2k
1.5k 500pF 0.005 270pF ANTENNA COIL
0.001 LM358B LM358A 4.7k TEST POINT OUTPUT
0.002 5.6k 2.2pF
470pF 2.4k 4.7k 33pF
5.6M
COIL 0.005
RFC1
MPSH MPSH 2N2907 2N2222A RFC1: 0.35µH
1.8k
FIGURE Super-Regenerative Receiver
center frequency (fC) circuit varied changing with little effect receiver sensitivity. output produces appropriate logic level pulses COP888CG microcontroller. voltage regulator required this circuit since detector circuit power supply rejection capability, small irregularities power supply voltage, ripple load variations, could cause loss data. properly operating receiver should have very narrow pulses peak, kHz-400 rate) across Receiver operation checked using test point. Here, with input signal, there should approximately 0.2V peak-to-peak noise. This test point used tune receivers transmitters together maximum response.
Receivers
far, discussion focused receivers, applications have similar requirements. There basically stages involved implementing receiver system. first stage amplifies incoming signal, followed limiter stage that limits signal. third stage provides bandpass filter, fourth stage used demodulate signal. Next, integrator circuit used sharpen demodulated pulse, finally, last stage uses comparator ensure appropriate logic level output. Figure shows basic design stages receiver stage.
VOUT
AMPLIFIER
LIMITER
BAND PASS
DEMODULATOR
INTEGRATOR
COMPARATOR
FIGURE Block Diagram Receiver DECODER SYNCHRONIZATION
There primary methods ensuring synchronization between HiSeC generator decoder-using sync frame, performing forward calculation rolling code. first method establishesinitial synchronization, resynchronization, between devices. second method maintains synchronization between devices. forward calculation, decoder "forward-calculates" predetermined number codes ahead (known code window) searching code match. This procedure allows decoder that previously synchronized with generator miss more transmitted codes, still find match. This could occur, example, transmitter range, activated user's pocket. other method synchronization required initialize decoder, resynchronize transmitter decoder after battery change, replace key, code window exceeded. This method requires sync frame.
www.fairchildsemi.com
AN-985
sync frame contains enough information decoder learn completely. decoder software decide whether should accept sync frames, under what conditions. sync frame, data field zeros, implying that been pressed, condition that impossible when sending normal data frame. This allows software detect sync frame easily.
codes) keys case accidental activation, missed code transmission. last design consideration number type receiverdecoder outputs necessary utilize transmitted information. complete receiver-decoder system implemented with COP888CG easily designed accomodate several outputs that each sink loads. These outputs might used transfer data from receiver-decoder other systems automobile. These outputs could RS-232C, SPI, Microwire, Class J1850 protocol outputs. Please refer COP8selection guide details configurable controller methodology. Figure shows complete receiver-decoder example circuit which uses super-regenerative receiver module, input capture capability COP888CG, serial EEPROM store multiple information count-ahead table, outputs, Microwire port multi-system communication.
DECODER LOGIC DESIGN
focus here designing decoder system using COP888CG microcontroller implement functions signal capture, frame decoding, program execution. When HiSeC transmission frame received, decoder system process frame different ways. first method route output receiver circuit directly microcontroller's input ports, where software polls input port continuously search valid frame. However, there problems with this approach. first problem with power consumption. microcontroller polls input port continuously, must remain powered most CMOS microcontrollers consume between normal operating mode. automotive applications where continous battery drain problem, this unacceptable. second problem that decoder constantly trying decode unwanted transmissions, which reduces time available other tasks performed microcontroller. applications where power consumption critical, processor multitasking used, such garage door openers, this method valid design option. second method takes advantage capture ability COP888CG, requires much less operating current. This microcontroller operates clock speeds MHz, contains timing capture registers that measure external frequencies time events precisely. These attributes make COP888CG microcontroller good choice this design. COP888CG capture registers used capture incoming data frame, allows microcontroller powered down wait frame sent. COP888CG uses approximately idle mode with clock, which less current drain. Capturing also allows microcontroller ignore frame that received frequency other than that expected. This capturing capability also allows potential secondary input from ignition system. This secondary input could used safety measure allow decoder system recognize accept sync frame only when physically placedin ignition system. This design option would allow user possibility resynchronizing decoder synchronization lost. Another consideration good decoder design information storage. multiple keys used, decoder must have method storing information recognize these multiple keys. Information storage also required resynchronization cases where data frame transmission been missed. serial EEPROM, interfaced microcontroller, solves these problems. Each key's seed code stored this additional memory, that each time activated, next several valid codes calculated stored. EEPROM also used provide additional depth "code window" establishing forward code look-up table (with number future valid
DECODER SOFTWARE DESIGN
decoder system software broken down into four major routines: Main Control, Decode, Rolling Code Generation, Output Control. Main Control routine begins initializing microcontroller variables, registers, port states. then places microcontroller into idle mode. When microcontroller awakens from idle mode sensing rising edge port pins, Main Control routine reads captured data, then passes control Decode routine. Decode routine times data frame restores original transmission reception capability. then returns control back Main Control routine, which stores unencoded frame RAM. Program control then passed Rolling Code Generation routine which compares received data frame table frames previously calculated each key. match found, writes logic into "match register". match found, routine writes logic into match register. Control again handed back Main Control routine, which checks match register passes appropriate commands output register. this point, program control passed Output Control routine which executes appropriate output response. Finally, Main Control routine powers microcontroller down waits next data frame input capture.
HISEC ROLLING CODE ALGORITHM
section above described general approach writing software code decoder system. more detailed information about HiSeC rolling code generation algorithm, implement functions software, please contact your local Fairchild Sales office.
Programming Information
This section briefly discusses program verify nonvolatile EEPROM configuration memory on-board NM95HS01/ rolling code generator. also discusses program verify NM93C86A Serial EEPROM which used receiverdecoder system. programmer, built around Fairchild Semiconductor COP888CG microcontroller, been developed program both NM95HS01/02 HiSeC Generator NM93C86A. Schematics, board layouts, software listings programmer provided, along with additional contact information.
www.fairchildsemi.com
AN-985
NM95HS01/02 PROGRAMMING OVERVIEW
NM95HS01/02 HiSeC Rolling Code Generator four pins that used programming. These pins. functions chip select line which times write cycle 104-bit non-volatile memory. functions data strobe. serves serial clock input, acts data pin.
www.fairchildsemi.com
AN-985
+12V
LM317 VOUT
47µF 240k 8.2k
1.5k 500pF 0.005 270pF ANTENNA COIL
0.001 LM358B LM358A 4.7k TEST POINT
0.002 5.6k 2.2pF
470pF 2.4k 4.7k 33pF
5.6M
COIL 0.005
RFC1
1.8k
7805 0.01µF 0.1µF
RESET 5V_ZENER IGNITION 7.5k L509B L509A OUTPUT OUTPUT 7.5k
XTAL 33pF
33pF
1n914
COP88CG
MICROWIRE
10µF
MPSH MPSH 2N2907 2N2222A RFC1: 0.35µH
NM93C86A
FIGURE Complete Receiver
Three voltages required program device. These Supervoltage (nominal 12V), Read/Write Voltage (VRW), Ground (0V). Read Write modes only entered applying supervoltage device specific sequence. This precludes risk device entering these modes during normal operation. supervoltage mode select only. NM95HS01/02 generator on-board charge pump supply necessary programming voltage cells. programming protocol EEPROM array on-board NM95HS01/02 matches Microwire format closely;
www.fairchildsemi.com
AN-985
however, there some important differences. first difference need supervoltage select programming mode. Another difference requirement that clock input clocked minimum 1500 times upon power-up ready device programming. This allow internal state machines registers complete their power sequences.
2,048 byte-wide memory; tied VCC, left floating, 1,024 word-wide configuration enabled. internal pull-up resistor assures that floating will pulled high. Figure shows arrangement NM93C86A.
COP888CG fully static, power, 8-bit CMOS microcontroller that contains 4,096 bytes store program code, bytes store register data. 8-bit input, 8-bit output, 8-bit bidirectional ports. microcontroller uses Microwire interface that allows communicate with variety serial EEPROMs. Figure shows arrangement COP888CG micrcocontroller.
RESET
COP88CG
NM93C86A
COP888CG DESCRIPTION
FIGURE NM93C86A Arrangement PROGRAMMER DESCRIPTION
programmer described here built using schematics, board layouts, software listings provided this application note. designed interface with IBM-compatible through RS-232C serial port. standard terminal communication software package (e.g., Windows®, PC-Talk, Kermit, etc.) used communicate with programmer. programmer designed accept specific 2-byte command sequences that tell programmer which function perform. example, command tells programmer write next bytes data EEPROM array NM95HS01/02. command tells programmer read 13-bytes EEPROM memory HiSeC device. This allows verification write operation. Similarly, command causes programmer write next 2,048 bytes data NM93C86A EEPROM array, command causes programmer read 2,048 bytes NM93C86A EEPROM memory into allowing write operation verified.
DEVICE PROGRAMMING
information given this application note provides basic tools instructions needed program verify EEPROM array contained on-board HiSeC rolling code generator, external EEPROM used provide memory capability HiSeC decoder. When programming these devices, care should taken obey timing requirements programming procedures each part. Requirements, procedures waveforms given detail individual data sheets.
FIGURE COP888CG Microcontroller Arrangement NM93C86A DESCRIPTION
NM93C86A 16,384-bit non-volatile serial EEPROM that configured either 1,024 2,048 architecture. configuration determined state pin. tied low, NM93C86A configured
www.fairchildsemi.com
Schematic Listing
+12V
XTAL
L509A +12V
L509B
C1V+ C2VDS14C232 T1IN T1OUT T2IN T2OUT R1OUT R1IN R2OUT R2IN L509C L509D
COP88CG
HiSeC HiSeC RFEN/LED TXOUT CK0/LED
RESET 7512 7805
+12V
+12V
Q1-Q4 2N2222A C1-C4 10µF C5-C8 18pF R3-R6 4.7k XTAL 10MHz R7-R8 6.8k R9-R10 D1-D3 1N914 C8-C14 0.01µF 100µF
GANG
AN-985
www.fairchildsemi.com
FIGURE Programmer Schematic
NM93C86A
EEPROM
AN-985
Layer
HiSeC Programmer GANG
EEPROM HiSeC
www.fairchildsemi.com
AN-985
Bottom Layer
www.fairchildsemi.com
AN-985
Fairchild Semiconductor ;-;File: Prog.asm ;Date 5-15-94 ;Author: Charles Watts ;Description: ;Assemble code HiSEC transmitter external EEPROM programmer ;The programmer uses pins HiSEC programming. ;The programmer uses Microwire interface portG external ;EEPROM programming. programmer uses pins portL UART ;communication. Char1 Char2 from UART ;Functions Read HiSEC data Write HiSEC data Read 98C86A Write 93C86A .incld cop888cg.inc .sect one, addl: .dsb addh: .dsb byt: .dsb pole: .dsb cnt: .dsb tmp: .dsb .endsect .sect code, rom, abs=0 Initialize port register data -delay1 delay2 page start: PORTD, ;Reset HiSEC PORTFC, #031 ;Set output PORTCD, ;Reset port sbit MSEL, CNTRL ;Enable Microwire sbit CNTRL ;Set Microwire strobe PSR, #050 :Set UART PAUD, #00b ;Set UART 9600, sbit PORTLC ;Enable UART sbit ENUI rbit PORTLC rbit PORTLC addh, ;Clear Variables addl, pole, PORTD, ;Set Main Routine -main: getchar ;Get byte from UART store byte ifeq byt, #030 byt=0 then jump subroutine HiSEC HiSEC ifeq byt, #031 byt=1 then jump subroutine main ;loop until branch getchar ;Get byte from UART store byte ifeq byte, #032 byt=2 read eeprom contents eerd
www.fairchildsemi.com
AN-985
ifeq HiSEC:
byt, #033 eewt pole, main
byt=3 write data eeprom ;pole=0
init ;clock 1,536 times getchar ;Get byte from UART store byte IFEQ byt, #034 byt=4 read hisec hird ifeq byt, #035 byt=5 write data into hisec hiwt main main routine Subroutines will follow -;-;Subroutine: eewt ;Description: purpose this routine write 2048 bytes data into NM93C86A data received from UART. address then incremented. ;-eewt: ewen ;Enable write mode #tmp ;load pointer top: getchar ;Get byte from UART store byte ;get first char [b+] ;store pointer location getchar ;get second char [b-] ;store pointer location ascbin ;convert ascii binary ;store eeprom count ;advance address ifeq pole, pole=1 return main ;-;Subroutine: eerd ;Description: purpose this routine read 2048 bytes data into NM93C86A data then sent UART. address incremented. ;-eerd: #tmp ;load pointer eelp: ;Get data from eeprom binasc ;convert binary ascii [b+] `store first ascii char putchar; ;send data [b-] ;store second ascii char putchar ;send data count ;advance address ifeq pole, pole=1 return main eelp ;-;Subroutine: hiwt ;Description: purpose this routine write bytes data into HiSEC NVM. data received from UART.
www.fairchildsemi.com
AN-985
hiwt:
sbit PORTD ;set sbit PORTD ;set rbit PORTD ;set rbit PORTD ;set ;reset carry page, ;set number bytes read bytes) cnt, ;set first read lpt1: sbit PORTD ;set #tmp getchar ;Get byte from UART store byte [b+] getchar [b-] ascbin rbit PORTD ;set lpt: ifbit byt=1 skip sbit PORTD ;set K2=5V sbit PORTD ;clock once rbit PORTD rbit PORTD ifeq cnt, ;has byte been written rst1 jump reset ;increment ;shift byte once right ;loop rst1: ;set rbit PORTD ;set K1=5V lpt2: ifbit PORTI ;loop until internal programming complete lpt2 drsz page ;decrement page lpt1 sbit PORTD rbit PORTD rbit PORTD rbit PORTD rbit PORTD rbit PORTD sbit PORTD ;-;Subroutine: hird ;Description: purpose this routine read bytes data from HiSEC NVM. data sent UART. ;-hird: sbit PORTD ;set sbit PORTD sbit PORTD sbit PORTD rbit PORTD ;set page, ;read bytes cnt, ;set read ;reset carry
www.fairchildsemi.com
AN-985
;clear variable sbit PORTD ;set sbit PORTD ;set sbit PORTD ;set sbit PORTD ;set sbit PORTD ;dummy rbit PORTD sbit PORTS ;dummy lpt3: sbit PORTD ;set high PORTI ;Read input must I7-bit rbit PORTD ;set ;change reverse ifeq cnt, ;has byte been read rst2 send byte ;increment lpt3 rst2: #tmp binasc [b+] putchar ;send data putchar ;reset drsz page ;decrement page lpt3 rbit PORTD rbit PORTD rbit PORTD rbit PORTD rbit PORTD rbit PORTD sbit PORTD sbit PORTD ;-;Subroutine: putchar ;Description: purpose this routine send byte data UART. ;-putchar: ;load tbuf with TBUF
www.fairchildsemi.com
AN-985
ifbit ENUR ;check flag transfer delay1, brt: delay2, #0ff del: drsz delay2 drsz delay1 ;-;Subroutine: getchar ;Description: purpose this routine receive byte data store into variable byt. ;-getchar: ifbit ;wait received byte getchar rst: RBUF ;get transmitted byte into ;-;Subroutine: ;Description: purpose this routine byte data from NM93C86A EEPROM store value into variable byt. ;-get: sbit PORTGD ;set high addh ;load high address #030 ;and with command op-code SIOR ;put shift register sbit .BUSY, ;send lp4: ifbit BUSY, addl ;load address SIOR ;put shift register sbit BUSY, ;send lp5: ifbit BUSY, SIOR, sbit BUSY, ;read dummy rbit BUSY, sbit BUSY, ;read EEPROM byte lp6: ifbit BUSY, SIOR ;load that byte into rbit PORTGD ;reset ;-;Subroutine: ;Description: purpose this routine write byte data NM93C86A. ;-put: sbit PORTGD ;set high addh ;load high address #028 with op-code SIOR ;load into shift register sbit BUSY, ;send lp7: ifbit BUSY,
www.fairchildsemi.com
AN-985
addl ;load address SIOR ;load into shift register sbit BUSY, ;send lp8: ifbit BUSY, ;put data into shift register SIOR ;send sbit BUSY, lp9: ifbit BUSY, lp10: ifbit PORTGP ;wait programming cycle lp10 lp11: ifbit PORTGP ;wait fall lp12 lp11 lp12: rbit PORTGD ;reset ;-;Subroutine: ewen ;Description: purpose this routine enable NM93C86A programming cycles. ;-ewen: sbit PORTGD ;set high SIOR, #026 ;load op-code into shift register sbit BUSY, ;send lp13: ifbit BUSY, lp13 SIOR, ;send zero's sbit BUSY, lp14: ifbit BUSY, lp14 rbit PORTGD ;reset ;-;Subroutine: count ;Description: purpose this routine keep track EEPROM address pointer. ;-count: addl ;load address ifeq #0ff ;increment. address ;equals then jump ;next routine. addl addh ;check high address ifeq reset address ;and exit. reset high address addh addl, pole, ;set pole flag host routine addh, addl, byt, ;set accedenal branch will ;not occur. ;-;Subroutine: init ;Description: purpose this routine clock hisec
www.fairchildsemi.com
AN-985
input 1,536 times. ;-init: delay1, ;upper limit loop1 delay2, #0ff ;lower limit loop2 sbit PORTD ;clock 1536 rbit PORTD ;chip registers drsz delay2 ;set. loop2 drsz delay1 loop1 ;-;Subroutine: binary ascii ;Description: purpose this routine convert binary byte into ascii characters. ;-binasc: push ;put accum stack swap ;Most significant nibble gets printed first #0ff ;swap upper lower nibbles ifgt #009 #007 #030 ;convert ascii [b+] ;Least significant nibble gets printed last #009 ;pull from stack ifgt #009 #007 #030 ;convert ascii [b-] ;-;Subroutine: ascii binary ;Description: purpose this routine convert ascii characters into binary byte. ;-ascbin: ;reset carry [b+] ;load first character ifget #039 ;jump next condition #00f ;else mask high nibble ;jump shift ifgt #046 ;jump next condition #00f ;else mask high nibble #009 ;add convert nibble ;jump shift ifgt #006 ;jump next condition #00f else mask high nibble #009 ;add convert nibble swap ;shift bits ;store into variable [b-] ;load first character ifgt #039
www.fairchildsemi.com
AN-985
;jump next condition #00f ;else mask high nibble ;jump shift ifgt #046 ;jump next condition #00f ;else mask high nibble #009 ;add convert nibble ;jump shift ifgt #066 ;jump next condition #00f ;else mask high nibble #009 ;add convert nibble ;logical ;store byte variable .end start ;-end program-
THIRD PARTY SUPPORT
following contact information provided assist user selecting maintaining COP8xx NM95HS01/02 development tools.
Manufacturer Product
Xeltek-Superpro
Phone Numbers
U.S.: Europe: Asia: BBS: (408) 524-1929 +49-5722-203125 +65-276-6433 (408) 245-7082 (408) 263-6667/(800) 967-4776 +31-921-7844 +886-2-9173005 (408) 262-6438 (Switzerland) (Taipei, Taiwan) (Germany) (Singapore)
System General Turpro-1 Universal Programmer
U.S.: Europe: Asia: BBS:
programmer described this application note ordered fron Fairchild, order information NM95HSPROG.
Life Support Policy
Fairchild's products authorized critical components life support devices systems without express written approval President Fairchild Semiconductor Corporation. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: 1793-856858 Deutsch Tel: 8141-6102-0 English Tel: 1793-856856 Tel: 1-6930-3696 Italiano Tel: 2-249111-1
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
www.fairchildsemi.com

Designing Programming Complete HiSeCTM-based System This applicat

Top Searches for this datasheet

Other recent searches