CS5331-32 CS5331 CS5332 OCB-AES Simplex Encryption/Decryption cor

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CS5331-32 CS5331 CS5332 OCB-AES Simplex Encryption/Decryption cor

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High Performance OCB-AES Simplex Encryption/Decryption Cores
CS5331-32
CS5331 CS5332 OCB-AES Simplex Encryption/Decryption cores1 designed provide simultaneous data privacy authenticity digital broadband, wireless, multimedia systems. These high performance application specific silicon cores combine efficiency authentication with high security Rijndael encryption algorithms, offering state-of-the-art authenticated-encryption scheme. CS5331 CS5332 cores provide high security functionality OCB-AES different applications based importance required speed size. CS5331 Compact OCB-AES core suitable applications like PDAs wireless LANs where small size crucial. CS5332 High Speed OCB-AES core appropriate applications such wireless high speed network servers where speed operation more critical. Amphion CS5331 CS5332 cores available both ASIC programmable logic versions that have been hand crafted Amphion deliver high performance while minimizing power consumption silicon area.
Camera
WLAN Base
WLAN Remote
Display
Motion JPEG
Access Control OCB-AES CS5331/32 Physical Layer
Access Control OCB-AES CS5331/32 Physical Layer
Motion JPEG
WLAN 802.11
Figure Example Secure Wireless Surveillance System Using OCB-AES Cores
FEATURES
Encryption/Decryption same device Fully compliant with Rijndael NIST FIPS Offset Codebook Mode (OCB) On-the-fly generation 128-bit data block 128-bit keys only
Secure corporate communications Virtual Private Networks (VPN) Video conferencing Voice services Personal mobile communications Video phones Point-to-Point Wireless Secure distance learning Corporate Training Universities
APPLICATIONS
Secure electronic transactions Medical files Financial files Securities exchange eCommerce Point-of-Sale
Patent Pending
Amphion continues expand family application-specific cores http://www.amphion.com current list products
CS5331-32
CS5330 SYMBOL DESCRIPTION
Table describes input output ports (shown graphically Figure CS5331/32 OCB-AES Simplex Encryption/Decryption cores. Unless otherwise stated, signals active high least significant bit.
High Performance OCB-AES Simplex Encryption/Decryption Cores
MODE LOAD DADDR DTYPE GTAG DNUMB
CS5331/32 OCB_AES Simplex Core
DSTAT QSTRB QADDR QTYPE QNUMB
Figure CS5331-32 Symbol
Table CS5331-32 OCB-AES Simplex Encryption/Decryption Core Interface Signal Definitions Signal
MODE LOAD DADDR DTYPE GTAG DNUMB DSTAT QSTRB QADDR QTYPE QNUM
Width (Bits)
Description
Mode select; Encryption, Decryption Load data enable data block address data block type; Key, Nonce, Plaintext, Last Plaintext Generate input data Key, Nonce Plaintext Number valid bytes, applied last plaintext block only System clock, rising edge active Asynchronous reset input data port status; DSTAT[1]: Core loading indicator, DSTAT[0]: Core ready indicator. data port status indicator cycle latency output strobe indicating ciphertext/tag word valid output data address; lowest 32-bit word output block type; Ciphertext, Last Ciphertext, output data Ciphertext Number valid output bytes, applied last ciphertext block only
FUNCTIONAL DESCRIPTION
Offset Codebook Mode (OCB) parallelizable block cipher mode operation that provides both authenticity privacy when combined with encryption algorithms. contained draft NIST FIPS modes operation symmetric block ciphers OCB-AES been implemented IEEE wireless standard 802.11i. Amphion CS5331 CS5332 combine mode with Rijndael algorithm provide efficient high security functionality wide range operations. These cores integrate Amphion CS5265 CS5275 Simplex Encryption/Decryption cores with CS5330 Simplex Controller core. CS5331 CS5332 OCB-AES simplex Encryption/ Decryption cores excellent compliments other Amphion cores. example, they combined with CS6750 MPEG-4 decoder rapidly construct secure duplex video conferencing system, they combined with CS3500/CS3600 family Turbo Coders achieve secure, error free data transmission. Figure represents overview diagram CS5331/CS5332.
Key, Nonce Plaintext/Ciphertext
Input Buffer
Amphion Half-Duplex Core
Output Buffer
Plaintext/ Ciphertext
Control Signals
Control Logic
Checksum Generator
Offset Scheduler
Figure Block Diagram CS5331/CS5332 Simplex OCB-AES Encryption/Decryption Cores
CS5331-32
High Performance OCB-AES Simplex Encryption/Decryption Cores
AVAILABILITY IMPLEMENTATION INFORMATION
Hardware accelerated technology governed internationally export regulations. Amphion OCB-AES cores listed this datasheet have been officially reviewed classified Department Trade Industry Bureau Export Administration. These cores licensed immediate export following countries: Austria Denmark Hungary Zealand Spain Australia Belgium Canada Czech Republic Finland France Germany Greece Ireland Italy Japan Luxembourg Netherlands Norway Poland Portugal Sweden Switzerland United Kingdom United States
delivery other destinations, please contact Amphion. Approval subject applicable export regulations. Licensees Amphion cores responsible complying with applicable requirements re-export electronics containing technology. cores contain technology that patent pending Philip Rogaway University California, Davis. Vendors obliged contact Rogaway order license technology.
ASIC CORES
applications that require high performance, cost high integration ASIC, Amphion delivers application specific silicon cores that pre-optimized targeted ASIC technology Amphion experts. Consult your local Amphion representative product specific performance information, current availability individual products, lead times ASIC core porting.
Table CS5331-32 ASIC Cores Using TSMC Process Standard Cell Libraries
PRODUCT LOGIC GATES CYCLES OPERATION TIMING CONSTRAINT (MHz) DATA RATE (MBITS/SEC)a 2327
CS5331TK CS5332TK
Sustained data rate refers maximum throughput plaintext/ciphertext.
Table CS5331-32 ASIC Cores Using TSMC Process Standard Cell Libraries
PRODUCT LOGIC GATES CYCLES OPERATION TIMING CONSTRAINT (MHz) DATA RATE (MBITS/SEC)a 3490
CS5331CS5332
Sustained data rate refers maximum throughput plaintext/ciphertext.
PROGRAMMABLE LOGIC CORES
ASIC prototyping projects requiring fast time-to-market, Amphion programmable logic cores offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions.
Table CS5331-32 Family Programmable Logic Core Using Xilinx Virtex2-5 PRODUCT
CS5331X2 CS5332X2
LOGIC USED (Slices)
1826 2184
MEMORY USED (BRAM)
CYCLES OPERATION
CLOCK SPEED (MHz)
DATA RATE (MBITS/Sec)a
Sustained data rate refers maximum throughput plaintext/ciphertext
Table CS5331-32 Family Programmable Logic Core Using Altera APEX20KE-1 PRODUCT
CS5331AA CS5332AA
LOGIC USED (LE)
4511 5081
MEMORY USED (ESB)
CYCLES OPERATION
CLOCK SPEED (MHz)
DATA RATE (MBITS/Sec)a
Sustained data rate refers maximum throughput plaintext/ciphertext
CS5331-32
High Performance OCB-AES Simplex Encryption/Decryption Cores
Typical ASIC FPGA Design Flow (Conceptual)
Data Formats Supplied AMPHION
System-Level Code simulation
Accurate Model
Hardware Development
Simulation
Simulation Models
Logic Synthesis
Testbench
(VHDL Verilog)
Gate-level analysis (timing functional)
Netlists
(Verilog, VHDL, EDIF, .bd)
Physical Design
FPGA Programming Files
Figure Design Data Formats Supplied Amphion
CS5331-32
ABOUT AMPHION
Amphion (formerly Integrated Silicon Systems) leading supplier speech coding, video/ image processing channel coding application specific silicon cores system-on-a-chip (SoC) solutions broadband, wireless, mulitmedia markets
High Performance Simplex OCB-AES Encryption/Decryption Cores
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04/02 Publication DS5331-32 v1.0

CS5331-32 CS5331 CS5332 OCB-AES Simplex Encryption/Decryption cor

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