CS5321-22 CS5321 CS5322 OCB-AES Encryption cores1 designed provid

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CS5321-22 CS5321 CS5322 OCB-AES Encryption cores1 designed provid

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High Performance OCB-AES Encryption Cores
CS5321-22
CS5321 CS5322 OCB-AES Encryption cores1 designed provide simultaneous data privacy authenticity digital broadband, wireless, multimedia systems. These high performance application specific silicon cores combine efficiency authentication with high security Rijndael encryption algorithms, offering state-of-the-art authenticated-encryption scheme. CS5321 CS5322 cores provide high security functionality OCB-AES different applications based importance required speed size. CS5321 Compact OCB-AES suitable applications like PDAs Wireless LANs where small size crucial. CS5322 High Speed OCB-AES appropriate applications such Wireless high speed network servers where speed operation critical. Amphion CS5321 CS5322 cores available both ASIC programmable logic versions that have been hand crafted Amphion deliver high performance while minimizing power consumption silicon area.
WLAN Base
WLAN Remote
Motion JPEG Camera ADPCM
Access Control OCB-AES CS5321/22 Physical Layer WLAN 802.11
Access Control OCB-AES CS5331/32 Physical Layer
Motion JPEG ADPCM
Display
Figure Example Secure Video Conferencing System Using OCB-AES Cores
Patent Pending
CS5321/CS5322 FEATURES
Fully compliant with Rijndael NIST FIPS Offset Codebook mode (OCB) On-the-fly generation 128-bit data block 128-bit keys only 32-bit
APPLICATIONS
Secure electronic transactions Medical files E-Commerce Financial files Securities exchange Point-of-Sale Secure corporate communications Virtual Private Networks (VPN) Video conferencing Voice services Personal mobile communications Video phones Point-to-Point Wireless Secure distance learning Corporate training Universities
Amphion continues expand family application-specific cores http://www.amphion.com current list products
CS5321-22
High Performance OCB-AES Encryption Cores
CS5320 SYMBOL DESCRIPTION
Table describes input output ports (shown graphically Figure CS5321 CS5322 Encryption cores. Unless otherwise stated, signals active high least significant bit.
LOAD DADDR DTYPE GTAG DNUMB
CS5321/22
DSTAT QSTRB QADDR QTYPE QNUMB
Figure CS5321-22 Symbol
Table CS5321-22 OCB-AES Encryption Interface Signal Definitions Signal
LOAD DADDR DTYPE GTAG DNUMB DSTAT QSTRB QADDR QTYPE QNUMB
Width (Bits)
Load data enable data block address
Description
data block type; Key, Nonce, Plaintext, Last Plaintext Generate input data Key, Nonce Plaintext Number valid bytes, applied last plaintext block only System clock, rising edge active Asynchronous reset input data port status; DSTAT[1]: Core loading indicator, DSTAT[0]: Core ready indicator. data port status indicator cycle latency output strobe indicating ciphertext/tag word valid output data address; lowest 32-bit word output block type; Ciphertext, Last Ciphertext, output data Ciphertext Number valid output bytes, applied last ciphertext block only
FUNCTIONAL DESCRIPTION
Offset Codebook Mode (OCB) parallelizable block cipher mode operation that provides both authenticity privacy when combined with encryption algorithms. contained draft NIST FIPS modes operation symmetric block ciphers OCB-AES been implemented IEEE wireless standard 802.11i. Amphion CS5321 CS5322 combine mode with Rijndael algorithm provide efficient high security functionality wide range operations. These cores integrate Amphion CS5220/CS5230 Encryption cores with CS5320 Controller core. CS5321 CS5322 OCB-AES Encryption cores excellent compliments other Amphion cores. example, they combined with CS6750 MPEG-4 decoder rapidly construct private broadcast system, they combined with CS4190 ADPCM codec achieve secure, high speed, high channel-count speech processing Voiceover-Packet (VoP) systems. Figure represents overview diagram CS5321/CS5322.
Key, Nonce Plaintext
Input Buffer
Amphion Core
Output Buffer
Ciphertext
Control Signals
Control Logic
Checksum Generator
Offset Scheduler
Figure Block Diagram CS5321/CS5322 OCB-AES Encryption Cores
AVAILABILITY IMPLEMENTATION INFORMATION
Hardware accelerated technology governed internationally export regulations. Amphion OCB-AES cores listed this datasheet have been officially reviewed classified Department Trade Industry Bureau Export Administration. These cores licensed immediate export following countries: Austria Denmark Hungary Zealand Spain Australia Belgium Canada Czech Republic Finland France Germany Greece Ireland Italy Japan Luxembourg Netherlands Norway Poland Portugal Sweden Switzerland United Kingdom United States
delivery other destinations, please contact Amphion. Approval subject applicable export regulations. Licensees Amphion cores responsible complying with applicable requirements re-export electronics containing technology. cores contain technology that patent pending Philip Rogaway University California, Davis. Vendors obliged contact Rogaway order license technology.
ASIC CORES
applications that require high performance, cost high integration ASIC, Amphion delivers application specific silicon cores that pre-optimized targeted ASIC technology Amphion experts. Consult your local Amphion representative product specific performance information, current availability individual products, lead times ASIC core porting.
Table CS5321-CS5322 ASIC Cores Using TMSC Process Standard Cell Libraries PRODUCT
CS5321TK CS5322TK
LOGIC GATES
CYCLES OPERATION
TIMING CONSTRAINT (MHz)
DATA RATE (MBITS/Sec)a
2327
Sustained data rate refers maximum throughput plaintext/ciphertext
Table CS5321-CS5322 ASIC Cores Using TMSC Process Standard Cell Libraries PRODUCT
CS5321CS5322
LOGIC GATES
CYCLES OPERATION
TIMING CONSTRAINT (MHz)
DATA RATE (MBITS/Sec)a
3490
Sustained data rate refers maximum throughput plaintext/ciphertext
PROGRAMMABLE LOGIC CORES
ASIC prototyping projects requiring fast time-to-market programmable logic solution, Amphion programmable logic cores offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions.
Table CS5321-CS5322 Programmable Logic Cores Using Xilinx Virtex2-5 PRODUCT
CS5321X2 CS5322X2
LOGIC USED (LUT)
1376 1543
MEMORY USED (BRAM)
CLOCK SPEED (MHz)
DATA RATE (MBITS/Sec)
Table CS5321-CS5322 Programmable Logic Cores Using Altera APEX20KE-1 PRODUCT
CS5321AA CS5322AA
LOGIC USED (LE)
3322 3605
MEMORY USED (ESB)
CLOCK SPEED (MHz)
DATA RATE (MBITS/Sec)
CS5321-22 High Performance OCB-AES Encryption Cores
ABOUT AMPHION
Amphion (formerly Integrated Silicon Systems) leading supplier speech coding, video/ image processing channel coding application specific silicon cores system-on-a-chip (SoC) solutions broadband, wireless, mulitmedia markets. CORPORATE HEADQUARTERS Amphion Semiconductor Malone Road Belfast Northern Ireland, Tel: Fax: +44.28.9050.4000 +44.28.9050.4001
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04/02 Publication DS55321-22 V1.0

CS5321-22 CS5321 CS5322 OCB-AES Encryption cores1 designed provid

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