CS5250-80 CS5250-80 series decryption cores1 designed achieve dat

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CS5250-80 CS5250-80 series decryption cores1 designed achieve dat

Datasheet Thumbnail

Top Searches for this datasheet

High Performance Decryption Cores
CS5250-80
CS5250-80 series decryption cores1 designed achieve data privacy authenticity digital broadband, wireless, multimedia systems. These high performance application specific silicon cores support (Rijndael) algorithm described NIST Federal Information Processing Standard. They used conjunction with CS5210-40 series Amphion encryption cores rapidly construct complete security solutions. CS5200 family cores available both ASIC programmable logic versions that have been hand crafted Amphion deliver high performance while minimizing power consumption silicon area.
Satellite Downlink Ultra High Speed
Ground Station Uplink Ultra High Speed Ground Station Uplink Metropolitan Link Ultra High Speed Long Distance Location High Speed Location High Speed Location Metropolitan Link
Figure Example Satellite Point-to-Point Secure Communication Scheme Using
Patent pending
DECRYPTION CORE FEATURES
Table CS5250-80 Features Glance CS5250 Standard
Fully compliant with NIST FIPS 128-bit data block 128-, 192-, 256-bit keys on-line selectable 128-bit keys only 32-bit 128-bit Electronic Codebook mode (ECB) Output Feedback mode (OFB) Cipher Block Chaining mode (CBC) Cipher Feedback mode (CFB)
CS5260 Compact
CS5270 High Speed
CS5280 Ultra High Speed
Amphion continues expand family application-specific cores http://www.amphion.com current list products
CS5250-80
High Performance Decryption Cores
CS5250-80 SYMBOL DESCRIPTION
Table gives descriptions input output ports (shown graphically Figure CS5250-80 series decryption cores. Unless otherwise stated, signals active high bit(0) least significant bit.
APPLICATIONS
Electronic financial transactions eCommerce Banking Securities exchange Point-of-Sale Secure corporate communications Storage Area Networks (SAN) Virtual private networks (VPN) Video conferencing Voice services Personal mobile communications Video phones Point-to-Point Wireless Wearable computers Secure environments Satellite communications Surveillance systems Network appliances
DAADR LDKY IKEY KADDR (CS5250 only) LOAD
Figure CS5250-80 Symbol
KSTAT DSTAT
CS5250-80
QSTRB QADDR
Table CS5250-80 Standard Rijndael Decryption Interface Signal Definitions Signal
DADDR LDKEY IKEY KADDR
Width (Bits)
(128) (128)
Description
Cipher text data (128-bit width CS5280) Cipher text data address, lowest 32-bit word Load inverse cipher Inverse cipher (128-bit width CS5280) Inverse cipher address, lowest 32-bit word Inverse cipher size select (CS5250 only) When Selects 128-bit When Selects 192-bit When Selects 256-bit Load ciphertext enable System clock, rising edge active Asynchronous reset port status, when Asserted, loading cipher keys allowed Input port status next cycle after text D[3] (the highest word 128-bit clock) loaded, DSTAT will De-asserted indicate decryption progress. will Asserted when core ready loading highest word next 128-bit text. lower three words loaded anytime period when DSTAT depending key-size selection. Output strobe indicating Plaintext word valid Plaintext data address, lowest 32-bit word Plaintext data (128-bit width CS5280)
LOAD KSTAT DSTAT
QSTRB QADDR
(128)
bits wide standard; bits wide compact/high speed cores; applicable ultra high speed core
CS5250-80
High Performance Decryption Cores
four versions Amphion decryption cores follow block diagram shown Figure CS5200 decryption cores outstanding matches with other Amphion cores. instance they combined with CS6650 MPEG2 Decoder easily provide secure high definition closed-circuit system, they combined with CS3252 Codec part secure wireless access point. Amphion encryption/decryption cores also excellent choice security incorporated into broadband switches, routers, firewalls remote access concentrators. Likewise, cores ideal Secure Socket Layer (SSL) channel used servers, gateways other access applications requiring high number parallel channels carry eCommerce.
FUNCTIONAL DESCRIPTION
Rijndael algorithm iterated block cipher that encrypts decrypts data 128-bit data blocks using 128-bit, 192-bit, 256-bit key. algorithm consists initial data/key addition Nine, eleven thirteen rounds when length 128-bits, 192-bits, 256-bits respectively final round which variation typical round
Figure represents block diagram Rijndael decryption algorithm. Rijndael round transforms data using permutations, non-linear substitutions, additions Galois field multiplications. Rijndael schedule consists parts: Expansion expands cipher into linear array 4-byte words Round Selection selection required number Round Keys from expanded array
Control Logic
Ciphertext
Input Buffer
Round Transformations
Output Buffer
Plaintext
Inverse
Buffer
Scheduler
Figure Block Diagram CS5250-80 Series Decryption Cores
AVAILABILITY IMPLEMENTATION INFORMATION
Hardware accelerated technology governed internationally export regulations. Amphion cores listed this datasheet have been officially reviewed classified Department Trade Industry Bureau Export Administration. These cores licensed immediate export following countries: Austria Australia Belgium Canada Czech Republic Denmark Hungary Zealand Spain Finland Ireland Netherlands Sweden France Italy Norway Switzerland Germany Japan Poland United Kingdom Greece Luxembourg Portugal United States
delivery other destinations, please contact Amphion. Approval subject applicable export regulations. Licensees Amphion cores responsible complying with applicable requirements re-export electronics containing technology.
ASIC CORES
applications that require high performance, cost high integration ASIC, Amphion delivers application specific silicon cores that pre-optimized targeted ASIC technology Amphion experts. Consult your local Amphion representative product specific performance information, current availability individual products, lead times ASIC core porting.
Table CS5250-80 Family ASIC Cores using TSMC 180nm Process Standard Cell Libraries
PRODUCT LOGIC GATES CYCLES OPERATION
TIMING CONSTRAINT (MHz)
DATA RATE (MBITS/Sec) 581a 492b 426c
CS5250TK
19.2K
CS5260TK CS5270TK CS5280TK
16.4K 283K
2,327 25,600
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
CS5250-80
High Performance Decryption Cores
PROGRAMMABLE LOGIC CORES
ASIC prototyping projects requiring fast time-to-market programmable logic solution, Amphion delivers programmable logic core solutions that offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions.
Table CS5250-80 Family Programmable Logic Cores using Altera APEX20KE-1
PRODUCT CS5250AA LOGIC USED (LE) 1560 MEMORY USED (ESB) CYCLES OPERATION CS5260AA CS5270AA 1176 1481
CLOCK SPEED (MHZ) 74.1
DATA RATE (MBITS/Sec) 215a 182b 158c
80.4 62.5
Table CS5250-80 Family Programmable Logic Cores Using Xilinx VirtexE-8
PRODUCT CS5250XV SLICES MEMORY USED (BRAM) CYCLES OPERATION CS5260XV CS5270XV CS5280XV 4626
CLOCK SPEED (MHZ) 84.7
DATA RATE (MBITS/Sec) 246a 208b 181c
8704
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Table CS5250-80 Family Programmable Logic Cores Using Xilinx Virtex2-5
PRODUCT CS5250XV SLICES MEMORY USED (BRAM) CYCLES OPERATION CS5260XV CS5270XV CS5280XV 3998
CLOCK SPEED (MHZ)
DATA RATE (MBITS/Sec) 290a 369b 426c
91.5
1064 9344
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Table CS5250-80 Family Programmable Logic Cores using Actel ProASICPlus
PRODUCT CS5250RQ DEVICE APA300 CORE CELLS 3449 MEMORY USED (CELLS) CYCLES OPERATION CS5260RQ CS5270RQ CS5280RQC APA450 APA300 2485 3167
CLOCK SPEED (MHz) 36.36
DATA RATE (MBITS/Sec) 105a 133b 154c
39.73 31.08
116a 361a
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Typical ASIC FPGA Design Flow (Conceptual)
ASVC Data Formats Supplied AMPHION
System-Level Code simulation
Accurate Model
Hardware Development
Simulation
Simulation Models
Logic Synthesis
Testbench
(VHDL Verilog)
Gate-level analysis (timing functional)
Netlists
(Verilog, VHDL, EDIF, .bd)
Physical Design
FPGA Programming Files
Figure Design Data Formats Supplied Amphion
CS5250-80
ABOUT AMPHION
High Performance Decryption Cores
CORPORATE HEADQUARTERS Amphion Semiconductor Malone Road Belfast Northern Ireland, Tel: Fax: +44.28.9050.4000 +44.28.9050.4001
Amphion (formerly Integrated Silicon Systems) leading supplier speech coding, video/ image processing channel coding application specific silicon cores system-on-a-chip (SoC) solutions broadband, wireless, mulitmedia markets Web: www.amphion.com Email: info@amphion.com
WORLDWIDE SALES MARKETING Amphion Semiconductor, 2001 Gateway Place, Suite 130W Jose, 95110 Tel: Fax: (408) 1248 (408) 1239
EUROPEAN SALES Amphion Semiconductor CBXII, West Wing 382-390 Midsummer Boulevard Central Milton Keynes England, Tel: Fax: 1908 847109 1908 847580
CANADA EAST COAST SALES Amphion Semiconductor, Montreal Quebec Canada Tel: Fax: (450) 5544 (450) 5543
SALES AGENTS
Voyageur Technical Sales 6205 Airport Road Building Suite Toronto, Ontario Canada L4V1E1 Tel: Fax: (905) 0361 (905) 4986 Phoenix echnologies Gavish Street Kfar-Saba, 44424 Israel SPINNAKER SYSTEMS Hatchobori Bldg. 3-12-8 Hatchobori, Chuo-ku Tokyo 104-0033 Japan
Fax:
+972 7644 +972 7644
Tel: Fax:
3551 2275 3351 2614
JASONTECH, Hansang Building, Suite Bangyidong 181-3, Songpaku Seoul Korea 138-050
SPS-DA Science Park #03-19 Aquarius Singapore Science Park Singapore 117628 Fax: 9070 9071
Tel: Fax:
6700 8600
2001-02 Amphion Semiconductor Ltd. rights reserved. Amphion, Amphion logo "Virtual Components Converging World" trademarks Amphion Semiconductor Ltd. others property their respective owners.
10/02 Publication DS5210/40 v1.2

CS5250-80 CS5250-80 series decryption cores1 designed achieve dat

Top Searches for this datasheet

Other recent searches