CS5210-40 CS5210-40 series encryption cores1 designed achieve dat

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High Performance Encryption Cores
CS5210-40
CS5210-40 series encryption cores1 designed achieve data privacy authenticity digital broadband, wireless, multimedia systems. These high performance application specific silicon cores support (Rijndael) algorithm described NIST Federal Information Processing Standard. They used conjunction with CS5250-80 series Amphion decryption cores rapidly construct complete security solutions. CS5200 family cores available both ASIC programmable logic versions that have been handcrafted Amphion deliver high performance while minimizing power consumption silicon area.
Compact
Virtual Private Network VPN) Ultra High Speed
Financial Institution High Speed
Figure Example Secure Mobile Financial Transactions Using
Patent Pending
ENCRYPTION CORE FEATURES
Table CS5210-40 Features Glance CS5210 Standard
Fully compliant with NIST FIPS 128-bit data block 128-, 192-, 256-bit keys on-line selectable 128-bit keys only 32-bit 128-bit Electronic Codebook mode (ECB) Output Feedback mode (OFB) Cipher Block Chaining mode (CBC) Cipher Feedback mode (CFB)
CS5220 Compact
CS5230 High Speed
CS5240 Ultra High Speed
Amphion continues expand family application-specific cores http://www.amphion.com current list products
CS5210-40
High Performance Encryption Cores
CS5210-40 SYMBOL DESCRIPTION
Table gives descriptions input output ports (shown graphically Figure CS5210-40 series encryption cores. Unless otherwise stated, signals active high bit(0) least significant bit.
APPLICATIONS
Electronic financial transactions eCommerce Banking Securities exchange Point-of-Sale Secure corporate communications Storage Area Networks (SAN) Virtual private networks (VPN) Video conferencing Voice services Personal mobile communications Video phones Point-to-Point Wireless Wearable computers Secure environments Satellite communications Surveillance systems Network appliances
DADDR LDKY KADDR (CS5210 only) LOAD
Figure CS5210-40 Symbol
KSTAT DSTAT
CS5210-40
QSTRB QADDR
Table CS5210-40 Standard Rijndael Encryption Interface Signal Definitions Signal
DADDR LDKEY KADDR
Width (Bits)
(128) (128)
Description
Plaintext data (128-bit width CS5240) Plaintext data address, lowest 32-bit word Load enable Cipher (128-bit width CS5240) Cipher address, lowest 32-bit word Cipher size select (CS5210 only) When Selects 128-bit When Selects 192-bit When Selects 256-bit Load Plaintext enable System clock, rising edge active Asynchronous reset port status. When Asserted, loading cipher keys allowed Input port status next cycle after text D[3] (the highest word 128-bit clock) loaded, DSTAT will De-asserted indicate encryption progress. will Asserted when core ready loading highest word next 128-bit text. lower three words loaded anytime period when DSTAT depending key-size selection. Output strobe indicating Cipher text word valid Cipher text data address, lowest 32-bit word Cipher text data (128-bit width CS5240)
LOAD KSTAT DSTAT
QSTRB QADDR
(128)
bits wide standard; bits wide compact/high speed cores; applicable ultra high speed core
CS5210-40
High Performance Encryption Cores
four versions Amphion encryption cores follow block diagram shown Figure CS5200 encryption cores excellent complements other Amphion cores. instance they combined with CS6100 Motion JPEG Encoder rapidly construct secure surveillance system, they combined with CS4191 ADPCM codec achieve secure, high speed, high channel-count speech processing Voice-over-Packet (VoP) systems. Amphion encryption/decryption cores also excellent choice security incorporated into broadband switches, routers, firewalls remote access concentrators. Likewise, cores ideal Secure Socket Layer (SSL) channel used servers, gateways other access applications requiring high number parallel channels carry eCommerce.
FUNCTIONAL DESCRIPTION
Rijndael algorithm iterated block cipher that encrypts decrypts data 128-bit data blocks using 128-bit, 192-bit, 256-bit key. algorithm consists initial data/key addition Nine, eleven thirteen rounds when length 128-bits, 192-bits, 256-bits respectively final round which variation typical round
Figure represents block diagram Rijndael encryption algorithm. Rijndael round transforms data using permutations, non-linear substitutions, additions Galois field multiplications. Rijndael schedule consists parts: Expansion expands cipher into linear array 4-byte words Round Selection selection required number Round Keys from expanded array
Control Logic
Plaintext
Input Buffer
Round Transformations
Ciphertext Output Buffer
Buffer
Scheduler
Figure Block Diagram CS5210-40 Series Encryption Cores
AVAILABILITY IMPLEMENTATION INFORMATION
Hardware accelerated technology governed internationally export regulations. Amphion cores listed this datasheet have been officially reviewed classified Department Trade Industry Bureau Export Administration. These cores licensed immediate export following countries: Austria Australia Belgium Canada Czech Republic Denmark Hungary Zealand Spain Finland Ireland Netherlands Sweden France Italy Norway Switzerland Germany Japan Poland United Kingdom Greece Luxembourg Portugal United States
delivery other destinations, please contact Amphion. Approval subject applicable export regulations. Licensees Amphion cores responsible complying with applicable requirements re-export electronics containing technology.
ASIC CORES
applications that require high performance, cost high integration ASIC, Amphion delivers application specific silicon cores that pre-optimized targeted ASIC technology Amphion experts. Consult your local Amphion representative product specific performance information, current availability individual products, lead times ASIC core porting.
Table CS5210-40 Family ASIC Cores Using TSMC Process Standard Cell Libraries
PRODUCT LOGIC GATES CYCLES OPERATION
TIMING CONSTRAINT (MHz)
DATA RATE (MBITS/SEC) 581a 492b 426c
CS5210TK
18.2K
CS5220TK CS5230TK CS5240TK
14.8K 203K
2327 25600
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
CS5210-40
High Performance Encryption Cores
PROGRAMMABLE LOGIC CORES
ASIC prototyping projects requiring fast time-to-market programmable logic solution, Amphion delivers programmable logic core solutions that offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions.
Table CS5210-40 Family Programmable Logic Cores using Altera APEX20KE-1
PRODUCT CS5210AA LOGIC USED (LE) 1452 MEMORY USED (ESB) CYCLES OPERATION
CLOCK SPEED (MHz) 77.8
DATA RATE (MBITS/Sec) 226a 191b 166c
CS5220AA CS5230AA 1167 85.9
Table CS5210-40 Family Programmable Logic Cores using Xilinx VirtexE-8
PRODUCT CS5210XE SLICES MEMORY USED (BRAM) CYCLES OPERATION CS5220XE CS5230XE CS5240XE 2397
CLOCK SPEED (MHz) 94.7
DATA RATE (MBITS/Sec) 275a 233b 202c
91.2 77.2
1061 9882
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Table CS5210-40 Family Programmable Logic Cores using Xilinx Virtex2-5
PRODUCT CS5210X2 SLICES MEMORY USED (BRAM) CYCLES OPERATION CS5220X2 CS5230X2 CS5240X2 2181
CLOCK SPEED (MHz) 117.3
DATA RATE (MBITS/Sec) 341a 289b 250c
120.2 113.7
1323 10880
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Table CS5210-40 Family Programmable Logic Cores using Actel ProASICPlus
PRODUCT CS5210RQ DEVICE APA150 CORE CELLS 3169 MEMORY USED (CELLS) CYCLES OPERATION CS5220RQ CS5230RQ CS5240RQ APA150 APA300 6144 2570 NM/A 43.43 40.19 CLOCK SPEED (MHz) 29.48 DATA RATE (MBITS/Sec) 108b 125c 128a 467a
Implementation 128-bit length Implementation 192-bit length Implementation 256-bit length
Typical ASIC FPGA Design Flow (Conceptual)
ASVC Data Formats Supplied AMPHION
System-Level Code simulation
Accurate Model
Hardware Development
Simulation
Simulation Models
Logic Synthesis
Testbench
(VHDL Verilog)
Gate-level analysis (timing functional)
Netlists
(Verilog, VHDL, EDIF, .bd)
Physical Design
FPGA Programming Files
Figure Design Data Formats Supplied Amphion
CS5210-40
ABOUT AMPHION
High Performance Encryption Cores
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07/02 Publication DS5210/40 v1.2

CS5210-40 CS5210-40 series encryption cores1 designed achieve dat

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