CS5010-40 CS5010-CS5040 DES/3DES Encryption/Decryption cores desi

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CS5010-40 CS5010-CS5040 DES/3DES Encryption/Decryption cores desi

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DES/3DES Encryption/Decryption Cores
CS5010-40
CS5010-CS5040 DES/3DES Encryption/Decryption cores designed achieve data privacy digital broadband, wireless, multimedia systems. These high performance application specific silicon cores support Data Encryption Standard (also referred Data Encryption Algorithm) described NIST Federal Information Processing Standard 46-3. They offer efficient means providing both Triple encryption decryption core order rapidly construct complete security solutions. DES/3DES family cores available both ASIC programmable logic versions that have been hand crafted Amphion deliver high performance while minimizing power consumption silicon area.
Patient Room Camera
Nurse Station
MPEG-2 Encoder
MPEG-2 Decoder
Security Gateway High Speed DES/3DES Encoder 10/100-Base T-Hub
Security Nurse Gateway Station HighPC Speed DES/3DES Decoder
Figure Example Secure Audio/Video Based Remote Patient Monitoring System Using DES/3DES
ENCRYPTION CORE FEATURES
Table CS5010-40 Features Glance CS5010 Ultra Compact
Fully compliant with NIST FIPS 46-3 Triple Support 32-bit 128-bit 28-bit Input Port 56-bit Input Port EDE2 EDE3 Triple (112- 168-bit length)
CS5020 Compact
CS5030 High Speed
CS5040 Ultra HIgh Speed
Amphion continues expand family application-specific cores http://www.amphion.com current list products
CS5010-40
DES/3DES Encryption/Decryption Cores
APPLICATIONS
Electronic financial transactions eCommerce Banking Securities exchange Point-of-Sale Secure corporate communications Storage Area Networks (SAN) Virtual Private Networks (VPN) Video conferencing Voice services
Personal mobile communications Video phones Point-to-Point Wireless Wearable computers Secure environments Satellite communications Surveillance systems Network appliances
DATA ENCRYPTION ALGORITHM
Data Encryption Algorithm iterated block cipher with Feistel structure that encrypts decrypts data 64bit data blocks using 56-bit key. algorithm consists initial permutation input data Sixteen rounds same process round final inverse initial permutation data
Figure represents block diagram Data Encryption Algorithm. round transforms data using permutations, additions non-linear substitutions. schedule consists three parts: Permutation remove eight redundant parity bits within 64-bit key, permute Scheduled Circular Shifting permuted circularly shifted according schedule either bits, left right. Compression 56-bit shift compressed using another permutation, rearrangement, obtain 48-bit subkey.
Triple Data Encryption Algorithm offers increased security extending bits, thus greatly reducing effectiveness exhaustive searches "brute-force" attacks. Triple simply three successive operations sequence encrypt-decrypt-encrypt, decrypt-encrypt-decrypt decrypting data.
Figure Algorithm Structure
FUNCTIONAL DESCRIPTION
Amphion series DES/3DES cores offer complete solution maintaining legacy functionality modern data encryption needs, offering simple interface, internal external memory usage, external keyspace processing, highly efficient design offering unparalleled performance. CS5010 Ultra Compact DES/3DES CS5020 Compact DES/3DES Cores designed offer efficient high performance means both Triple encryption/decryption, with emphasis reduced resource usage. CS5030 High Speed DES/3DES Core offers increased data throughput comparison Compact Cores, while still achieving highly efficient hardware implementation. CS5040 Ultra High Speed DES/3DES Core designed provide high performance solution while still achieving relatively resource usage. Ultra Compact DES/3DES Core capable standard modes operation. these added modes operation Compact, High Speed Ultra High Speed DES/3DES Cores subject conditions. example, impractical fully pipelined core perform mode, data throughput hardware would have substantially reduced order support feedback operation between output input core. versions Amphion DES/3DES cores follow block diagram shown Figure DES/3DES cores excellent complements other Amphion cores. instance they combined with CS6650 MPEG-2 Decoder rapidly construct secure patient monitoring system, they combined with CS4191 ADPCM codec achieve secure, high speed, high channel-count speech processing Voice-over-Packet (VoP) systems. Amphion encryption/decryption cores also excellent choice security incorporated into broadband switches, routers, firewalls remote access concentrators. Likewise, cores ideal Secure Socket Layer (SSL) channel used servers, gateways other access applications requiring high number parallel channels carry eCommerce.
Control Logic
Plaintext/ Ciphertext
Input Buffer
Round Transformations
Output Buffer
Ciphertext/ Plaintext
Buffer
Scheduler
Figure Block Diagram DES/3DES Cores
CS5010-40
DES/3DES Encryption/Decryption Cores
CS5210-40 SYMBOL DESCRIPTION
Table describes input output ports (shown graphically Figure CS5010-40 series DES/3DES encryption cores. Unless otherwise stated, signals active high bit(0) least significant bit.
DADDR DLOAD KADDR KLOAD MODE TRIPLE
Figure CS5010-40 DES/3DES Symbol
DSTAT
DES/3DES
QSTRB QADDR
Table CS5010-40 DES/3DES Cores Interface Signal Definitions Signal
DADDR
Width (Bits)
Ultra High Speed) (Ultra Compact) (Compact) (High Speed) (Ultra High Speed) Ultra High Speed)
Description
Input Plaintext/Ciphertext data Input Plaintext/Ciphertext data address, lowest 32-bit word
DLOAD KADDR KLOAD MODE TRIPLE DSTAT
Load input Plaintext/Ciphertext enable Encryption data Encryption address, lowest 28-bit word Load encryption Encryption/Decryption mode select, Encryption. Decryption DES/3DES mode select, DES, 1:3DES Triple selection mode, 0:EDE2, EDE3 System clock, rising edge active Asynchronous reset Input port status This signal will Asserted when core ready loading highest word next 64-bit data block, highest word multiple input blocks available Compact High Speed cores. lower words loaded anytime period when DSTAT depending key-size selection Output strobe indicating Plaintext/Ciphertext word valid Output Plaintext/Ciphertext data address, lowest 32-bit word
QSTRB QADDR
(Ultra Compact) (Compact) (High Speed) (Ultra High Speed) Ultra High Speed)
Output Plaintext/Ciphertext data
CS5010-40
DES/3DES Encryption/Decryption Cores
AVAILABILITY IMPLEMENTATION INFORMATION
Hardware accelerated 3DES technology governed internationally export regulations. Amphion 3DES cores listed this datasheet available within License export following countries pending: Austria Denmark Hungary Zealand Spain Australia Belgium Canada Czech Republic Finland France Germany Greece Ireland Italy Japan Luxembourg Netherlands Norway Poland Portugal Sweden Switzerland United Kingdom United States
delivery other destinations, please contact Amphion. Approval subject applicable export regulations. Licensees Amphion 3DES cores responsible complying with applicable requirements re-export electronics containing 3DES technology.
ASIC CORES
applications that require high performance, cost high integration ASIC, Amphion delivers application specific silicon cores that pre-optimized targeted ASIC technology Amphion experts. Consult your local Amphion representative product specific performance information, current availability individual products, lead times ASIC core porting.
Table CS5210-40 DES/3DES Series ASIC Cores Using TSMC Process Standard Cell Libraries
PRODUCT LOGIC GATES CYCLES OPERATION TIMING CONSTRAINT (MHz) DATA RATE (MBITS/SEC) 1600 3200 12800 3DES DATA RATE (MBITS/SEC) 1067 4267
CS5010TK CS5020TK CS5030TK CS5040TK
7.9K 11.8K 21.8K 56.7K
PROGRAMMABLE LOGIC CORES
ASIC prototyping projects requiring fast time-to-market programmable logic solution, Amphion programmable logic core offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions.
Table CS5010-40 DES/3DES Programmable Logic Cores using Altera APEX20KE-1
PRODUCT LOGIC USED (LE) CYCLES OPERATION TIMING CONSTRAINT (MHz) DATA RATE (MBITS/SEC 3DES DATA RATE (MBITS/SEC)
CS5010AA CS5020AA CS5030AA CS5040AA
1190 1721 3212 9466
67.8 64.8 54.8 59.8
3827
1275
Table CS5010-40 DES/3DES Programmable Logic Cores using Xilinx Virtex2-5
PRODUCT LOGIC USED (LUT) SLICES CYCLES OPERATION TIMING CONSTRAINT (MHz) DATA RATE (MBITS/SEC 3DES DATA RATE (MBITS/SEC)
CS5010X2 CS5020X2 CS5030X2 CS5040X2
1261 2270 5484
1376 4305
96.7 90.3 80.7 91.0
1291 5824
1941
Table CS5010-40 DES/3DES Programmable Logic Cores using Actel Axcelerator
PRODUCT SILICON VENDOR DEVICE MAX. FREQUENCY (MHz) DATA THROUGHPUT (MBits/Sec) 3DES UTILIZATION AVAILABILITY R-CELLS C-CELLS
CS5010RR CS5020RR CS5030RR CS5040RR
Actel Actel Actel Actel
AX500 AX500 AX500 AX1000
2584
1194
1212 4162
1151 1715 3116 7179
Note: Speed grade
Table CS5010-40 DES/3DES Programmable Logic Cores using Actel ProASICPlus
PRODUCT SILICON VENDOR DEVICE MAX. FREQUENCY (MHz) DATA THROUGHPUT (MBits/Sec) 3DES UTILIZATION AVAILABILITY Logic Storage
CS5010RQ CS5020RQ CS5030RQ CS5040RQ
Actel Actel Actel Actel
APA150 APA150 APA300 APA600
1664
1923 2830 5253 11331
1192 3926
CS5010-40
ABOUT AMPHION
DES/3DES Encryption/Decryption Cores
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Amphion (formerly Integrated Silicon Systems) leading supplier speech coding, video/ image processing channel coding application specific silicon cores system-on-a-chip (SoC) solutions broadband, wireless, mulitmedia markets Web: www.amphion.com Email: info@amphion.com
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10/02 Publication DS5010/40 v1.1

CS5010-40 CS5010-CS5040 DES/3DES Encryption/Decryption cores desi

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