Demodulator CS3810 broadband wireless demodulator core been devel
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CS3810
Demodulator
CS3810 broadband wireless demodulator core been developed provide efficient highly optimized solution wireless data networks. Combined with CS3710 modulator core data transmission speeds 155Mbps achieved error rates. CS3810 suited applications areas such point-to-point WLAN, metropolitan area networks, wireless easily combined with CS5200 series cryptography cores create secure high speed data links. CS3810 provides integrated high performance complete baseband demodulation solution wireless data transmission. includes symbol timing recovery, adaptive filtering precise lock tracking ensure optimal data recovery under adverse channel conditions. This includes signalling control ADC, ensuring straight forward system integration deployment. combined block synchronisation scheme error control/ correction system included deliver reliable data recovery. core also includes straightforward microprocessor interface allowing setting demodulation parameters easy system integration.
Data Input Test Input
Data Encoding
Error Protection
Mapping
Test Input
Timing/symbol recovery
Spectral Shaping
TXI_OUT TXQ_OUT
Filtering
Decode Synchronisation
Error Correction Output Recovery formatter Control Registers Control Registers
Controller/ Processor CS3710 Broadband Wireless Modulator Core
Controller/ Processor
Data
CS3810 Broadband Wireless Demodulator Core
Figure Block Diagram CS3710/CS3810 Broadband Wireless Modulation/Demodulation Cores
FEATURES
Fully integrated Digital Baseband demodulator including timing symbol recovery error correction digital timing carrier recovery Wide carrier tracking range Acquisition time 10ms. Internal offset removal imbalance adjustment Programmable equalization adaptation rate Residual better than 10-12 Internal FIFO smooth data output Programmable carrier recovery loop constants damping factor Equalizer weights read/write-able from microprocessor
Forward Error Correction Features
overhead Concatenated RS-Convolutional interleaved system Interleaver employing Intelsat method, with depth Soft decision based Viterbi decoder, constraint length states) Input output start frame signals Internal correction Viterbi renormalization counters
Data Framing
Intelsat Style Frame/Superframe structure Superframe detection output sync signals
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CS3810
Demodulator
APPLICATIONS
Wireless Metropolitan Area Network Wireless Secure wireless Broadband voice, data video transmission
DATA ADDR
interface RXUSRCLK RESET RESTART ZIFMT AGCREF VCORNG HBWBLL FFKBLL LCKTHBLL LCKWINBLL INIPCLL AFCCLL NAFCCLL PILBWCLL DDLBWCLL MUCMAEQ MUDDEQ MapI MapQ MapStrb Test
INPUT/OUTPUT DESCRIPTION
Table describes input output ports (shown graphically Figure CS3810 demodulator core. static programming signals overwritten microprocessor interface except ZIFMT that only connection. Unless otherwise stated, control signals input data clocked outputs clocked rising edge 74MHz clock signal (CLK), control signals active high. overall architecture demodulator core illustrated Figure
Global control
Output Data control control
RXSYNC RXDATA AGCP
Input data setting settings
VCSTRB VCOV AGCOK AGCOK LCKBLL LCKCLL STATCLL FIFOERR LCKTCM LCKTUW TCMERR RSERR)U RSERR_L BLLSTRB BLLIQ BLLQI
CS3810 Broadband Wireless Demodulator
Lock Status
settings
Stats
Test Data
settings
RSERRPRD BYPASS UPTCM
Figure CS3810 Symbol
Symbol Timing Recovery Core (BLL/CLL) Decoder Core
Input Data
Filtering
Carrier Symbol Recovery
Phase Lock Stream Decode
Block Synchron -ization
Error Correction
Descrambling
Output
Deframing Formatting
Control Register Bank
Figure Block Diagram CS3810
Table CS3810 Demodulator Interface Signal Descriptions Name
GLOBAL CONTROLS RXUSRCLK RESET Input Input Input Input clock signal, generated phase locked sampling clock. Samples clocked rising edge Output clock signal. Samples clocked demodulator FIFO rising edge Asynchronous reset, active
Width
Description
Table CS3810 Demodulator Interface Signal Descriptions Name
RESTART
Input
Width
Description
Synchronous reset signal, active HIGH. restart acquisition process after activated. returns idle state after RESTART re-starts acquisition until lock achieved.
INPUT DATA ZIFMT Input Input sample format, static programming signal two's complement offset binary Input sample from DAC, symbol rate (74MHz), format determined ZIFMT Input sample from DAC, symbol rate (74MHz), format determined ZIFMT
SETTING AGCREF SETTINGS VCORNG
Input Input
Input
threshold reference, static programming signal
Input
frequency range selection, static programming signal, specifying corresponding Df/f0 when 12-bit control signal VCOV changes from middle maximal minimal value 1/8192 1/4092 actual Df/f0 necessarily accurate specified still functioning. only affects acquisition range speed. Costas pass filter H(f) gain factor selection, static programming signal 1/32 1/16 Frequency error pass filter gain factor selection before lock declared, static programming signal 1/2048 1/1024 1/512 1/256 Frequency error pass filter gain factor selection, after lock declared, static programming signal 1/16384 1/8192 1/4096 1/2048 Lock threshold selection, relative lock indicator value ideal signal, static programming signal lock detection window size selection, terms number 32-QAM symbols, static programming signal 16384 32768
HBWBLL
Input
FFKBLL
Input
LFFKBLL
Input
LCKTHBLL
Input
LCKWINBLL
Input
CS3810
Name
SETTINGS INIPCLL
Demodulator
Table CS3810 Demodulator Interface Signal Descriptions Width Description
Input
initial period selection, terms 32-QAM symbols, static programming signal, 16384 32768 When lock declared, switches from idle state initial state which equalizer into mode. acquisition starts after initial period. frequency offset estimate, static programming signal When use, uses scan counter mechanism estimate frequency offset. Every time when pull-in fails counter increased give frequency offset value until lock achieved. Number computations averaging period Simulation shows that noisy conditions selection gives more reliable frequency offset estimate pull-in (acquisition) mode bandwidth select 0.0015(55KHz) 0.003(110KHz) bandwidth approximated based assumption damping factor 0.71 decision-direct (tracking) mode bandwidth select 0.01(370KHz) 0.02(740KHz) bandwidth approximated based assumption damping factor 0.71 Equalizer select mode 1/1024 1/512 1/256 1/128 Equalizer select mode 1/8192 1/4096 1/2048 1/1024
AFCCLL
Input
NAFCCLL
Input
PILBWCLL
Input
DDLBWCLL
Input
MUCMAEQ
Input
MUDDEQ
Input
OUTPUT DATA RXSYNC RXDATA Output Output Output ready flag. Signals that valid output data present RXDATA port Received output data port
Table CS3810 Demodulator Interface Signal Descriptions Name Width Description
ERROR CORRECTION STATISTICS TCMERR RSERR_U RSERR_L CONTROL AGCP CONTROL VCOV Output control voltage, 12-bit offset-binary format, normalized according frequency range such that maximal value corresponds lowest frequency zero corresponds highest frequency, updated every four symbols (9.25 MHz, clock cycles) control voltage strobe, asserted cycles every clock cycles indicate update VCOV Output width-modulated pulse with period symbols. pulse width proportional input signal level. Output Output Output Reports number estimated errors decoded datastream Reports number errors corrected Reed Solomon Decoder (upper bits) Reports number errors corrected Reed Solomon Decoder (lower bits)
VCSTRB
Output
ERROR CORRECTION CONTROL RSERRPRD UPTCM BYPASS LOCK STATUS AGCOK LCKBLL LCKCLL STATCLL Output Output Output Output indicator, asserted when average peak sample level within +/-15% ideal level lock flag, asserted when lock declared retained, updated once every lock detection window lock flag, asserted when lock declared retained, updated every output symbol (two clock cycles) status, updated every output symbol (two clock cycles) 000: idle (equalizer initial mode, phase error 001: initial (equalizer CMA, phase error 010: (equalizer CMA, estimate frequency offset) 011: (equalizer CMA, scan counter increases) 100: pull-in (equalizer CMA, pull-in) 110: pull-in (equalizer CMA, pull-in) 111: Lock (equalizer tracking) When Asserted signifies output fifo overflowed data been dropped When asserted signifies decoder achieved lock When asserted signifies that block synchronization been achieved Input Input Input Static signal-sets duration over which statistics gathered Static signal used control operation decoder Static signal, when asserted decoder bypassed
FIFOERROR LCKTCM LCKUW
Output Output Output
CS3810
Name
TEST DATA BLLSTRB
Demodulator
Table CS3810 Demodulator Interface Signal Descriptions Width Description
Output
output sample strobe, cycle pulse every clock cycles, indicating peak transition samples after lock achieved peak sample transition sample output sample two's complement format output sample two's complement format decoder test input decoder test input Active strobe signal used sample MAPI MAPQ Static signal, when asserted MAPI MAPQ sampled otherwise demodulated data decoded normal
BLLIQ BLLQI MAPI MAPQ MapStrb MapTest
Output Output Input Input Input Input
MICROPROCESSOR INTERFACE DATA ADDR Tri-state Input Input Input Input 16-bit data 5-bit address Address latch enable Chip select, level sensitive active Write/Read control signal Write Read Output enable, level sensitive active LOW. demodulator drives data only when both active
Input
DEMODULATOR OVERVIEW
input demodulator directly from converter. samples received spectrum double symbol rate.
REED SOLOMON DECODING
Prior decoding block boundaries recovered. sync detection circuitry searches unique word similar scheme employed Intelsat IESS-308. Once locked sync detection module also repacks output stream into Reed Solomon symbols. delineated blocks de-interleaved Reed Solomon decoded. corrected errors reported reflected RSERR_U RSERR_L output ports during statistics gathering period.
loop implemented with external gain control element order achieve desired receiver dynamic range maintain proper input level ADC. module determines average power input signal compares programmed threshold. pulse width modulated signal output module. stream externally integrated used control voltage.
DESCRAMBLING
self synchronizing descrambler utilizing 220-1 pattern operates data stream thus randomizing recover original modulated input message. Data from descrambler written FIFO symbol rate clock output RXDATA rising edge RXUSRCLK.
TIMING RECOVERY
received data stream then enters symbol timing recovery loop, which consists resampling circuitry filtering, crosstalk removal, imbalance adjustment Digital Phase Locked Loop (DPLL). combined resampling matched filter used enable transfer input data stream from input data domain symbol rate domain.
LOCK INDICATION
number lock indicators provided status registers bits enable overall synchronisation status demodulator monitored. These are: Symbol timing recovery loop lock Carrier recovery loop lock decoder synchronized Unique word sync detection lock
CARRIER RECOVERY
recovered symbol rate data then enters carrier recovery loop demodulator. This consists derotation module, removal crosstalk, adjustment imbalance, equalization DPLL. constellation recovered symbol rate data still rotating this stage necessary de-rotate this prior equalization. After de-rotation symbol rate data applied adaptive equaliser remove transmission related distortions.
recovered symbols state decoder. user select puncture rate, lock thresholds even bypass decoder. decoder provides estimates which read microprocessor interface.
CS3810
Demodulator
TIMING CHARACTERISTICS
programming signals assumed static, i.e., they change during normal operation process. microprocessor interface signals have been described
previous section. timing diagrams other signals provided below, with reference clock output sample strobe signals.
Figure Input Data Timing
ZSTRB
cycles (256 symbols)
AGCP AGCOK
Figure Control Timing
BLLSTRB BLLIQ BLLQI
Figure Test Data Timing
PERFORMANCE
Figure demonstrates over error correction performance Concatenated correction system employed decoder (under AWGN conditions).
Performance
1.00E+00 1.00E-01 1.00E-02 1.00E-03 Concatenated coded data Uncoded Data 10.25 10.5 10.75
1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08
Eb/No (dB)
Figure Error Correction Performance demodulator. acquisition performance presented shown Table
Table Demodulator Acquisition Performance Metric
Carrier acquisition range Symbol acquisition range Carrier tracking range Typical acquisition time 600KHz 140ppm baud rate 600KHz
Performance
CS3810
Demodulator
PERFORMANCE DENSITY METRICS
PROGRAMMABLE LOGIC CORES DENSITY METRICS
ASIC prototyping projects requiring fast time-to-market programmable logic solution, Amphion programmable logic cores offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions. following performance density metrics been obtained when demodulator core implemented stand-alone design device specified below. should noted that function implemented different FPGA devices, combined with additional logic larger devices, then additional constraints might need applied achieve similar metrics. Note that metrics provided demodulation (Table channel decoding (Table separately.
Table CS3810 Decoder Programmable Logic Core Altera
DEVICE SILICON VENDOR AREA MEMORY REQUIREMENT ESBs CRITICAL PATH (TXUSRXLK) 56.82 (17.6 CRITICAL PATH (CLK74M) 75.76 (13.2
APEX20KC-7
Altera
10044
Table CS3810 Symbol Timing Recovery Programmable Logic Core Altera
DEVICE SILICON VENDOR AREA MEMORY REQUIREMENT ESBs CRITICAL PATH (CLK74M) 74.63 (13.4
APEX20KC-7
Altera
11276
Typical ASIC FPGA Design Flow (Conceptual)
Data Formats Supplied AMPHION
System-Level Code simulation
Accurate Model
Hardware Development
Simulation
Simulation Models
Logic Synthesis
Testbench
(VHDL Verilog)
Gate-level analysis (timing functional)
Netlists
(Verilog, VHDL, EDIF, .bd)
Physical Design
FPGA Programming Files
Figure Design Data Formats Supplied Amphion
CS3810
ABOUT AMPHION
Demodulator
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2002 Amphion Semiconductor Ltd. rights reserved. Amphion, Amphion logo,"Virtual Components Converging World", trademarks Amphion Semiconductor Ltd. others property their respective owners.
03/02 Publication DS3810 v1.0
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