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FlexQTMI Volt Synchronous First-In/First-Out Queue Memory Co


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FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Volt Synchronous First-In/First-Out Queue
Memory Configuration
8,192 4,096 2,048 1,024
Device
FQV251 FQV241 FQV231 FQV221
Memory Configuration
Device
FQV211 FQV201 FQV421 FQV321
Features:
Industry leading First-In/First-Out Queues 166MHz) Write cycle time 6.0ns independent Read cycle time (Data Setup time 2.0ns) Read cycle time 6.0ns independent Write cycle time (Data Setup time 4.0ns) 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Full, Empty, Almost Full, Almost Empty Half Full flag indicators Preset Almost Full PRAF Almost Empty PRAE offset values Programmable PRAF PRAE offset values Asynchronous output enable tri-state data output drivers Available packages: Plastic Lead Chip Carrier (PLCC) (0°C 70°C) Commercial operating temperature available cycle time 6.0ns above (-40°C 85°C) Industrial operating temperature available cycle time 7.5ns above
Product Description:
HBA's FlexQI offers industry leading FIFO queuing bandwidth Gbps) with wide range memory configurations (from 8,192 System designer full flexibility implementing deeper wider queues using depth width expansion features. Full Empty indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. These FlexQI devices have power consumption, hence minimizing system power requirements. addition, industry standard PLCC package offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Block Diagram Single Synchronous Queue 8,192 4,096 2,048 1,024
RESET
WRITE CLOCK (WCLK) WRITE ENABLE WEN1) WRITE ENABLE 2/LOAD (WEN2/ LOAD DATA FULL FULL ALMOST-FULL PRAF FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV421 FQV321
READ CLOCK (RCLK) READ ENABLE (REN1) READ ENABLE DATA EMPTY EMPTY ALMOST-EMPTY PRAE
OUTPUT ENABLE
Figure Single Device Configuration Signal Flow Diagram
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
WCLK WEN1 WEN2/ LOAD
LOAD Write Control Logic
EMPTY PRAE
Offset Register
Flag Logic Write Pointer
PRAF
FULL
Input Register
SRAM
Output Register
Output Buffer
Read Pointer
Read Control Logic
Reset
RCLK REN1
Figure Device Architecture
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Index
PRAF PRAE REN1 RCLK
WEN2/LOAD
EMPTY
PLCC (Order code: View Figure Device Pin-Out
FULL
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Symbol
Name
Reset Write Clock Write Enable
Input/Output
Input Input Input
Description
Reset required initialize Write Read pointers first position queue setting low. FULL PRAF will high; EMPTY PRAE will low. Writes data into queue during high transitions WCLK WEN1 activated. first only write enable control queue depending state WEN2/ LOAD during reset. During reset, setting WEN2/ LOAD high places queue into dual write enable mode. WEN1 must WEN2/ LOAD must high perform valid write this mode. During reset, setting WEN2/ LOAD places queue into single write enable/programmable flag mode. WEN1 must WEN2/ LOAD must high perform valid write this mode. this mode, WEN1 WEN2/ LOAD must program offset values PRAF PRAE wide input data bus. Reads data from queue during high transitions RCLK REN1 low. Reads data from queue during high transitions RCLK REN1 both low. Reads data from queue during high transitions RCLK REN1 both low. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). wide output data bus. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. Queue almost full when PRAF goes during high transition WCLK. Default (Full-7) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty+7) programmed offset values determine status PRAE 3.3V power supply. Ground.
WCLK
WEN1
WEN2/ LOAD
Write Enable Load
Input
30,31,32, 01,02,03, 04,05,06 24,23,22, 21,20,19, 18,17,16
RCLK
REN1
Data Inputs Read Clock Read Enable Read Enable Output Enable
Input Input Input Input Input
Data Output
Output
FULL
Full Flag
Output
EMPTY
Empty Flag Programmable Almost-Full Flag Programmable Almost-Empty Flag Power Ground
Output
PRAF
Output
PRAE
Output
Table Descriptions
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Symbol Rating
Terminal Voltage with respect Storage Temperature Output Current
Com'l Ind'l
-0.5 +125
Unit
VTERM TSTG IOUT
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
Table Absolute Maximum Ratings
FQV251, FQV241 FQV231, FQV221 FQV211, FQV201 FQV421, FQV321
Commercial Clock 6ns, 7.5ns, 10ns, 15ns Industrial Clock 7.5ns, 10ns, 15ns
Symbol Parameter Recommended Operating Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Supply Voltage Com'l/Ind'l Supply Voltage Input High Voltage Com'l/Ind'l Input Voltage Com'l/Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage, Active Power Supply Current Standby Current
ILI(1)
Power Consumption
Electrical Characteristics
ICC1(2,3) ICC2(4)
Table Specifications
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Capacitance 100MHz Ambient Temperature (25°C) Symbol Parameter Input Capacitance Output Capacitance
Measurement with 0.4<=VIN<=Vcc With output tri-stated High) Icc(1,2) measured with WCLK RCLK Design simulated, tested.
Conditions VIN= VOUT=
Max.
Unit
COUT(2,4)
NOTES:
Table Specifications (Continued)
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Commercial
FQV251-6 FQV241-6 FQV231-6 FQV221-6 FQV211-6 FQV201-6 FQV421-6 FQV321-6 FQV251-7.5 FQV241-7.5 FQV231-7.5 FQV221-7.5 FQV211-7.5 FQV201-7.5 FQV421-7.5 FQV321-7.5
Commercial Industrial
FQV251-10 FQV241-10 FQV231-10 FQV221-10 FQV211-10 FQV201-10 FQV421-10 FQV321-10 FQV251-15 FQV241-15 FQV231-15 FQV221-15 FQV211-15 FQV201-15 FQV421-15 FQV321-15
Symbol
tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAF tPRAE tSKEW1(2) tSKEW2
Parameter
Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z Output Enable Output Valid Output Enable Output High-Z(1) Write Clock Full Flag Read Clock Empty Flag Write Clock Almost-Full Flag Read Clock Almost-Empty Flag Skew time between Read Clock Write Clock Full Flag Empty Flag Skew time between Read Clock Write Clock PRAF PRAE
NOTES:
Design simulated, tested. Refer Table
Table Electrical Characteristics
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock 6ns, 7.5ns Output Load*, clock 10ns, 15ns 3.0V 1.5V 1.5V Refer Figure Refer Figure
Include scope capacitances Table Test Condition
Vcc/2
3.3V
D.U.T. 30pF*
Figure Test Load clock 6ns, 7.5ns
Figure Output Load clock 10ns, 15ns *Includes scope capacitances.
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Functions
Reset required initialize Write Read pointers first position queue setting low. FULL PRAF will high; EMPTY PRAE will low. data outputs will low. PRAF PRAE offset will their default values (Full-7 Empty+7 respectively). Writes data into queue during high transitions WCLK WEN1 activated. Synchronizes FULL PRAF flags. WCLK RCLK independent each other. single dual write enable control queue depending state WEN2/ LOAD during reset. perform write operation single write enable mode: WEN2/ LOAD during reset. WEN1 low, WEN2/ LOAD high during high transition WCLK. perform offset programming operation single write enable mode: WEN2/ LOAD during reset. WEN1 low, WEN2/ LOAD during high transition WCLK. perform write operation dual write enable mode: WEN2/ LOAD high during reset. WEN1 low, WEN2/ LOAD high during high transition WCLK. WEN2/ LOAD During reset, setting WEN2/ LOAD puts queue into single write enable/offset programming mode. Setting WEN2/ LOAD high places queue into dual write enable mode. wide input data Reads data from queue during high transitions RCLK REN1 activated. Synchronizes EMPTY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK REN1 both low. This also advances Read pointer queue. Reads data from queue during high transitions RCLK REN1 both low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY
WCLK
WEN1
RCLK
REN1
REN2
FULL
EMPTY
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Functions (Continued)
PRAF
Queue almost full when PRAF goes during high transition WCLK. Default (Full7) programmed offset values determine status PRAF Refer Table behavior PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty+7) programmed offset values determine status PRAE Refer Table behavior PRAE
PRAE
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV421 FQV321 Selection Sequence
Write offset registers: Empty offset (Low Byte) Empty offset (High Byte) Full offset (Low Byte) Full offset (High Byte)
PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte
WEN2/ LOAD
WEN1
WCLK
Operation
Write Memory
Operation
Figure Write Offset Register
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV421 FQV321 Selection Sequence
Read from offset registers: Empty offset (Low Byte) Empty offset (High Byte) Full offset (Low Byte) Full offset (High Byte)
PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte
WEN2/ LOAD
REN1 REN2
RCLK
Operation
Write Memory
Operation
Figure Read Offset Register
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Device
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV421 FQV321 D/Q7-0 D/Q4-0 D/Q7-0 D/Q3-0 D/Q7-0 D/Q2-0 D/Q7-0 D/Q1-0 D/Q7-0 D/Q0 D/Q7-0 Don't Care D/Q6-0 Don't Care D/Q5-0 Don't Care Default Value 007H
PRAE Programming (bits)
Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte D/Q7-0 D/Q4-0 D/Q7-0 D/Q3-0 D/Q7-0 D/Q2-0 D/Q9-0 D/Q1-0 D/Q7-0 D/Q0
PRAF Programming (bits)
Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
D/Q7-0 Don't Care D/Q6-0 Don't Care D/Q5-0 Don't Care Default Value 007H
Table Parallel Offset Register Data Mapping Table Default Values
Device
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV421 FQV321
Standard Mode
8,192 4,096 2,048 1,024
Table Maximum Depth Queue
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
FQV251 8,912 Data Width
Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
FQV241 4,096
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
FQV231 2,048 Data Width
Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
FQV221 1,024
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
FQV211
Data Width
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
FQV201
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
FQV421
Data Width Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
FQV321
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
Bits Offset Registers bits FQV251 bits FQV241 bits FQV231 bits FQV221 bits FQV211 bits FQV201 bits FQV421 bits FQV321 Note: Don't Care applies unused bits both High Byte Byte
Figure Parallel Offset Write/Read Cycles Diagram
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
FQV251
y(1) (y+1) [8,192-(x+1)] (8,192-x(2))to 8,191 8,192
FULL
PRAF
PRAE
EMPTY
EMPTY
FQV241
FULL
PRAF
PRAE
EMPTY
(y+1) [4,096-(x+1)] (4,096-x 4,095 4,096
FQV231
FULL
PRAF
PRAE
EMPTY
(y+1) [2,048-(x+1)] (2,048-x(2))to 2,047 2,048
FQV221
y(1) (y+1) [1,024-(x+1)] (1,024-x 1,023 1,024
FULL
PRAF
PRAE
EMPTY
FQV211
FULL
PRAF
PRAE
(y+1) [512-(x+1)] (512-x
Table Status Flags
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
FQV201
FULL
PRAF
PRAE
EMPTY
EMPTY
(y+1) [256-(x+1)] (256-x(2))to
FQV421
y(1) (y+1) [128-(x+1)] (128-x
FULL
PRAF
PRAE
EMPTY
FQV321
FULL
PRAF
PRAE
(y+1) [64-(x+1)] (64-x
NOTES:
PRAE offset default value). PRAF offset default value).
Table Status Flags (Continued)
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Timing Diagrams
tRST
tRSTS tRSTR
REN1
tRSTS tRSTR
WEN1
tRSTS tRSTR
WEN2/ LOAD
tRSTF
EMPTY PRAE
tRSTF
FULL PRAF
tRSTF
1(2)
NOTES:
Holding WEN2/ LOAD high during reset will make second Write Enable pin. Holding WEN2/ LOAD during reset will make Load Enable programmable flag offset registers. After reset, outputs will high-impedance clocks (RCLK, WCLK) free-running during reset.
Diagram Reset Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
tWCLK
tWCLKH
tWCLKL
WCLK
Valid Data tENS tENH
WEN1
tENS tENH
Operation
WEN2/LOAD
tFULL tFULL
Operation
FULL
tSKEW1(1)
RCLK
REN1
NOTES:
tSKEW1 minimum time between rising RCLK edge rising WCLK edge FULL change during current clock cycle. time between rising edge RCLK rising WCLK less than tSKEW1, FULL change state until next WCLK edge.
Diagram Write Cycle Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
tRCLK tRCLKH tRCLKL
RCLK
tENS tENH
REN1
tEMPTY tEMPTY
EMPTY
Valid Data tOLZ tOHZ
tSKEW1(1)
WCLK
WEN1
WEN2/LOAD
NOTES: tSKEW1 minimum time between rising WCLK edge rising RCLK edge EMPTY change during current clock cycle. time between rising edge RCLK rising edge WCLK less than SKEW1, then EMPTY change state until next RCLK edge. Diagram Read Cycle Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
WCLK
First Valid Write tENS
WEN1
tENS
WEN2/ LOAD
tSKEW1
tFRL
RCLK
tEMPTY
EMPTY
tENS
REN1
tA(1) tOLZ
NOTES:
tRFL First Read Latency. When tSKEW1 greater than equal minimum specification, tRFL tRCLK tSKEW1. When tSKEW1 less than minimum specification, tRFL 2*tRCLK tSKEW1 tRCLK tSKEW1 Latency Timings apply only Empty Boundary EMPTY Low).
Diagram First Data Word Latency Timing
Speed Grade
tSKEW1 tSKEW1
First Word Latency 66MHz
tSKEW1 tSKEW1
tSKEW1 tSKEW1
tSKEW1 tSKEW1
tFRL
tRCLK tSKEW1 2*tRCLK tSKEW1
tRCLK tSKEW1 Table Empty Boundary Latency Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Write Write Write
WCLK
tSKEW1 tSKEW1
tFULL tFULL tFULL
FULL
tENS tENH tENS
WEN1
tENS tENH tENS
WEN2/LOAD
RCLK
tENS tENH tENS tENH
REN1
Output Register Data Data Read Next Data Read
NOTES:
Only Write Enable inputs, WEN1 WEN2, needs inactive inhibit writes Queue.
Diagram Full Flag Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
WCLK
tENS
tENH tENS
tENH
WEN1
tENS tENH tENS tENH
WEN2/LOAD
tFRL(1) tSKEW1 tSKEW1 tFRL(1)
RCLK
tEMPTY tEMPTY tEMPTY
EMPTY
REN1
Output Register Data
NOTES:
When tSKEW1 greater than equal minimum specification, tRFL tRCLK tSKEW1. When tskew1 less than minimum specification, tRFL maximum 2*tRCLK tSKEW1 tRCLK tSKEW1 Latency Timings apply only Empty Boundary EMPTY Low)
Refer Table
Diagram Empty Flag Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
tWCLKH
tWCLKL
WCLK
tENS tENH
WEN1
tENS tENH
WEN2/ LOAD
tPRAF
PRAF
Full words Queue
Full words Queue tSKEW2
tPRAF
RCLK
tENS tENH
REN1
NOTES:
PRAF offset. words queue FQV321; words queue FQV421; words queue FQV201; words FQV211; 1,024 words FQV221; 2,018 words FQV231; 4,096 words FQV241; 8,192 words FQV251. tSKEW2 minimum time between rising RCLK edge rising WCLK edge PRAF change during that clock cycle. time between rising edge RCLK rising edge WCLK less than tSKEW2, then PRAF change state until next WCLK rising edge. write performed this rising edge write clock, there will Full (x+1) words queue when PRAF goes low.
Diagram Programmable Full Flag Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
tWCLKH tWCLKL
WCLK
tENS tENH
WEN1
tENS tENH
WEN2/ LOAD PRAE
words Queue tSKEW2 tPRAE words Queue tPRAE
RCLK
tENS tENH
REN1
NOTES:
PRAE offset tSKEW2 minimum time between rising WCLK edge rising RCLK edge PRAE change during that clock cycle. time between rising edge RCLK rising edge WCLK less than tskew2, then PRAE change state until next RCLK rising edge. read performed this rising edge read clock, there will Empty (y+1) words queue when PRAF goes low.
Diagram Programmable Empty Flag Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
tWCLK tWCLKH tWCLKL
WCLK
tENS tENH
LOAD
tENS
WEN1
PRAE offset
(Low Byte)
PRAE offset
(High Byte)
PRAF offset
(Low Byte)
PRAF offset
(High Byte)
Diagram Write Offset Registers Timing
tRCLK tRCLKH tRCLKL
RCLK
tENS tENH
LOAD
tENS
REN1
Output Register Data
PRAE offset
(Low Byte)
PRAE offset
(High Byte)
PRAF offset
(Low Byte)
PRAF offset
(High Byte)
Diagram Read Offset Registers Timing
March 2001
Preliminary
Page
FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV321
FlexQTMI
Order Information:
Device Family Device Type XXXX V251 (8,192 V241 (4,096 V231 (2,048 V221 (1,024 V211 (512 V201 (256 V421 (128 V321 *Speed available only Commercial temp (0°C 70°C) **Package Plastic Lead Chip Carrier (PLCC) Example: FQV241L6J FQV231L10JI 6ns, Commercial temp) 10ns, Industrial temp) Power Speed (ns) Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
High Bandwidth Access, Inc. 2107 North First Street, Suite Jose, 95131, Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com sales@hba.com
March 2001
Preliminary
Page

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