225A833 Other Read/Write Cycle Times (-55 125°C) Number Pending A

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225A833 Other Read/Write Cycle Times (-55 125°C) Number Pending A

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128K Radiation Hardened Static MCM-
225A833
Other Read/Write Cycle Times (-55 125°C) Number Pending Asynchronous Operation CMOS Compatible Single Power Supply Operating Power Packaging Options 64-Lead Dual Flat Pack (1.000" 0.900")
Radiation Fabricated with Bulk CMOS Process Total Dose Hardness through 1x106 rad(Si) Neutron Hardness through 1x1014 N/cm2 Dynamic Static Transient Upset Hardness through 1x109 rad(Si)/s Soft Error Rate 1x10-11 Upsets/Bit-Day Latchup Free
General Description
128K radiation hardened static composed four 128K SRAM memory assembled single, doublesided ceramic substrate. Each high performance 131,072 word 8-bit static random access memory with industrystandard functionality. fabricated with SYSTEMS' radiation hardened technology designed systems operating radiation environments. operates over full military temperature range requires single power supply. available with CMOS compatible I/O. Power consumption typically less than mW/MHz operation, less than power disabled mode. read operation fully asynchronous, with associated typical access time nanoseconds. SYSTEMS' enhanced bulk CMOS technology radiation hardened through advanced proprietary design, layout, process hardening techniques.
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Functional Diagram
Top/Bottom Decoder
Block Address Decoder
Side/Block
(((256
Address Decoder
Memory Cell Array
Word Input/Output
Column Address Decoder
DQ0-DQ31
Note:
A4-A8
package leads common with bottom SRAM devices except through
Signal Definitions
0-16
Address input pins that select particular eight-bit word within memory array. Bi-directional data pins that serve data outputs during read operation data inputs during write operation. Negative chip select, when level, allows normal read write operation. When high level, through forces SRAM precharge condition, holds data output drivers high impedance state disables data input buffers only. this signal used, must connected GND.
0-31
Negative write enable, when level, activates write operation holds data output drivers high impedance state. When high level, allows normal read operation. Negative output enable, when high level holds data output drivers high impedance state. When level, data output driver state defined through this signal used must connected GND.
Truth Table
Inputs(1),(2)
Notes:
Power
Mode
don't care inputs VIH. Active Active Standby When high, high-Z. dissipate minimum amount standby power when standby mode: VDD. other input levels float.
Write Read Standby(3)
High
High
Data-In Data-Out High-Z
Absolute Maximum Ratings
Applied Conditions(1) Minimum Maximum
Storage Temperature Range (Ambient) Operating Temperature Range (Tcase) Positive Supply Voltage Input Voltage Output Voltage Power Dissipation Thermal Resistance, Junction-to-Case (JC) Lead Temperature (Soldering sec) Electrostatic Discharge Sensitivity
-70°C -55°C -0.5 -0.5 -0.5
+150°C +125°C +7.0 VDD+ VDD+
3°C/W +230°C (Class
Notes:
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. voltages with reference module ground leads. Maximum applied voltage shall exceed +7.0 Guaranteed design; tested. Class defined MIL-STD-883, Method 3015. Typical power dissipation recommended that part thermally bonded board.
Recommended Operating Conditions
Symbol Parameters(1) Minimum Maximum Units
Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" Input Logic "High"
Note:
+4.5 -0.3 +3.5
+5.5 +125 +1.5
Volt Volt Celsius Volt Volt
1)All voltages referenced GND.
Power Sequencing
Power shall applied device only following sequences prevent damage excessive currents: Power-Up Sequence: GND, VDD, Inputs Power-Down Sequence: Inputs, VDD,
Electrical Characteristics
Group Sub-Groups Device Type Limits Minimum Maximum
Test
Symbol
Test Conditions(1)
Units
Supply Current (Cycling Selected) Supply Current (Cycling De-Selected) Supply Current (Standby) Data Retention Current High Level Output Voltage Level Output Voltage Data Retention Voltage High Level Input Voltage Level Input Voltage Input Leakage Output Leakage Cout
IDD1 IDD2 IDD3 IILK IOLK
FMAX 1/tAVAV(min) Output Load FMAX 1/tAVAV(min) VDD= IOH= -200 IOL= VDD= CMOS CMOS VOUT
0.05
Notes:
Typical operating conditions: 25°C, pre-radiation. -55°C Tcase +125°C; unless otherwise specified. Design Verified Characterization worst case timing sequence tWLQZ tDVWH tWHWL tAVAV (write cycle time)
Output Load Circuit
2.8V
Read Cycle Timing Characteristics(1)
Minimum Maximum Minimum Maximum Maximum Maximum Minimum Minimum Minimum Maximum Maximum
Test Read Cycle Time Address Access Time Chip Select Access Time Output Enable Access Time Chip Select Output Active Output Enable Output Active Output Hold After Address Change Chip Select Output Disable Output Enable Output Disable
Symbol tAVAV tAVQV tSLQV tGLQV tSLQX tGLQX tAXQX tSHQZ tGHQZ
Device Type
Limits
Units
Note: 1)Test conditions: input switching levels VIL/VIH V/VDD -0.5 (CMOS), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading derate access times 0.02 ns/pF (typical). Tcase +125°C; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
tAXQX
tSLQX
tSHQZ tGLQV
tGLQX
Data
tGHQZ
Valid Data
High Impedance
Write Cycle Timing Characteristics(1)
Minimum Maximum
Test
Symbol
Device Type
Limits
Units
Write Cycle Time Write Pulse Width Chip Select Write Data Setup Write Address Setup Write Data Hold After Write Address Setup Start Write Address Hold After Write Write Enable Output Disable Output Active After Write Write Disable Pulse Width
tAVAV tWLWH tSLWH tDVWH tAVWH tWHDX tAVWL tWHAX tWLQZ tWHQX tWHWL
Minimum Minimum Minimum Minimum Minimum Minimum Minimum Minimum Maximum Minimum Minimum
Note:
Test conditions: input switching levels VIL/VIH V/VDD (CMOS), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading -55°C Tcase +125°C; unless otherwise specified. Cycle time individual die.
Write Cycle Timing Diagram
tAVAV
Address
Valid Address tAVWH tSLWH tWHAX
tWLWH
tAVWL
Data
tWLQZ High Impedance tDVWH
tWHWL tWHQX
High Impedance
tWHDX
Data
High Impedance
Valid Data
High Impedance
Dynamic Electrical Characteristics
Read Cycle asynchronous operation, allowing read cycle controlled address, chip select (S1-S4) (refer Read Cycle Timing diagram). perform valid read operation, both chip select output enable must write enable must high. output drivers controlled independently signal. Consecutive read cycles executed with S1-S4 held continuously low, toggling addresses. address-activated read cycle, S1-S4 must valid prior coincident with activating address edge transition(s). amount toggling skew between address edge transitions permissible; however, data outputs will become valid tAVQV time following latest occurring address edge transition. minimum address activated read cycle time tAVAV When operated minimum address-activated read cycle time, data outputs will remain valid until tAXQX time following next sequential address transition. control read cycle with S1-S4, addresses must valid prior coincident with enabling S1-S4 edge transition. Address transitions occur later than specified setup times S1-S4; however, valid data access time will delayed. address edge transition, that occurs during time when S1-S4 low, will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tSHQZ time following disabling S1-S4 edge transition.
Write Cycle write operation synchronous with respect address bits, control governed write enable chip select (S1-S4) edge transitions (refer Write Cycle Timing diagrams). perform write operation, both S1-S4 must low. Consecutive write cycles performed with S1-S4 held continuously low. least control signals must transition opposite state between consecutive write operations. write mode controlled different control signals: S1-S4. Both modes control similar except S1-S4 controlled modes actually disables during write recovery pulse. controlled mode shown table diagram previous page simplicity. However, each mode control provides same write cycle timing characteristics. Thus, some parameter names referenced below shown write cycle table diagram, indicate which control control switches high low. write data into RAM, S1-S4 must held least tWLWH /tSLSH time. amount edge skew between signals tolerated control signals initiate terminate write operation. consecutive write operations, write pulses must separated minimum specified tWHWL /tSLSH time. Address inputs must valid least tAVWL /tAVSL time before enabling W/S1-S4 edge transition, must remain valid during entire write time. valid data overlap write pulse width time tDVWH /tDVSH, address valid write time tAVWH /tAVSH also must provided during write operation. Hold times address inputs data inputs with respect disabling W/S1-S4 edge transition must minimum tWHAX /tSHAX time tWHDX /tSHDX time, respectively. minimum write cycle time tAVAV.
Radiation Characteristics
Total Ionizing Radiation Dose SRAM will meet stated functional electrical specifications over entire operating temperature range after total ionizing radiation dose 1x106 rad(Si). electrical timing performance parameters will remain within specifications after rebound 125°C extrapolated years operation. Total dose hardness assured wafer level testing process monitor transistors product using X-ray Co60 radiation sources. Transistor gate threshold shift correlations have been made between X-rays applied dose rate 1x105 rad(Si)/min 25°C gamma rays (Cobalt source) ensure that wafer level X-ray testing consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation SRAM capable writing, reading, retaining stored data during after exposure transient ionizing radiation pulse duration 1x109 rad(Si)/s, when applied under recommended operating conditions. ensure validity specified performance parameters before, during, after radiation (timing degradation during transient pulse radiation 10%), stiffening capacitance placed package between package (chip) with inductance between package (chip) stiffening capacitance kept minimum. there operatethrough valid stored data requirements, typical de-coupling capacitors should mounted circuit board close possible each device. SRAM will meet functional electrical specification after exposure radiation pulse duration 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that current conducted during pulse inputs, outputs, power supply significantly exceed normal operating levels. application design must accommodate these effects. Neutron Radiation SRAM will meet functional timing specification after total neutron fluence 1x1014 cm-2 applied under recommended operating storage conditions. This assumes equivalent neutron energy MeV. Soft Error Rate SRAM soft error rate (SER) performance <1x10-11 upsets/bit-day, under recommended operating conditions. This hardness level defined Adams worst case cosmic environment. Latchup SRAM will latch above radiation exposure conditions when applied under recommended operating conditions.
Radiation Hardness Ratings (1),(2)
Symbol
Characteristics
Conditions
Minimum
Maximum
Units
SEU1 SEU2
Total Dose Single Event Upset(3) Single Event Upset
MIL-STD-883, 1019.5 Condition -55°C Tcase 80°C -55°C Tcase 125°C -55°C Tcase 125°C
rad(Si) Upsets/Bit-Day Upsets/Bit-Day Immune
Single Event Induced Latchup
Notes: Measured room temperature unless otherwise stated. Verification test approved test plan. Device electrical characteristics guaranteed post irradiation levels 25°C. worst case particle environment, geosynchronous orbit, 0.025'' aluminum shielding. Specification using CREME code upset rate calculation method with thickness. Immune MeV/mg/cm
Tester Timing Characteristics
CMOS Configuration
Input Levels*
VDD-
Output Sense Levels
VDD- High
High
High
*Input rise fall times
Radiation Hardness Assurance
SYSTEMS provides superior quality level radiation hardness assurance products. excellent product quality sustained qualified operation which requires process control with statistical process control, radiation hardness assurance procedures rigid computer controlled manufacturing operation monitoring tracking system. SYSTEMS technology built with resistance radiation effects. product designed exhibit fails/bit-day worst case geosynchronous orbit under worst case operating conditions. Total dose hardness assured irradiating test structures every total dose exposure with Cobalt testing performed quarterly lots assure product meeting radiation hardness requirements.
Reliability
SYSTEMS' reliability starts with overall product assurance system that utilizes quality system involving employees including operators, process engineers product assurance personnel. extensive wafer acceptance methodology, using in-line electrical data well physical data, assures product quality prior assembly. continuous reliability monitoring program evaluates every wafer level, utilizing test structures well product testing. Test structures placed every wafer, allowing correlation checks within-wafer, wafer-to-wafer, from lot-to-lot. Reliability attributes CMOS process characterized testing both irradiated non-irradiated test structures. evaluations allow design model process changes incorporated specific failure mechanisms, i.e., carriers, electromigration, time dependent dielectric breakdown. These enhancements operation create more reliable product. process reliability further enhanced accelerated dynamic life tests both irradiated non-irradiated test structures. Screening testing procedures from customer followed qualify product. final periodic verification quality reliability product validated (Technology Conformance Inspection).
Screening Levels
SYSTEMS screen levels meet full compliant space applications. limited performance evaluation situations, SYSTEMS offers engineering screen level.
Standard Screening Procedure
Flow Wafer Acceptance Serialization Flip Chip Pull Destructive Bond Pull Burn-In Electrical Test Dynamic Burn-In Electrical Test Internal Visual Fine Gross Leak Temperature Cycle Mechanical Shock PIND Radiography Electrical Test Dynamic Burn-In Final Electrical Test Fine Gross Leak External Visual Level Sample Sample Comments Alternate Method Used Traceability
MIL-STD-883, 2010, 2017 Bubble Test Only
Meets Group MIL-PRF-38534, Based MIL-STD-883, 2009
Burn-In Circuit
Stress Methodology
There methods burn-in defined. "Static" burn-in, possible addresses written with logic half burn-in duration logic remaining half. "Dynamic" burn-in, possible addresses written with alternating high data. pins specified static dynamic burn-in lists driven through individual series resistors (1.6K ±10%). burn-in circuit diagram shown right. Voltage Levels Vin(0): level programmed signals High level programmed signals (-0% +10%) pins tied this level Float pins tied this level (±10%) 1.6K (±10%)
DQ31
128K SRAM
Listing dynamic burn-in listing shown right. square wave, MHz.
Input
Signal F/16 F/32
Input
Signal F/64 F/128 F/256 F/512 F/1024
Input
Signal F/2048 F/4096 F/8192 F/16384 F/32768
Input
Signal F/65536 F/131072 F/262144 F/524288 F/1048576
Packaging
128K SRAM offered custom 64-lead dual packages constructed multilayer ceramic (AI2O3) feature internal power ground planes. Optional capacitors mounted package maximize supply noise decoupling increase board packing density. These capacitors attach directly internal package power ground planes. This design minimizes resistance inductance bond wire package, both which critical transient radiation environment. pins must connected either VDD, active driver prevent charge build radiation environment. connect.)
64-Lead Dual Flat Pack Pinout
View
40-Lead Flat Pack
Lead Lead
(Width) (Pitch)
A=1.760 B=1.000 .010 C=.900 .010 D=.775 E=.008 .002 F=.025
G=.135 H=.270 .012 J=.048 K=.080 L=.025 M=.035
Notes: Part mark device specification.
Lead Lead
Dimensions inches. Unless otherwise specified, tolerances .005".
"QML" required device specification.
Ordering Information
128K CMOS Memory Device Number 255A833
Package Designation
Speed Designation
Screen Designation
1=64-Lead
1=Class 3=Engineering 5=Class 7=Customer Specific
SYSTEMS reserves right make changes products herein improve reliability, function design. SYSTEMS does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others.
Cleared Public Domain Release ©2001 SYSTEMS, Rights Reserved
SYSTEMS 9001, AS9000, 14001, Level Company 9300 Wellington Road, Manassas, 20110-4122 866-530-8104 0037_128K_32_SRAM.ppt
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122

225A833 Other Read/Write Cycle Times (-55 125°C) Number Pending A

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