Supports eight 10/100 Mbits/s Ethernet ports with integrated 10/100Bas
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AL216 Preliminary Port 10/100 Ethernet Switch with Integrated
Supports eight 10/100 Mbits/s Ethernet ports with integrated 10/100Base-T/-TX/FX Transceivers Scalable ports using four AL216 devices. Non-blocking ports Scalable design stackable switch implementation Capable trunking Mbits/s link Built-in storage media access control (MAC) addresses expandable Designed utilize low-cost SGRAM SDRAM RoXexpansion link supports Gbits/s throughput Automatic source address learning Serial EEPROM interface low-cost system configuration Secure mode traffic filtering Broadcast storm control Port monitoring support IEEE 802.3x flow control full-duplex operation. Optional backpressure flow control support half-duplex operation Supports store-and-forward mode switching VLAN support RMON SNMP support with external management (MIB) device 388-pin package
AL216 highly integrated, scalable eight-port 10/100 switch/MAC/PHY Ethernet standard product. This device supports both fiber ports. targeted high performance low-cost desktop workgroup switches. AL216 provides extremely low-power dissipation, operates from single 3.3V power supply.
Buffer Manager
TP/FIBER TP/FIBER TP/FIBER TP/FIBER TP/FIBER TP/FIBER TP/FIBER TP/FIBER
10/100 10/100 10/100 10/100 10/100 10/100 10/100 10/100
10/100 10/100 10/100 10/100 10/100 10/100 10/100 10/100 High Speed Switch Fabric
Switch Controller
Address Control
Expansion Interface
Address Table
Address Table Expansion
EEPROM Interface Switch Controller
Figure
System Block Diagram
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AL216 Preliminary
This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL216 Overview Descriptions. Functional Description. RoXInterface. Data Reception. 3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.3.3 Illegal Frame Length Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission Frame Generation.
Frame Forwarding.
Half-Duplex Mode Operation Secure Mode Operation Address Learning 3.6.1 Address Aging. Link Aggregation/Trunking Load Balancing 3.8.1 3.8.2 3.8.3 Trunk Port Assignment Port-Based Trunk Loading Based Load Balancing Setup
3.10
Spanning Tree Support. Flow Control Half Duplex Flow Control (Backpressure) Full-Duplex Flow Control (802.3x)
3.10.1 3.10.2 3.11 3.12 3.13 3.14 3.15 3.16
Queue Management VLAN Support. Uplink Port. Port Monitoring. Physical Layer Transceivers. Management.
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AL216 Preliminary
3.16.1 3.17 3.17.1 3.17.2 3.17.3
Management Register Access Parallel Mode Serial Mode Bicolor Mode.
Operational Modes
Mode Configurations Single Configuration. Dual Configuration
SGRAM SDRAM Interface SRAM Interface EEPROM Interface 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 System Initialization Write Cycle Timing. Read Cycle Timing Reprogramming EEPROM Interface EEPROM
Register Descriptions. Management Registers.
Timing Requirements. Absolute Maximum Ratings Electrical Characteristics Package Outline Diagram Appendix (VLAN Worksheet) Appendix (Port Trunk Port Assignment Worksheet)
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AL216 Preliminary
AL216 Overview
AL216 8-port 10/100 Mbit/s dual-speed Ethernet switch with integrated 10/100 Mbit/s transceivers. Each port supports both Mbit/s Mbit/s data rate. operation mode auto-negotiated PHY. ports full-duplex capable. low-cost scalable solution 32-ports achieved through low-cost buffer memory architecture. RoXinterface Gbit/s interface (4.8 Gbit/s full-duplex). interface support four switch chips. Various system configurations achieved using family components. maximum port configuration will either 32-port Mbit/s ports 24-port Mbit/s plus Gigabit Ethernet ports. interface also supports external management device. SNMP RMON supported through this external management device. addition, AL216 also supports VLAN workgroup segment switching applications multiple link aggregation trunks. trunking applications, chip provides optional load balancing schemes, explicit dynamic. With trunking, possible group four full-duplex links together form single Mbit/s link. During transmission, data obtained from buffer memory routed destination port. event collision during half-duplex operation, control will back retransmit accordance IEEE 802.3 specification. Data received from interface stored external memory buffer. AL216 utilizes cost-effective SGRAM SDRAM provide 8-Mbit 16-Mbit buffer memory. AL216 provides flow control methods. half-duplex operation, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive buffer full. sending station will transmit until line clear. full-duplex mode, AL216 utilizes IEEE 802.3x PAUSE frames flow control mechanism. ports support multiple addresses. AL216 supports addresses internally. These addresses shared among eight ports. Additional SRAM added provide addresses support. initialization configuration switch programmed external EEPROM. unmanaged switch design, there need CPU. Field reconfiguration achieved using parallel interface reprogram EEPROM. Refer Figure managed switch applications, AL216 supports network management through network management option, AL300A. When management option enabled, network statistics each port gathered sent across ring. management information base chip will collect store data network management agent. Access statistic counters provided interface device. AL216 also supports port-based VLAN. VLAN register used configure destination ports multicast broadcast frames. device also provides levels security intrusion protection. Security implemented per-port basis.
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AL216 Preliminary
AL216 operates only store forward mode. entire frame checked errors. Frames with errors automatically filtered will forwarded destination port. Other features include port monitoring broadcast storm throttling. Diagram
Figure
Diagram (Top View)
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RODH ROCTL3 ROCTL7 ROD2 ROD6 ROD10 ROD12 ROD16 ROD20 ROD23 ROD27 ROD31 VDDA FOSD6 SPEEDLED FDUPLED3 FDUPLED6 LINKLED2 LINKLED6 FOSD2 SPEEDLED FDUPLED1 FDUPLED5 FDUPLED7 LINKLED3 LINKLED7 FOSD1
Figure
VDDA
ROCTL1 ROCTL5 ROD0 ROD4 ROD8 ROD11 ROD14 ROD18 ROD22 ROD25 ROD29 SPEEDLED ROD26 ROD30 SPEEDLED FDUPLED2 LINKLED1 LINKLED5 FOSD5 SPEEDLED FDUPLED0 FDUPLED4 LINKLED0 LINKLED4 FOSD3 FOSD7 FOSD4 SPEEDLED SPEEDLED
ROCTL0 ROCTL2 ROCTL6 ROD1 ROD5 ROD9 ROD13 ROD17 ROD21 ROD24
VDDPLL
FOSD0
ROCTLH ROCTL4 ROD3 ROD7 ROD15 ROD19 ROD28 LEDSELEC SPEEDLED
SYSCLK
BYPASSPL
ETD13 ETD14
ETGWN
VSSPLL
TPIN7
TPIP7
ETD9
ETD12
ETD15
VDDA
TPIN6
TPIP6
AL216 Pinout Information
VDDA TPIN5 ETD5 ETD10 VDDA TPIN4 ETD1 VDDA TPIN3 ETA13 ETD3 VDDA ETA9 ETA11 VDDA TPIN2 ETA5 TPIN1 ETA1 ETA3 VDDA ETADVN TPIN0 PBD31 ETADSCN VDDA VDDM PBD28 PBD26 REXTBS PBD24 VDDA PBD20 PBD22 REXT10 REXT100 TPOP7 PBD16 TPOP6 PBD12 PBD14 TPOP5
ETD8
ETD11
TPIP5
ETD6
ETD7
TPIP4
ETD2
ETD4
TPIP3
ETA15
ETD0
ETA12
ETA14
TPIP2
ETA8
ETA10
TPIP1
ETA6
ETA7
ETA2
ETA4
TPIP0
ETOEB
ETA0
VDDA
PBD30
ETCLK1
RMIICLK
PBD27
PBD29
VDDA
PBD23
PDB25
TPON7
PBD19
PBD21
TPON6
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PBD8 PBD10 PBD5 PBD1 PBD3 PBA9_10 PBA1 PBWEN RICTL1 RID1 RID9 RID13 RID22 RID25 EECLK PBA4 PBA0 CLK250 RICTLH RICTL3 RICTL7 RID3 RID7 RID11 RID15 RID17 RID20 RID23 RID27 RID31 RESETN PBA7 PBA5 PBA2 PBCASN RICLK RICTL0 RICTL4 RICTL6 RID2 RID5 RID8 RID12 RID16 RID19 REF_ACS RID26 RID29 EPBYPASS PBA6 PBA3 PBRASN PBCSN RIDH RICTL2 RICTL5 RID0 RID4 RID6 RID10 RID14 RID18 RID21 RID24 RID28 RID30 EEDIO
PBD17
PBD18
TPON5
PBD13
PBD15
TPOP4
TPON4
PBD9
PBD11
TPOP3
TPON3
PBD6
PBD7
TPOP2
TPON2
PBD2
PBD4
DEVID1
TPOP1
TPON1
PBA8_9
PBD0
TESTMODE
TRI_ALLN
TMDC
TPOP0
TPON0
DEVID0
TMDIO
PBANC_8
SSOUT
TRST
SCANMOD
SEL_MDIO
AL216 Preliminary
AL216 Preliminary
Descriptions
Physical Interface AL216 physical interface supports 10Base-T, 100-Base-TX 100Base-FX which compliant IEEE 802.3u.
Table 10/100 Mbit/s Twisted-Pair Fiber Interface Pins (Port 0-Port
PINS D26, E26, F26, G26, H26, L26, D25, E25, F25, G25, H25, K25, L25, U25, V25, W25, Y25, AA25, AB25, AC25, AD25 SIGNAL TPIP+/ FOIN+[7:0] TYPE DESCRIPTION Receive Data. Positive differential received Mbaud MLT3, Mbaud Manchester data from magnetics. Fiber-Optic Data Input. Positive differential received Mbaud pseudo-ECL data from fiber transceiver. TPIN-/ FOIN-[7:0] Receive Data. Negative differential received Mbaud MLT3 Mbaud Manchester data from magnetics. Fiber-Optic Data Input. Negative differential received Mbaud pseudo-ECL data from fiber transceiver. TPOP+/ FOOUT+[7: Transmit Data. Positive differential transmit Mbaud MLT3 Mbaud Manchester data magnetics. Fiber-Optic Data Output. Positive differential transmit Mbaud pseudo-ECL compatible data fiber transceiver. Transmit Data. Negative differential transmit Mbaud MLT3 Mbaud Manchester data magnetics. Fiber-Optic Data Output. Negative differential transmit Mbaud pseudo-ECL compatible data fiber transceiver. Fiber-Optic Signal Detect. Pseudo-ECL input signal which indicates whether fiber-optic receive pairs (FOIN±) receiving valid signal levels. These inputs ignored when fiber mode should grounded.
U26, V26, W26, Y26, AA26, AB26, AC26, AD26
TPON-/ FOOUT- [7:0]
B15, A16, C17, B16, C23, B23, A24,
FOSD[7:0]
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AL216 Preliminary
Table Configuration Pins
PINS SIGNAL LEDSELECT TYPE DESCRIPTION Select when Mode. This selects either activity link LEDs, when driven (default) selects speed duplex LEDs when driven high. Link LED. This indicates good link status ports [7:0]. active-low output. Single mode. Link [7:3] dual mode. Table Mode Enable. power-up reset, when pulled high through resistor, these pins will enable mode (10Base-T 100Base-TX disabled) ports [7:0]. When pulled low, will enable 10Base-T 100Base-TX modes (100Base-FX mode disabled). These pins ORed with register [29.0]. These pins have internal pull-down resistors. default value disable mode. SPEEDLED7 Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. single/dual mode, Table Table FULL_DUP Full Duplex. power-up, this used select either full- half-duplex operation eight channels. This same function register This ignored when auto-negotiation enabled. When this pulled through resistor power-up reset, indicates full duplex. This internal pull-down resistor default full-duplex normal operation. SPEEDLED6 Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. single/dual mode, Table Table
A23, B22, D22, C22, A22, B21, D20,
LINKLED[7:0]
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS
SIGNAL SPEED
TYPE
DESCRIPTION Speed. power-up reset, this signal used select operating speed same function register this signal pulled with resistor, will enable Mbit/s operation. this signal pulled high with resistor, will enable Mbit/s operation. This signal ignored when auto-negotiation enabled. This signal register ANDed. This internal pull-down, default 100TX mode, when auto-negotiation enabled.
SPEEDLED5
Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. single/dual mode, Table Table
STRETCH_LED
Stretch Mode. power-up reset, when pulled high through resistor, this enables stretching. When high, activity output stretched minimum maximum, unless BLINK_LED_MODE high, which case stretching 2.5s high, 2.5s low. This ORed with register This internal pull-down resistor. Default stretch mode disabled.
SPEEDLED4
Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. single/dual mode, Table Table
BLINK_LED
Blink Mode. power-up reset, when pulled high through resistor, activity output will blink high 0.5s 0.5s whenever there activity, unless STRETCH_LED high, which case blinking 2.5s high 2.5s low. This signal ORed with register This internal pull-down resistor; default blink mode disabled.
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS SIGNAL SPEEDLED3 TYPE DESCRIPTION Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. single/dual mode, Table Table DESC_BYP Scrambler/Descrambler Bypass. power-up reset, this used enable DESC_BYP function pulling this high through resistor, station management unavailable. This same function register This internal pull-down resistor; default disabling scrambler/descrambler. SPEEDLED2 Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. Serial Strobe. This synchronizing strobe serial data output stream that goes high start each serial stream, once every clocks when serial mode. Auto-negotiation Enable. power-up reset, when this through resistor, autonegotiation enabled. Pulsing this will cause autonegotiation restart. This input same function register This input register ANDed together. This internal pull-down resistor; default auto-negotiation
SERSTR
AUTO_EN
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS SIGNAL SPEEDLED1 TYPE DESCRIPTION Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. Serial Data. single serial data stream output that contains status information from eight AL216 ports. serial mode enabled pulling LED_MODE[1] high through resistor, LED_MODE[0] power-up reset. Carrier Integrity Enable. power-up reset, this pulled high through resistor, will enable carrier integrity function register station management unavailable. This internal pull-down resistor normal operation (CARIN_EN disabled).
SERDATA
CARIN_EN
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS SIGNAL SPEEDLED0 TYPE DESCRIPTION Speed This indicates operating speed port When link high, this indicates Mbit/s operation. When link high, high indicates Mbit/s operation. active-low output. Serial Clock. This approximately 1.56 clock output used clock serial data, when serial mode enabled pulling LED_MODE[1] LED_MODE[0] high through resistor power-up reset. Mode [1:0]. power-up reset, mode configuration pins [1:0] used select mode operation pulling them high through resistor shown below.
Modes Mode Mode Mode Parallel Reserved Serial Bicolor Outputs SPEEDLED[7:0], FDUPLED[7:0],LINKLED[7:0] Reserved SERCLK, SERDATA, SERSTROBE SPEEDLED[7:0], LINKLED[7:0]
SERCLK
LEDMODE0
When serial mode, eight channels' functions will multiplexed onto serial output stream. When bicolor mode, each eight channels will have outputs each, drive bicolor LED. These pins have internal pull-down resistors. FDUPLED7 Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. mode select, Table Table Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. mode select, Table Table
FDUPLED6
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS SIGNAL FDUPLED5 TYPE DESCRIPTION Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. mode select, Table Table Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. mode select, Table Table Mode Refer truth table under mode (B14) setting this pin. Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. mode select, Table Table Enhanced Link Integrity Test Function. When this input pulled high power-up reset through resistor, AL216 will detect change speed from Mbit/s Mbit/s, when instantaneous speed change occurs. This ORed with register This internal pull-down resistor; default LITF_EN disabled.
FDUPLED4
LEDMODE1 FDUPLED3
LITF_ENH
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AL216 Preliminary
Table Configuration Pins (Continued)
PINS SIGNAL FDUPLED2 TYPE DESCRIPTION Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. Table Table Mode. This input, when pulled powerup reset through resistor, will cause AL216 provide three LEDs port parallel mode. three LEDs speed, link duplex. When pulled high, AL216 will provide LEDs port parallel mode depending selection LEDSELECT input. input LEDSELECT will provide activity/link speed/duplex. This internal pull-down resistor; default three LEDs port parallel mode. FDUPLED1 Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output. Table Table Smart Mode. This mode determines pins have configured pull-up pull-down. this mode enabled, will then drive with appropriate logic level When this input pulled high power-up reset through resistor, SMARTLED mode enabled. This internal pull-down resistor; default SMARTLED mode enabled. this mode, LEDs driven default (i.e., active-low). FDUPLED0 Full-Duplex This output operates full-duplex indicator when AL216 fullduplex mode. this device half-duplex mode, then this output becomes collision output. active-low output.
TWO_LED_ MODE
SMARTLED
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AL216 Preliminary
Table Input Interface
PINS AD18, AF19, AE19, AF18, AD17, AE18, AC17, AF17, AD16, AC15, AF16, AD15, AE16, AF15, AD14, AE15, AD13, AF14, AC14, AE14, AD12, AF13, AC12, AE13, AD11, AF12, AE12, AF11, AD10, AE11, AC10, AF10 AD9, AE10, AF9, AE9, AD8, AF8, AC9, SIGNAL RID[31:0] TYPE DESCRIPTION Ring Input Data.
RIDH RICTLH RICTL[7:0] RICLK
Ring Input Data Header. Ring Input Control Header. Ring Input Control Signal. Ring Clock.
Table Output Interface
PINS A14, C15, B13, D13, A13, C14, B12, C13, A12, B11, C12, A11, D12, B10, C11, A10, D10, C10, SIGNAL ROD[31:0] TYPE DESCRIPTION Ring Output Data.
RODH ROCTLH ROCTL[7:0]
Ring Output Data Header. Ring Control Header. Ring Output Control Data.
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AL216 Preliminary
Table SGRAM/SDRAM Interface
PINS AA2, AA1, AB2, AB1, AA3, AC2, AB4, AC1, AB3, SIGNAL PBD[31:0] TYPE DESCRIPTION SGRAM SDRAM Data Bus.
PBA9_10
Packet Buffer Address 9/10. This connected address when connected Mbit SGRAM address when connected Mbit SGRAM. Packet Buffer Address 8/9. This connected address when connected Mbit SGRAM address when connected Mbit SGRAM. Packet Buffer Address 8.This connected address when connected Mbit SGRAM connect when connected Mbit SGRAM. SGRAM Address Lines. PBA0- PBA7 sampled during ACTIVE command (row address READ/WRITE command (column address with PBA8 defining auto precharge). Chip Select. active-low enables disables command decoder SGRAM SDRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. (Active-Low)
PBA8_9
PBANC_8
AE3, AF3, AE4, AD4, AF4, AE5, AC5,
PBA[7:0]
PBCSN
PBRASN PBCASN PBWEN
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AL216 Preliminary
Table SRAM Interface
PINS SIGNAL ETD[15:0] TYPE DESCRIPTION SRAM Data Bus.
ETA[15:0]
SRAM Address Line. Table Table ETA[5:0]. Table ETA[15:6] (dual MII). Synchronous Address Status Controller. Mode Table Table Synchronous Address Advance. Used advance SRAMs internal burst counter. Mode Table Table Global Write. Enables full 32-bit write. Mode Table Table Output Enable. (Active-Low). This enables data output driver. Mode Table Table System Clock Output.
ETADSCN
ETADVN
ETGWN
ETOEB
ETCLKI
Table EEPROM Interface
PINS AF20 AC19 AE20 SIGNAL EEDIO EECLK EPBYPASS TYPE DESCRIPTION EEPROM Data Input Output. EEPROM Clock. EEPROM Bypass. This bypasses EEPROM setup. This should tied ground normal operation.
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AL216 Preliminary
Table Miscellaneous Pins
PINS AC22, AE23 AD19 SIGNAL DEVID[1:0] RESETN TYPE DESCRIPTION Device Number. Reset. Reset must asserted least 1ms. AL216 will come reset after RMCLK must running during reset. Bypass PLL. normal operation. Select External MDIO. This signal allows station management access registers external MDIO interface. normal operation. Management Data Clock. This timing reference transfer data MDIO signal. This signal asynchronous RMCLK. maximum clock rate 12.5 MHz. When running above 6.25 MHz, must synchronous with RMCLK have setup time hold time with respect RMCLK. AE24 TMDIO Management Data Input/Output. This used transfer control status information between AL216 station management. Control information driven station management synchronous with MDC. Status information driven AL216 synchronous with MDC. This requires external pull-up resistor. Reference Input Buffers. REF_ACS must connected system ground through resistor. External Bias Resistor. Connect this 24.9 resistor ground. parasitic load capacitance must less than External Bias Resistor 100. Connect this 21.5 resistor ground. This sets Mbit/s driver output level. External Bias Resistor Connect this 20.1 resistor ground. This sets Mbit/s driver output level. Crystal Output. used.
AF24
BYPASSPLL SEL_MDIO
AD23
TMDC
AE17
REF_ACS
REXTBS
REXT100
REXT10
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AL216 Preliminary
Table Miscellaneous Pins (Continued)
PINS SIGNAL RMCLK SYSCLK CLK250 TYPE DESCRIPTION Clock Input. CMOS input level clock input. ppm, duty cycle. System Clock Input. switch fabric requires clock. Clock Input PHY.
Table Test Mode Pins
PINS AE21 SIGNAL TYPE DESCRIPTION Test Data Input. Serial data input JTAG controller. Sampled rising edge TCK. When JTAG mode, low. Test Data Output. Serial data output from JTAG controller. Updated falling edge TCK. When use, leave unconnected. Test Mode Select. When pulled high through resistor, this selects JTAG test mode. When use, low. Test Clock. JTAG clock input used synchronize JTAG control data transfers. When unused, low. Test Reset. Asynchronous active-low reset input JTAG controller. normal use, low. Scan Mode Select. Places AL216 scan mode. normal operation. Test Mode Select. Reserved manufacturing testing. This should tied normal operation. Status Serial Output. testing only. 3-State CMOS Outputs. Tying this will place CMOS outputs high-impedance state. normal operation, pull this input high.
AE22
AC20
AD20
TCLK
AF22 AF23
TRST SCANMODE Figure Figure TESTMODE Figure Figure SSOUT TRI_ALLN
AD21
AF21 AD22
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AL216 Preliminary
Table Power Interface
AA4, AA23 AC6, AC11, AC16, AC21 D11, D16, D21, F23, L23, A15, A25, E24, F24, G24, H24, J24, K23, M23, P24, P26, T24, A26, AC4, AC8, AC13, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26, B25, B26, C24, D14, D19, D23, J23, P23, AA24, AB23, AB24, AC24, AE26, C25, C26, D24, E23, G23, H23, J25, J26, K24, L24, M24, M25, M26, N23, N24, R24, T25, V23, W24, Y23, V24, DESCRIPTION VDD. Digital power VDDA. Analog power VDDM. moat must connected analog supply, VDDA. VDDPLL. System clock phase-locked loop power VSS. Ground.
VSSPLL. System clock phase-locked loop ground. connect.
Note: balls center should connected ground. These pins rows through columns through
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AL216 Preliminary
Twisted Pair Port Twisted Pair Port Twisted Pair Port Twisted Pair Port Twisted Pair Port Twisted Pair Port Twisted Pair Port Twisted Pair Port PBD[n] PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY 10/100 MAC/PHY High Speed Switch Fabric
Switch Controller Expansion Interface Address Control
ROD[n] ROCTL[n] RODH ROCTLH RID[n] RICTL[n] RIDH RICTLH RICLK Control Signals ETA[n] ETD[n] MDIO
SRAM Interface Address Table Management
Buffer Manager
Management Information EEPROM Interface EEDIO EECLK DEVID1 DEVID2 RESET JTAG SCAN SYSCLK RMCLK
Figure
AL216 Interface Block Diagram
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AL216 Preliminary
Functional Description
RoXInterface
switch system shown Figure 24-port 10/100 Mbit/s Ethernet switch. This system utilizes architecture which serves system backplane.
AL300A
AL216
AL216
AL216
Figure
Managed Switch Implementation using with 24-Port 10/100 Mbit/s
ring composed data ring control ring. data ring used transfer frame data, events, well system configuration status report messages. control ring used communicate ring protocol messages among devices, which used switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. management device (MIB) resides ring. provides network management function devices ring. device collects network statistics switch system well provide system configuration devices. interface provided device. This supporting chip, AL300A, provides full statistical counters support both SNMP RMON network management.
Data Reception
interface will check start frame delimiter (SFD). Once detected, will then decide what action take whether frame data forwarded stored buffer switch. 3.2.1 Illegal Frame Length During receiving process, will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames with illegal frame lengths discarded.
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AL216 Preliminary
3.2.2 Long Frames AL216 handle frames 1536 bytes. frames longer than 1536 bytes will discarded. port continues receive data after 1536 byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.2.3 False Carrier Events carrier sense (CRS) signal asserted internally receive data valid (RX_DV) flag asserted within 16-bit-time (BT), port considered have false carrier event. false carrier event recorded counter. 3.2.4 Frame Filtering AL216 will make filtering forwarding decision each frame received based frame routing table, VLAN mapping, port state, system configuration. Received frames filtered under following conditions: AL216 will check received frames errors such symbol error, error, short event, RUNT, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frame when input buffer becomes available. frame security violations security option enabled receiving port.
spanning tree protocol enabled, AL216 will forward frame follows: port block-n-listen state learning state, forward frame when bridged protocol data unit (BPDU) frame; discard frame otherwise. port forwarding state, forward frame when BPDU frame.
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AL216 Preliminary
Frame Forwarding
After frame received, source address (SA) destination address (DA) retrieved. used update port's address table used determine frame's destination port. address lookup engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address frame regarded unicast frame. destination address passed address lookup engine which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving ports, frame will discarded. event will recorded VLAN boundary violation. There ways that AL216 handles frames with unknown destinations. forwarding decision controlled flood control option (System Configuration Register flood control disabled, frame will forwarded ports (except receiving port) within same VLANs receiving port. flood control option enabled, AL216 will forward frame only uplink port specified receiving port. AL216 defines port either single port trunk. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address frame will handled multicast broadcast frame. AL216 does differentiate multicast frames from broadcast frames, except reserved bridge management group address, specified Table IEEE 802.1d standard. destination ports broadcast frame ports within same VLAN, except source port itself. multicast/broadcast frame trapping (MCtrap) enabled, multicast/broadcast frames will forwarded only. 3.3.1 Broadcast Storm Control unique features provided AL216 broadcast storm control. This option allows user limit number broadcast frames into switch. This option implemented per-port basis. threshold number broadcast frames programmed System Configuration Register When storm control enabled number accumulated non-unicast frames over programmed threshold, broadcast frame discarded. storm control disabled number non-unicast frames received port over programmed threshold, AL216 will forward frame ports (except receiving port) within VLANs specified receiving port. port within specified VLAN, frame will also forwarded CPU. broadcast storm drop (BConly_SC) enabled, AL216 will only drop broadcast frames multicast frames.
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3.3.2 Frame Transmission AL216 transmits frames accordance IEEE 802.3 standard. AL216 will send frames with guaranteed minimum inter-packet/frame (IPG) even received frames have less than minimum requirement. AL216 also supports transmission frames with (optional). 3.3.3 Frame Generation During transmit process, frame data read from memory buffer forwarded destination port's device nibbles. Seven bytes preamble signal (10101010) will generated first before (10101011) frame data sent, then four bytes sent. Summary Programmable Control Transmit Receive control transmit receive operation per-port basis. options programmable Port Configuration Register (registers 1Ch). Data rate duplex mode. This option per-port option. Typically, speed auto-negotiated. manual override, appropriate port configuration register programmed. Flow control. flow control implemented independently per-port basis. AL216 uses backpressure half-duplex flow control IEEE 802.3x full-duplex flow control. Flood control. AL216 provides modes unmatched address forwarding. flood-to-all option elected, AL216 will forward unmatched frames ports. Secure mode. security option implemented per-port basis. When port configured secured mode, security violation will disable port. security violation defined frame without matched secured port's address table.
Half-Duplex Mode Operation
half-duplex operation, logic will abort transmit process collision detected through assertion collision (COL) signal PHY. Retransmission frame scheduled accordance IEEE 802.3's truncated binary exponential back-off algorithm. transmit process encountered consecutive collisions, excessive collision error reported, AL216 will retransmit frame unless retry-on-excessivecollision (REC) option enabled. enabled, number collisions reset zero transmission started soon inter-packet have passed after last collision. collision detected after transmission, late collision error will reported, frame will still retransmitted after proper back-off time. AL216 also provides option aggressive back-off System Configuration Register (Register SuperMAC). This option allows back only three slots. This will create more aggressive channel capture behavior than standard IEEE backoff algorithm.
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Secure Mode Operation
AL216 provides security support per-port basis. Whenever secure mode enabled, port will stop learning addresses. address table each port will remain unchanged. this mode operation, address lookup table will freeze additional addresses will learned. AL216 provides levels security protection. most severe intrusion protection disabling port experiencing intrusion. security management (SecMgmt System Configuration Register Register will disable port frame with unlearned received secured port (security violation). Once port disabled, only enabled network management. Security management global option. alternative method enable security local port level without security management. When AL216 configured such, device will only discard frames that have security violation. This used environment where intruders prevented from accessing network. Summary Programmable Registers SecMgmt (register 00). This sets global security management option. AL216 will partition port that experiences security violation. Security (register 1C). This port configuration option. When this option enabled, port secured. When port receives security violation frame, will discard frame security management disable port security management
Address Learning
table lookup engine provides switching information required routing data frames. address lookup table through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM management device. static address entries will aged updated AL216. After frame received AL216, embedded source address (SA) destination addresses (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL216 will then check error security violation, perform search. there error security violation, device will store source address address lookup table. been previously stored another port's table, AL216 will delete from previously stored location. individual address 48-bit unique address programmed learned. will masked, i.e., multicast AL216 provides on-chip MACAddress-To-PortID/TrunkID table with entries frame destination lookup operation. Optional external SRAM used increase number address 16K. AL216 address table contains both static addresses, input EEPROM dynamically learned addresses. learns individual addresses from following three sources: Frames received with errors from local ports.
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Frames forwarded from other devices through ring device. Table convergence messages received from ring, which issued device itself.
received frame contains source address that already been learned another port's address table aged out, will perform following operation based switch's configuration. security option selected port, AL216 will consider this security violation. port non-protected port, AL216 will delete from previous port's address table update current port's address table. However, static address entry, address will updated.
3.6.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed less than programmed time. Summary Programmable Options Address Learning Address Aging Time. address aging aging time programmed system configuration register (register 01). resolution aging time normally increments second. SlowAge (register programmed resolution will second increments. Static Programmed Addresses. static addresses programmed EEPROM addresses section EEPROM programming more detail.
Link Aggregation/Trunking
AL216 supports link aggregation/trunking. Link aggregation trunking basically method treat multiple physical links single logical link. benefit trunking able group multiple lower speed links into higher speed link. example, four full-duplex Mbit/s links used single Mbit/s link. This very useful switch switch, switch server, switch router applications. AL216 considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link. grouping ports trunk must from four ports bottom four ports device, i.e., port port total eight trunks supported ring chip sets. multiple link trunk, links within trunk should have equal amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk deployed. AL216 offers alternative load balancing methods. selection load balancing method System Configuration Register (register 00).
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Load Balancing
load-balancing methods that AL216 uses support trunking port-based MACaddress-based. port-based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frames might routed trunk randomly, this could cause frames arrive order. port-based load balancing trunk two-, three-, four-port trunk. During transmission, frame will routed from source port assigned trunk port. When frame received from trunk ports, will routed destination port within VLAN. essence, AL216 treats trunk single port within same VLAN. traffic ports evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex). alternative MAC-address-based load balancing. When AL216 receives frame with trunk destination, will automatically forward frame port trunk, based source address. address load balancing decision based proprietary algorithm. algorithm assumes trunk four-port trunk. Therefore, MAC-address-based load balancing used, trunk must consist four ports. (Use MAC-based load balancing two- threeport trunks could result loss frames.) advantage port-based load balancing ability support two- three-port trunks. 3.8.1 Trunk Port Assignment maximum number trunks ring architecture eight. port configuration registers provide ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports. example, trunk consist either port port Each trunk port's number sequence corresponding order port devices. example, port Figure 3.8.2 Port-Based Trunk Loading port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port Registers 34). port assignment worksheet provided Appendix recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. following procedure trunk: Select trunk ports using Port Configuration Registers Assign ports Trunk Port Register 34). port should assigned appropriate trunk using this register. trunk port itself, port assignment should assigned itself. port trunk port worksheet provided Appendix page 107. Assign port trunk port port trunk port register. This necessary because each port group trunk must assigned trunk port. assigning trunk port itself, broadcast frames will routed back source port.
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Assign ports trunk port same VLAN using register port VLAN grouping should only include trunk port assigned other trunk ports. This ensure that broadcast frames will only forwarded assigned port.
AL216
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
Port-Based Loading Example Register bits referenced where register number number. following example shows 3-port trunk assigned 8-port switch. desired trunk ports Therefore, port configuration register bits 17.9, 19.9, 1B.9 trunk port, port should assigned itself. Assign port trunk port port trunk port port trunk port trunk ports therefore, trunk number assignment port trunk port register bits should follows: 2D.2 2D.3 2E.2 2E.3 2F.2 2F.3 30.2 30.3 31.2 31.3 trunk ports, trunk ports should assigned their port number port trunk port register. port trunk port bits follows: 32.2 32.3 33.2 33.3 34.2 34.3
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Table Trunking Port Assignment
Reg. 2d/Port Reg. 2e/Port Reg. 30/Port Reg. 31/Port Reg. 32/Port Reg. 33/Port Reg. 34/Port Reg. 2f/Port
Trunk Port
Value
Trunk Bits Trunk Bits Trunk Bits Trunk Bits Trunk Bits Trunk Bits
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Table Trunking Port Assignment (Continued)
Trunk Bits Trunk Bits
Assigning VLAN VLAN assigned shown Table bits bits 21.6 21.7 because port assigned port other ports similarly.
Table VLAN 8-Port Switch with 3-Port Trunk
Port Port Port Port Port Port Port Port Reg. Port DEVICE
Reg.
Reg.
Reg.
Reg.
Reg.
Port Port Port Port Device Port Port Port Port
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Reg.
AL216 Preliminary
Table VLAN 8-Port Switch with 3-Port Trunk (Continued)
Port Port Port Port Device Port Port Port Port
3.8.3 Based Load Balancing Setup MAC-address-based load balancing, there need assign trunk port. AL216 dynamically assigns address trunk port. address based trunks must consist four trunk ports. bits chosen their randomness. statistically random bits will ensure good load balancing among four trunk ports. following procedure trunk: Select address loading setting 00.3 Select trunk ports using registers Assign ports trunk port same VLAN using registers port VLAN grouping should include trunk ports. Since AL216 will assign port addresses, frames from single port routed trunk ports. Based Load Balancing Example simplicity, example 8-port switch with 4-port trunk. desired trunk port Therefore, port configuration register bits 15.9, 17.9, 19.9, 1B.9 Assign VLAN. VLAN assigned shown Table bits except ports themselves.
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Table VLAN 8-Port Switch with 4-Port Trunk with Based Loading
Port Port Port Port Port Port Port Port Reg. Port DEVICE
Reg.
Reg.
Reg.
Reg.
Reg.
Port Port Port Port Device Port Port Port Port Port Port Port Port Device Port Port Port Port
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Reg.
Reg.
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Summary Programmable Registers System Configuration (register 00). 00.3 sets trunk address loading. System Configuration (register 01). 01.0 01.1 bits address loading algorithm. Trunk Port Designation (registers 1C). port configuration register designates port trunk port. Port Trunk Port Loading Assignment (registers 34). These registers assign loading trunk. Port VLAN (register 2C). These registers assign port VLAN.
Spanning Tree Support
AL216 capability support implementation spanning tree protocol. ports programmed port state required spanning tree protocol. spanning tree protocol option enabled, AL216 will forward frame follows: port block-n-listen state learning state, frame forwarded BPDU frame; frame discarded otherwise. outgoing frames except outgoing BPDUs will masked from path PHY. port forwarding state, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY. port learning state, source addresses incoming frames from will learned. incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY.
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3.10 Flow Control
AL216 operate different modes: half- full-duplex. Each port operate either half- full-duplex configured have flow control enabled disabled independently per-port basis. 3.10.1 Half Duplex Flow Control (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever receive frame buffer port full, port will start sending signal through port. remote station will defer transmission after sensing signal. Backpressure flow control applied ensure that there dropped frames. AL216 supports types backpressure: collision based carrier based. Carrier-based backpressure generated AL216, when switch port's frame buffer full. AL216 will cease line when port buffer space available frame reception. jamming signal programmed either Collision-based backpressure generated AL216 only when switch port receives frame. AL216 will cease line when line idle.
carrier-based backpressure several advantages over collision-based backpressure. Collision-based backpressure cause late collisions. After consecutive collisions, could drop frames. AL216 option drop frames after consecutive collisions. However, terminal still drop frames.
Therefore, recommend carrier-based backpressure preferred method halfduplex flow control. this mode operation, also recommend that signal should reason this recommendation far-end terminal might still able transmit frame cause collision. excessive collisions could cause frames dropped. 3.10.2 Full-Duplex Flow Control (802.3x) full-duplex mode, AL216 will transmit receive frame accordance 802.3x. transmission channel receiving channel operate independently. incoming direction, whenever receive frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below FlowControlOff threshold, port will then send PAUSE frame with delay value zero resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished, start pause timer. will resume frame transmission either after pause timer expires when PAUSE frame with zero delay value received.
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When 802.3x flow control option elected, device will program appropriate auto-negotiation capability field. When AL216 used full-duplex mode, recommended that flow control should turned This prevent buffer from overflow loss frames. connected device 802.3x capability, then recommended that link half-duplex.
3.11 Queue Management
Each port AL216 individual transmit receive queues. frames coming into AL216 stored shared memory buffer, lined transmit queues corresponding destination port. Each port AL216 input frame queue dedicated queue buffer locally generated management event messages. Each output port maintains output frame queue dedicated multicast queue outgoing multicast frame parking. transmit frame from sources: local, from another device ring. output queue, source selected multicast queue, device will channel copy frame head multicast queue output queue transmission. output queue, source selected local input queue, device will channel from local DRAM buffer output queue upon requested DRAM bandwidth, available. output queue, source selected from another device ring, device will send message that device attempt channel through ring from source input queue that device local output queue. multicast queue, source selected local input queue, device will channel from local DRAM buffer multicast queue upon requested DRAM bandwidth, available. multicast queue, source selected from another device ring, device will send message that device, trying channel through ring from source input queue that device local multicast queue.
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3.12 VLAN Support
Each port AL216 assigned one, multiple, VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) source port except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. Otherwise, frame will treated frame with unknown destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port should assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL216 provides VLAN registers port (register mapping 32-ports bits). Each register contains 16-bit bit-map (total bits) indicate VLAN group port. VLAN registers hold broadcast destination masks each source port. will indicate broadcast frames will routed from source port specified port. Note that source port must within source port VLAN, because broadcast frames routed source port. setting VLAN trunking, please Link Aggregation/Trunking page details. VLAN Setup Example VLAN setup worksheet provided Appendix complete VLAN easily marking ports that desired send broadcast frame example, following VLAN groups 16-port switch Group consists Group consists Note: might easier mark VLAN ports first then delete source ports that broadcast frames returned completed VLAN bit-maps shown Table Table
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Table Device VLAN 16-Port Switch
Port Port Port Port Port Port Port Port Device Port Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Port Port Port Port Device Port Port Port Port Port Port Port Port Device Port Port Port Port
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Reg.
AL216 Preliminary
Table Device VLAN 16-Port Switch
Port Port Port Port Port Port Port Port Device Port Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Port Port Port Port Device Port Port Port Port Port Port Port Port Device Port Port Port Port
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Reg.
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3.13 Uplink Port
uplink port provides means connect switch with repeater hub, workgroup switch, router, type interconnecting device compliant with IEEE 802.3 standard. port also designated uplink port. flood control enabled, AL216 will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register 1C), data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLAN, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL216 will direct following frames uplink port: Frames with unicast destination address that does match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN.
When configuring uplink port, uplink port should designate itself uplink port.
3.14 Port Monitoring
AL216 supports port monitoring. This feature provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. AL216 allows transmit receive data monitored different snooping ports. monitored port snooping port selected port monitoring configuration register (register 06). Summary Programmable Register Designate Uplink Port (register 1C). This register provides option designate uplink port either port, trunk, CPU. details register description. Port Monitoring Register (register 06). This register selects target monitored port snooping port. 5-bit Port_ID designates port. format Port_ID [Dev_ID], [Port_ID]. [Dev_ID] device number [Port_ID] port number.
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3.15 Physical Layer Transceivers
AL216 integrates eight 100Base-X physical sublayers (PHY), 100Base-TX physical medium dependent (PMD) transceivers, eight complete 10Base-T modules both Mbit/s Mbit/s Ethernet operation. also supports 100Base-FX operation through external fiber-optic transceivers. transceiver capable operating either full-duplex mode half-duplex mode either Mbit/s Mbit/s operation. Operational modes selected hardware configuration pins software settings management registers, determined onchip auto-negotiation logic. Physical Layer Transceivers Supports auto-negotiation (IEEE 802.3u, clause Fast link pulse (FLP) burst generator Arbitration function Supports station management protocol frame format (clause Basic extended registers Supports next page mode Accepts preamble suppression 12.5 clock rate Supports following management functions pins: Speed select Scrambler/descrambler bypass Full-duplex Carrier integrity enable Auto-negotiation mode select Supports half- full-duplex operations Per-channel power-down mode Mbit/s Mbit/s operations Loopback Mbit/s Mbit/s operations Internal pull-up pull-down resistors default configuration during powerup
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10Base-T Transceiver Compatible with IEEE 802.3 10Base-T standard Category unshielded twisted-pair (UTP) cable Auto-polarity detection correction Adjustable squelch level extended line length capability (two levels) On-chip filtering eliminates need external filters Half- full-duplex operations
100Base-TX Transceiver Compatible with IEEE 802.3u (clause 23), (clause 24), autonegotiation (clause 28), (clause specifications Scrambler/descrambler bypass Full- half-duplex operations On-chip filtering adaptive equalization that eliminates need external filters
100Base-FX Transceiver Pseudo-ECL compatible input/output 100Base-FX support (with fiber-optic signal detect) Compatible with IEEE 802.3u 100Base-FX standard Reuses existing twisted-pair pins compatible fiber-optic transceiver pseudo-ECL (PECL) data additional data pins required Reuses existing AL216 pins fiber-optic signal detect (FOSD) inputs Fiber mode automatically configures port Disables auto-negotiation Disables 10Base-T Disables 100Base-FX far-end fault signaling Disables MLT-3 encoder/decoder Disables scrambler/descrambler mode enable pin- register-selectable individual per-port basis (register
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3.16 Management
AL216 supports transceiver management either through ring, AL300A through serial MDIO signal lines. access registers through MDIO pins, SEL_MDIO input must tied logic serial management interface used obtain status configure PHY. This mechanism corresponds specifications 100Base-X (Clause 22), supports register through register Additional vendor-specific registers implemented within range summary registers described Management Register section, Table 3.16.1 Management Register Access management interface consists pins, management data clock (MDC) management data input/output (MDIO). AL216 designed support frequency specified 12.5 MHz. MDIO line bidirectional shared devices. MDIO requires pull-up resistor which will pull MDIO logic state during idle turnaround periods. Each management data frame 64-bits long. first bits preamble consisting continuous logic 1-bits MDIO corresponding cycles MDC. Following preamble start-of-frame field indicated <01> pattern. next field signals operation code (OP). <10> indicates read from management register operation, <01> indicates write management register operation. next fields device address management register address. Both five-bits wide, most significant transferred first. During read operation, two-bit turnaround (TA) time spacing between register address field data field provided MDIO avoid contention. Following turnaround time, 16bit data stream read from written into management registers AL216. AL216 supports preamble suppression mode indicated basic mode status register (BMSR, address 01h). station management entity (i.e., other management controller) determines that PHYs system support preamble suppression reading this bit, then station management entity need generate preamble each management transaction. AL216 requires single initialization sequence 32-bits preamble following power-up/hardware reset. This requirement generally mandatory pull-up resistor MDIO management access made determine whether preamble suppression supported. While AL216 will respond management accesses without preamble, minimum idle between management transactions required specified IEEE 802.3u.
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VDDO RJ-45 TPOUT+ 51.1 51.1 TPOUT- AL216 TPIN+ TPIN- 0.01 0.01 1000 0.01
Figure
Typical Single-Channel Twisted-Pair (TP) Interface
3.17 Operational Modes
AL216 provides three basic output modes operation: parallel mode, serial mode, bicolor mode. parallel mode provides three output signals each eight channels signals total): speed, link, full-duplex. serial mode multiplexes eight channels' status information onto single serial output stream. single data stream, SERDATA, accompanied with serial clock SERCLK, serial strobe SERSTROBE (three signals total). bicolor mode provides output signals, SPEEDLED[7:0], LINKLED [7:0], each eight channels signals total). These outputs intended drive bicolor LED, packaged single package. This reduces total number packages channel. Additional output control obtained using management registers. Each forced either high register MR20 per-channel basis. register MR20 that overrides value, matter what mode device outputs active-low outputs; external buffers required. mode operation selected power-up reset LED_MODE [1:0], TWO_LED_MODE configuration pins, LEDSELECT pin.
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3.17.1 Parallel Mode When operating parallel mode, each channel three outputs: speed, link, full duplex depending setting TWOLED mode. AL216 placed parallel mode power-up reset, when LEDMODE[1:0] connected logic parallel mode operate modes, depending setting TWOLED power-up reset. When TWOLED mode input parallel mode will provide three LEDs each port: speed, link, duplex. LEDSELECT ignored this mode. When TWOLED mode input one, only LEDs port available. outputs selected, depending state SELECTLED input. SELECTLED input will change what status present LEDs. SELECTLED input could driven from toggle switch that used select whether would like display either activity link, speed duplex 8-ports.
Table Modes
SELECT MODE MODE TWOLED
MODE
SPEEDLED
LINKLED
FDUPLED
Parallel
Activity activity Mbit/s Mbit/s Mbit/s Link Mbit/s link SPEEDLED0: SERLEDCLK SPEEDLED1: SERLEDDATA SPEEDLED2: SERLEDSTRB
Link link Half-duplex Full-duplex link Link Activity) Blinking Activity
function function Full-duplex Half-duplex
Serial
function
function
Reserved Bicolor Single Mode Dual Mode
function Blink yellow function function
function Blink green Link link function
function function function function
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3.17.2 Serial Mode When serial mode selected, status information from eight channels multiplexed into serial data stream. activity function still stretched blink described above each output still forced high described above. Table outlines three-pin serial interface. Serial Stream Order Every SERLEDSTROBE indicates that serial stream follows. Each serial stream consists following components: Chnl[4:0] current channel count channel (A), channel 00101 channel (F)). other signals discussed above. Note that data always goes high when strobe goes high; thus, user wishes implement two-pin interface using just clock data, this high pulse used synchronization. Chnl[4:0] will cycle through each addresses from before starting over. Since strobe occurs once every clocks, there will clocks between each data burst. Thus, data burst looks something like (for channel then channel looks like shown Table
Table Serial Descriptions
SIGNAL SERLEDCLK TYPE Output DESCRIPTION This roughly output clock MHz/16 MHz). other serial signals change after falling edge this clock. This clock generated from LEDCLK. This serial stream, clocked SERLED clock. serial stream contents discussed below. This strobe, which goes high start each serial stream. strobe occurs once every clocks.
SERLEDDATA SERLEDSTROBE
Output Output
Table Serial Port Order
CLOCK STROBE DATA Chnl(4) Chnl(3) Chnl(2) Chnl(1) Chnl(0) Link
CLOCK STROBE DATA
Speed
FullDup
Coll
Jabber
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DATA STROBE
DATA STROBE
DATA STROBE DATA STROBE
Figure
Serial Mode Timing Diagram
3.17.3 Bicolor Mode When bicolor mode selected, AL216 provides output signals channel. These signals speed outputs (SPEEDLED) link outputs (LINKLED). These signals work together drive single bicolor channel. bicolor single package with LEDs connected parallel, with opposite polarities. bicolor mode, bicolor LEDs connected between blink yellow blink green signals shown Table LEDs connected this way, LEDs would then flash color indicate link second indicate activity.
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Mode Configurations
some applications might desirable connect AL216 directly interface such HomePNA certain CPUs that feature interfaces. AL216 offers special modes which integrated PHYs ports bypassed interfaces these ports made available user. Since both these modes interfaces certain pins pins normally used external address table, these functions available modes.
Single Configuration
port AL216 accessed through pins SPEEDLED pins. Four ports from AL216 selected configuring FDUPLED[2:1]. When single mode, SPEEDLED longer operational. AL216's serial mode used bring signals. Steps Required Enable Feature Disable external address table setting System Configuration Register Disable MDIO used port. Configure pins from Table switch will read configuration upon power reset.
Table Single Mode LEDs
Mode Single Mode Test Mode Scan Mode FDUP LED[7] FDUP LED[6] FDUP LED[5] FDUP LED[4] FDUP LED[3] FDUP LED[2:1] When Port Port Port Port
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Table Single Port (1/3/5/7)
Signal RXD0 RXD1 RXD2 RXD3 RXCLK RXDV RXER TXD0 TXD1 TXD2 TXD3 TXCLK TXEN AL216 Signal ETA5 ETA4 ETA3 ETA2 ETADSCN ETA1 ETADVN SPEEDLED7 SPEEDLED6 SPEEDLED5 SPEEDLED4 ETOEB SPEEDLED3 ETGWN ETA0
Dual Configuration
ports AL216 accessed through SPEEDLED, LINKLED pins. Four port pairs from AL216 selected configuring FDUPLED[2:1]. When dual mode, external address table, SPEEDLED LINKLED longer operational. AL216's serial mode used bring signals. Steps Required Enable Dual Feature Disable external address table setting System Configuration Register Disable MDIO used ports. Configure pins from Table switch will read configuration upon power reset.
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Table Dual Mode LEDs
Mode Dual Mode Test Mode Scan Mode FDUP LED[7] FDUP LED[6] FDUP LED[5] FDUP LED[4] FDUP LED[3] FDUP LED[2:1] When Port Port Port Port Port Port Port Port
Table Dual Port (0/2/4/6)
Signal RXD0 RXD1 RXD2 RXD3 RXCLK RXDV RXER TXD0 TXD1 TXD2 TXD3 TXCLK TXEN AL216 Signal ETA15 ETA14 ETA13 ETA12 ETA7 ETA11 ETA8 LINKLED7 LINKLED6 LINKLED5 LINKLED4 ETA6 LINKLED3 ETA9 ETA10
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Table Dual Port (1/3/5/7)
Signal RXD0 RXD1 RXD2 RXD3 RXCLK RXDV RXER TXD0 TXD1 TXD2 TXD3 TXCLK TXEN AL216 Signal ETA5 ETA4 ETA3 ETA2 ETADSCN ETA1 ETADVN SPEEDLED7 SPEEDLED6 SPEEDLED5 SPEEDLED4 ETOEB SPEEDLED3 ETGWN ETA0
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SGRAM SDRAM Interface
ports AL216 work store-and-forward mode that ports support both Mbit/s Mbit/s data speed. AL216 utilizes central memory buffer pool, which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL216 designed MHz, 8-Mbit SGRAM 16-Mbit SGRAM cost performance. memory size selected through SG16M System Configuration Register SGRAM accessed page burst access mode very high-speed access. This burst mode must repeatedly access same column. burst mode reaches column address, then wraps around first column address continues count until interrupted news read/write, precharge, burst stop command. AL216 will initialize SGRAM automatically. precharges banks inserts eight autorefresh commands. will also program mode registers AL216 read write operations. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM auto-refresh. Auto-refresh uses refresh address counter. SGRAM auto-refresh command generates precharge command internally SGRAM. AL216 will insert auto-refresh command once every During transmit, frame retrieved from buffer pool forwarded destination port. SDRAM interface, either SDRAM memory module used. interface between AL216 memory module connected follows: Connect RAS, CAS, CLK, directly SDRAM memory. logic Connect AL216 A0-A10 address lines A0-A8, A10, memory module. DQML, DQMH, logic
SRAM Interface
additional byte static required user needs provide addresses. AL216 stores addresses internally. additional glue logic required interface SRAM AL216. interface AL216 16-bits wide.
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AL216 Preliminary
EEPROM Interface
AL216 provides three functions through EEPROM interface: system initialization, obtaining system status, reconfiguration system real time. 5.2.1 System Initialization EEPROM interface provided manufacturer provide preconfigured system their customers. Customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which accessed powerup reset. AL216 uses 24C02 serial EEPROM device (2048 bits organized bits organization EEPROM data shown Table addresses shown Table During start-up, EPBYPASS (AE20) tied low, AL216 will detect presence EEPROM. EEPROM present, AL216 will initialized attached management device ring. initialization command received, device will operate. reset held low, AL216's EEPROM interface will into high-impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. There ways that EEPROM reprogrammed: external parallel port, residing ring. reprogramming using parallel port, signal used hold RESET low; EEPROM interface will then high-impedance state. external device then program EEPROM through EEDIO EECLK pins. EEPROM address should same device with address (EEPROM) grounded. example, EEPROM device address device address 001.
Device Type Identifier Device Address
Figure
EEPROM Address Format
5.2.2 Write Cycle Timing write cycle started start-bit ended stop-bit. start-bit transition from high EEDIO when EECLK high. operation terminates when EEDIO goes from high when EECLK high. Following start condition, writing device must output address EEPROM. most significant four-bits EEPROM address device type identifier. These four bits 1010. EEPROM device address should device number. EECLK output from AL216. EEDIO input AL216 reading EEPROM output writing (See Figures 12.)
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EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
Start Stop
When accessing EEPROM, reset held before writing operation begin. typical write operation shown Figure
Device Address Stop
Start
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Write Operation
5.2.3 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1." typical read operation shown Figure
Start Device Address Start Device Address Stop
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Read Operation
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AL216 Preliminary
5.2.4 Reprogramming EEPROM Interface There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, forces EEDIO pins into high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices. alternate reconfiguring system input data directly into AL216. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's address must 0XX; AL216's address will 1XX. customer program AL216 EEPROM. read write timing same EEPROM. Because user reads well writes AL216, status register read from AL216. This will serve very useful tool diagnostics unmanaged switch.
AL216
Reset
EECLK EEDIO EEPROM Parallel Port
AL216
Reset EECLK EEDIO EEPROM
Reset AL216 EECLK EEDIO
EEPROM
Reset AL216 EECLK EEDIO
EEPROM
Figure
Programming EEPROM with Parallel Port
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5.2.5 EEPROM Note: specific bits register referenced notation, where register number number. Table shows EEPROM addresses cross-reference register/bit AL216. Addresses through configuring device. They downloaded AL216 during reset power-up. Address should programmed 0001 0001 0001 0100. Address indicates last address entry. static address used switch, address should programmed. Addresses used programming static address entry.
format address shown follows. YXXXXX represents: then XXXXX 5-bit individual port number. then XXXXX either trunk port represented followed 3-digit [trunk number, port, represented 11ZZZ; where don't care states.
Table EEPROM
ADDRESS Reserved ADDRESS 00YXXXXX ADDRESS 76-77 address[42:32] ADDRESS 78-79 address[31:16] ADDRESS 7A-7B address[15:0]
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Table EEPROM Address
EEPROM PHYSICAL ADDRESS DESCRIPTION System Configuration [15:8] System Configuration [7:0] System Configuration System Configuration 0001 0001 0001 0100 Reserved Vendor-Specific Snooping Port Configuration Monitored Source Host [47:32] Monitored Source Host [31:16] Monitored Source Host [15:0] Monitored Destination Host [47:32] Monitored Destination Host [31:16] Monitored Destination Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration AL216 REGISTER/BIT 00.15 00.8 00.7 00.0 01.15 01.0 02.15 02.0 03.15 03.0 04.15 04.0 05.15 05.0 06.15 06.0 07.15 07.0 08.15 08.0 09.15 09.0 0A.15 0A.0 0B.15 0B.0 0C.15 0C.0 0D.15 0D.0 0E.15 0E.0 0F.15 0F.0 10.15 10.0 11.15 11.0 12.15 12.0 13.15 13.0 14.15 14.0 15.15 15.0 16.15 16.0 17.15 17.0 18.15 18.0 19.15 19.0
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Table EEPROM Address (Continued)
EEPROM PHYSICAL ADDRESS DESCRIPTION Port Configuration Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Reserved Checksum Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment AL216 REGISTER/BIT 1A.15 1A.0 1B.15 1B.0 1C.15 1C.0 1D.15 1D.0 1E.15 1E.0 1F.15 1F.0 20.15 20.0 21.15 21.0 22.15 22.0 23.15 23.0 24.15 24.0 25.15 25.0 26.15 26.0 27.15 27.0 28.15 28.0 29.15 29.0 2A.15 2A.0 2B.15 2B.0 2C.15 2C.0 2D.15 2D.0 2E.15 2E.0 2F.15 2F.0 30.15 30.0 31.15 31.0 32.15 32.0 33.15 33.0
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Table EEPROM Address (Continued)
EEPROM PHYSICAL ADDRESS DESCRIPTION Port Trunk Port Assignment Control Control Reserved Last Entry Address Static Entry (Port Number) Static Entry (MAC [47:32]) Static Entry (MAC [31:16]) Static Entry (MAC [15:0]) Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry AL216 REGISTER/BIT 34.15 34.0 35.15 35.0 36.15 36.0
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Register Descriptions
Table Register Organization
REGISTER NUMBER System Configuration System Configuration System Configuration Reserved Reserved Vendor-Specific Status Port Monitoring Configuration Monitored Source Host (MAC address [47:32]) Monitored Source Host (MAC address [31:16]) Monitored Source Host (MAC address [15:0]) Monitored Destination Host (MAC address [47:32]) Monitored Destination Host (MAC address [31:16]) Monitored Destination Host (MAC address [15:0]) Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration DESCRIPTION
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Table Register Organization (Continued)
REGISTER NUMBER Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Control Control Reserved DESCRIPTION
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Table Register Organization (Continued)
REGISTER NUMBER Reserved System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Registers Indirect Resource Access Data Registers Indirect Resource Access Data Registers Indirect Resource Access Data Registers Checksum DESCRIPTION
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System Configuration Registers System Configuration Registers (registers global system configuration registers. option selected this register affects overall system operation.
Table System Configuration Register (Register
NAME CPUprst FloodCtl DESCRIPTION Present. This AL216, when detects that EEPROM absent. device will assume that present.
Flood Control. Control forwarding unicast frames with unknown destination received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Security Enforcement. Controls enforcement security ports with security turned Security programmed per-port basis (registers 1C). SecMgmt security ANDed operations. When both options turned security violation will disable port. Security Off. security violation secured port will change port state. Security security violation secured port will disable port. Address Table Entry Aging Control. Disable. table aging process will stopped. Enable. table aging process will running dynamically learned table entries. Table Convergence Control. Disable. device will communicate with other devices about locally learned table entries. Enable. device will slow background process periodically transfer locally learned table entries other devices learn. Spanning Tree Protocol Enable Control. Disable. BPDU frames received from network ports will treated regular broadcast frames. Enable. BPDU frames received from network ports will forwarded only port.
Port Incoming Frame Flow Monitoring Enable Control. Disable Enable Port Outgoing Frame Flow Monitoring Enable Control. Disable Enable
SecMgmt
AgeEN
TCNVG
STPEN
PInMon
POutMon
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Table System Configuration Register (Register (Continued)
NAME CPUcfgrdy DESCRIPTION Configuration Ready. This used AL216 when initialized CPU. Indicates that register file initialization completed CPU. Network Management Enable Control. Disable. device will generate events. Enable. device will generate events propagate onto ring. System Initialization Complete. This when initialization completed under initialization mode. unmanaged switch, this relevant. Reserved. Should zero. Load Balancing Method Trunking. Port-based load balancing. address based load balancing. Time Disable. Device will time frames that exceed MaxDelay. Device will time frames. Reserved. Should zero.
NetMgmt
InitDone
Reserved L2Trunk
TimeoutDis
Reserved
Table System Configuration Register (Register
15~8 NAME MaxAge MaxDelay DESCRIPTION Maximum Aging Time. Maximum aging time dynamically learned entries. Maximum Frame Delay. Maximum frame transition delay through switch. second. seconds. seconds. seconds. Maximum Storm Control. Sets number broadcast frames that accumulated each input frame buffer. frames. frames. frames. frames.
MaxStorm
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Table System Configuration Register (Register (Continued)
NAME SuperMAC DESCRIPTION Super MAC. When this option selected, controller will more agressive back algorithm. Disable. Device will perform IEEE standard exponential backoff algorithm when collision occurs. Enable. When collision occurs, AL216 will back three slots. Retry Excessive Collision. This enables retransmit after consecutive collisions. Layer Trunk Select. Selects position address trunk assignment. [1:0]. [3:2]. [5:4]. [7:6].
L2TbitSel
Table System Configuration Register (Register
15~11 NAME Reserved SlowAge DESCRIPTION
Reserved. Should zero.
Timing. Slows down normal address aging timer specified register MaxAge field. Normal aging. Slow down aging. Backpressure Control. Standard Control. Backpressure Port Rate (collision based). SGRAM Size. Selects either 8-Mbit/s 16-Mbit/s SGRAM SDRAM. Mbit/s SGRAM. Mbit/s SGRAM. Backpressure Control. This enables either collision carrier based backpressure flow control half-duplex mode. Carrier based. Collision based.
BpIPG64
IPG64
PRate SG16M
BPCOL
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Table System Configuration Register (Register (Continued)
NAME ETEnb DESCRIPTION External Table Enable. Disable Enable Table Size Selection. Multicast/Broadcast Frame Trapping. Forward Multicast/Broadcast Frames Only. Flow Control Type. Flow control multicast. Flow control broadcast.
ET16K
MCTrap FlowCtrlBC
Reserved Register (Register This register reserved Allayer's use. bits should 0001 0001 0001 0100. Reserved Register (Register This register reserved Allayer's use. bits should 0000 0000 0010 1000. Vendor-Specific Register (Register This register used program vendor-specific option. also used programming vendor-specific register location location operation status.
Table Vendor-Specific Register (Register
12~8 NAME PHYAD MClkSpd PortOrder PHYOpReg PHYSpBit PHYDxModeBit DESCRIPTION Address. Setting this will program MDIO address through MDIO Clock Speed. Setting this will reduce MDIO clock speed kHz. Port Order. Setting this will reverse ID/port number switch. PHY's Operation Register. PHY's Operation Status Register Number. Speed Bit. PHY's Data Rate Status Register Number. Duplex Mode Bit. PHY's Operating Duplex Mode Status Register Number.
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Port Monitoring Configuration Register (Register This register configures port monitoring. sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID MgOPID DESCRIPTION
Reserved. Should zero.
Monitored Port Monitoring Input Port Snooping port incoming frame flow. Monitoring Output Port Snooping port outgoing frame flow.
RMON Source Destination Registers (Registers These registers used RMON manager frame counting. RMON manager counts frames (destination) from (source) addresses stored these registers. 48-bit address programmed three separate registers. Source address stored registers destination address register
Table RMON Source Registers (Registers
REGISTER 15~0 15~0 15~0 NAME SRCMAC[47:32] SRCMAC[31:16] SRCMAC[15:0] DESCRIPTION Monitored Source Host Address. Monitored Source Host Address. Monitored Source Host Address.
Table RMON Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME DSTMAC[47:32] DSTMAC[31:16] DSTMAC[15:0] DESCRIPTION Monitored Destination Host Address. Monitored destination host Address. Monitored Destination Host Address.
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Port Configuration Registers (Registers Registers used configure local port. There port configuration registers port. Port port configuration uses registers port uses registers etc. Port Configuration Register Uplink this 6-bit link which assigns uplink port trunk. uplink local stack, format Port: [Dev_ID] [Port_ID] Trunk: [100] [Trunk_ID] CPU: [100000] Router: [100001] uplink remote stack, Stack: [101] [Stack_ID] remote stack will assign final port/trunk Note: port/trunk uplink, uplink should port/trunk frame with unlearned will then filtered.
Table Port Configuration Registers (Registers
15~10 NAME UpLinkID DESCRIPTION Uplink associated with port. 0xxyyy: Port with DEVID PID. 100xxn: Trunk with DEVID TID. 111xxx: port. Others: Reserved Trunk Member Port. Individual port. Trunk port.
Reserved. Should zero.
TMember
Reserved StormCTL
Broadcast Storm Control Enable. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection. Security control frames received from non-uplink ports. Security off. forwarding decision made about frames received from port will involve source address checking. Security Frames received from port with unknown source address with source address learned previously from another port will discarded.
Security
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Table Port Configuration Registers (Registers (Continued)
NAME CPUOn DESCRIPTION Port VLAN Membership. Non-member. Broadcast frames received from port will forwarded port. Member. Broadcast frames received from port will forwarded port addition other member ports specified VLAN register port (excluding source port). Learning Disable. from this port will learned. from this port will learned. Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-n-listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. source information incoming frames from will learned; incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. source information incoming frames from will learned; incoming frames will forwarded based switch routing decision; outing frames will transmitted PHY.
Reserved. Should zero.
LrnDis
PortST
Reserved
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Table Port Configuration Register (Register
15~12 NAME Reserved FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0] DESCRIPTION
Reserved. Should zero.
Flow Control Full-Duplex Enable. Flow Control Half-Duplex Enable. MDIO Configuration. 0001: Master mode management. 0010: Slave mode management. 0111: Force mode. MDIO Disable. Link This don't care MDIO disabled. When MDIO disabled, this will force port into link link down state. Link down. Link Mbit/s Full-Duplex. Mbit/s Half-Duplex. Mbit/s Full-Duplex. Mbit/s Half-Duplex.
MDIODis LinkUp
PrtMode100F PrtMode100H PrtMode10F PrtMode10H
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Port VLAN Registers (Registers These registers provide VLAN each port. VLAN worksheet provided Appendix
Table Port VLAN Registers (Registers
REGISTER Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 15~8 NAME Dev3Map DESCRIPTION Port VLAN Corresponding Port Port Device with Dev_ID Non-member port. Member port.
Dev2Map
Port VLAN Corresponding Port Port Device with Dev_ID Non-member port. Member port.
15~8
Dev1Map
Port VLAN Corresponding Port Port Device with Dev_ID Non-member port. Member port.
Dev0Map
Port VLAN Corresponding Port Port Device with Dev_ID Non-member port. Member port.
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Port Trunk Port Assignment Registers (Registers port trunk port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port worksheet provided Appendix
Table Port Trunk Port Assignment Registers (Registers
PORT NUMBER REGISTER
Table Registers Descriptions
15~14 13~12 11~10 NAME Trunk Trunk Trunk Trunk Trunk Trunk Trunk Trunk DESCRIPTION Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port 1,10: Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port
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Control Register (Register Recommended Setting: 0000 0000 0000 0000 This register along with Register sets "route" bit-map from device this device. Each DxRoute five bits standing possible five segments RoX-II ring. right-most segment driven device following physical connection from right left. Devices don't have connected sequence according device bit-map means that route will travel that segment.
Table Control Register (Register
14~10 NAME Reserved D2Route D1Route D0Route DESCRIPTION
Reserved. Should zero.
Device Route. Route Selection from Device this device. Device Route. Route Selection from Device this device. Device Route. Route Selection from Device this device.
Control Register (Register Recommended Setting: 0000 0000 0000 0000
Table Control Register (Register
12~10 NAME OneDev Legacy D3GigaOn Reserved HiRoute D3Route DESCRIPTION Internal Loop Back Enable. Disable Enable Supports Legacy AL300A Protocol. Disable Enable Device Gigabit Device. Disable Enable
Reserved. Should zero.
Route Selection from AL3000 this Device. Route Selection from Device this Device.
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AL216 Preliminary
Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initialized device. Device ready programmed CPU. CheckSum Error. Checksum correct. EEPROM checksum error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Traffic Counter.
Reserved. Should zero.
CheckSumEr
10~7
SGRAMinit SRAMinit REGinit Traffic Counter Reserved Chip
AL216 Chip 0111: AL216
Port Operation Status Registers (Register Registers status indication per-port basis. These read-only registers. Port port status register port register port register
Table Port Operation Status Registers (Register
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation Flow Control. port mode ([1:0]) Pause disable. Pause enable. port mode ([1:0]) Backpressure based CRS. Backpressure based collision. DESCRIPTION
PHYError
SViolation
FlowCtrl
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AL216 Preliminary
Table Port Operation Status Registers (Register (Continued)
NAME Stormed DESCRIPTION Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. False Carrier Status. Normal False carrier experienced. Transmit Queue Underflow Status. Normal Underflow experienced. Frame Time Out. Normal Underflow experienced. Port Operating Mode. 10Mb half-duplex. 10Mb full-duplex. 100Mb half-duplex. 100Mb full-duplex.
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
CRSLoss
FalseCRS
Underflow
TimeOut
Port Mode
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Indirect Resource Command Register (Register This register used managing resource switch.
Table Indirect Resource Command Register (Register
NAME CmdDone Command Done. command. Done command. Read/Write Operation Command. Read operation. Write operation. Type Accessed Resource. 000: register. 001: EEPROM 010: SGRAM 011: On-chip tables (I): Read: sequential read. Write: address learn. 100: On-chip Tables (II): Read: address search. Write: address delete. 101: Reserved 110: Reserved 111: Reserved External Read. ResType Operation On-chip address table sequential read. Off-chip address table sequential read. Resource Address. address entry within accessed resource. DESCRIPTION
Operation
13~11
ResType
ExtRD
ResAddr
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Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData0 DESCRIPTION Indirect Resource Access Data.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData1 DESCRIPTION Indirect Resource Access Data.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData2 DESCRIPTION Indirect Resource Access Data.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData3 DESCRIPTION Indirect Resource Access Data.
Table Checksum (Register
15~8 NAME CheckSum Reserved EEPROM Checksum. DESCRIPTION
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Management Registers Table Summary Management Registers (MR)
REGISTER ADDRESS 8~19 22~27 SYMBOL MR8~MR19 MR20 MR21 MR22~MR27 MR28 MR29 MR30 MR31 Control Status Identifier Identifier Auto-negotiation Advertisement Auto-negotiation Link Partner Ability (base page, next page) Auto-negotiation Expansion Next Page Transmit Reserved FIFO Configuration RXER Counter Reserved Device Specific (status) Device Specific (100 Mbit/s control) Device Specific Mbit/s control) Quick Status NAME DEFAULT (HEX CODE) 3000 7849 0180 BB80 01E1 0000 0000 0000 0000 2080 0000
Note: following tables, letters type column indicate; Read, Write, Latch High indicates Applicable.
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Table Control Register Descriptions
NAME SW_RESET TYPEa DESCRIPTION Reset. Setting this will reset AL216. registers will their default state. This selfclearing. default Loopback. When this data transmission will take place media. receive data will ignored. loopback signal path will contain circuitry including, PMD. auto-negotiation must turned off, then loopback initiated. Transmit data start after loopback initiated. default value Speed Selection. value this reflects current speed operation Mbit/s; Mbit/s). This will only affect operating speed when auto-negotiation enable (register disabled (0). This ignored when auto-negotiation enabled (register 12). This ANDed with SPEED signal (A18). Auto-negotiation Enable. auto-negotiation process will enabled setting this default state This ANDed with AUTO_EN (D17) during power-up reset. Power-down. AL216 placed low-power state setting this both Mbit/s transceiver Mbit/s transceiver will powered down. While power-down state, AL216 will respond management transactions. default state Isolate. When this outputs will brought high-impedance state. default state Restart Auto-negotiation. Normally, auto-negotiation process started power-up. process restarted setting this default state NWAYDONE (register reset when this goes This self-cleared when auto-negotiation restarts. Duplex Mode. This reflects mode operation full duplex; half duplex). This ignored when auto-negotiation enable (register enabled. default state This ORed with FULL_DUP (B18).
LOOPBACK
SPEED100
NWAY_EN
PWRDN
ISOLATE
REDONWAY
FULL_DUP
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Table Control Register Descriptions (Continued)
NAME COLTST Reserved TYPEa DESCRIPTION Collision Test. When this AL216 will assert internal signal response RTX_EN. Reserved. bits will read
read, write, latch high, applicable.
Table Status Register Descriptions
NAME T4ABLE TYPEa DESCRIPTION 100Base-T4 Ability. This will always able. Able 100Base-TX Full-Duplex Ability. This will always able. Able 100Base-TX Half-Duplex Ability. This will always able. Able 10Base-T Full-Duplex Ability. This will always able. Able 10Base-T Half-Duplex Ability. This will always able. Able Reserved. bits will read Suppress Preamble. When this indicates that AL216 accepts management frames with preamble suppressed. Auto-negotiation Complete. When this indicates auto-negotiation process been completed. contents registers MR4, MR5, MR6, valid. default value This reset when auto-negotiation started. Remote Fault. When this indicates remote fault been detected. This will remain until cleared reading register. default Auto-negotiation Ability. When this indicates ability perform auto-negotiation. value this always
TXFULDUP
TXHAFDUP
ENFULDUP
ENHAFDUP
10~7
Reserved NO_PA_OK
NWAYDONE
REM_FLT
NWAYABLE
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Table Status Register Descriptions (Continued)
NAME LSTAT_OK TYPEa DESCRIPTION Link Status. When this indicates valid link been established. This latching function. link failure will cause clear stay cleared until been read management interface. Jabber Detect. This will whenever jabber condition detected. will remain until read, jabber condition longer exists. Extended Capability. This indicates that AL216 supports extended register (MR2 beyond). will always read
JABBER
EXT_ABLE
read, write, latch high, applicable.
Table MR2, MR3-PHY Identification Registers
NAME TYPEa 15~0 OUI[3:18] Organizationally Unique Identifier. third through twenty-fourth assigned manufacturer IEEE placed MR2, bits 15-0 MR3, bits 15-10. value bits 15:0 0180h. 15~10 OUI[19:24] MODEL[5:0] VERSION [3:0] Organizationally Unique Identifier. remaining bits OUI. value bits 15-10 1Dh. Model Number. Six-bit model number device. model number 38h. Revision Number. value present revision number DESCRIPTION
read, write, latch high, applicable.
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AL216 Preliminary
Table MR4-Auto-negotiation Advertisement Register
NAME NEXT_PAGE TYPEa DESCRIPTION Next Page. next page function activated setting this This will allow exchange additional data. Data carried optional next pages information. Acknowledge. This acknowledge from link code word. Remote Fault. When AL216 indicates link partner remote fault condition. Pause. When indicates that AL216 wishes exchange flow control information with link partner. 100Base-T4. This should always 100Base-TX Full-Duplex. written auto-negotiation will advertise that AL216 capable 100Base-TX full-duplex operation. 100Base-TX. written auto-negotiation will advertise that AL216 capable 100Base-TX operation. 10Base-T Full-Duplex. written auto-negotiation will advertise that AL216 capable 10Base-T fullduplex operation. 10Base-T. written auto-negotiation will advertise that AL216 capable 10Base-T operation. Selector Field. Reset with value 00001 IEEE 802.3.
12~10
REM_FAULT PAUSE
100BASET4 100BASET_FD
100BASETX
10BASET_FD
10BASET SELECT
read, write, latch high, applicable.
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Table MR5-Auto-negotiation Link Partner Ability (Base Page) Register
NAME LP_NEXT_PAGE TYPEa DESCRIPTION Link Partner Next Page. When this indicates that link partner wishes engage next page exchange. Link Partner Acknowledge. When this indicates that link partner successfully received least three consecutive consistent bursts. Remote Fault. When this indicates that link partner fault. Technology Ability Field. This field contains technology ability link partner. These bits similar bits defined register (see Table 53). Selector Field. This field contains type message sent link partner. IEEE 802.3 compliant link partners, this field should read 00001.
LP_ACK
12~5
LP_REM_FAULT LP_TECH_ABILITY
LP_SELECT
read, write, latch high, applicable.
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Table MR5-Auto-negotiation Link Partner Ability (Next Page) Register
NAME LP_NEXT_PAGE TYPEa DESCRIPTION Next Page. When this logic indicates that this last page transmitted. logic indicates that additional pages will follow. Acknowledge. When this logic indicates that link partner successfully received partner's link code word. Message Page. This used NEXT _PAGE function differentiate message page (logic from unformatted page (logic Acknowledge This used NEXT_PAGE function indicate that device ability comply with message (logic (logic Toggle. This used arbitration function ensure synchronization with link partner during next page exchange. Logic indicates that previous value transmitted link code word logic Logic indicates that previous value transmitted link code word logic Message/Unformatted Code Field. With these bits, there 2048 possible messages. Message code field definitions described annex IEEE 802.3u standard.
LP_ACK
LP_MES_PAGE
LP_ACK2
LP_TOGGLE
10~0
read, write, latch high, applicable.
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Table MR6-Auto-negotiation Expansion Register
15~5 NAME Reserved PAR_DET_FAULT TYPEa R/LH DESCRIPTION
Reserved. Should zero.
Parallel Detection Fault. When this indicates that fault been detected parallel detection function. This fault more than technology detecting concurrent link conditions. This only cleared reading this register. Link Partner Next Page Able. When this indicates that link partner supports next page function. Next Page Able. This indicating that this device supports NEXT_PAGE function. Page Received. When this indicates that NEXT_PAGE been received. Link Partner Auto-negotiation Capable. When this indicates that link partner auto-negotiation capable.
LP_NEXT_PAGE_ABLE
NEXT_PAGE_ABLE
PAGE_REC
R/LH
LP_NWAY_ABLE
read, write, latch high, applicable.
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AL216 Preliminary
Table MR7-Next Page Transmit Register
NAME NEXT_PAGE TYPEa DESCRIPTION Next Page. This indicates whether this last next page transmitted. When this indicates that this last page. When this indicates there additional next page. Acknowledge. This acknowledge from link code word. Message Page. This used differentiate message page from unformatted page. When this indicates unformatted page. When this indicates formatted page. Acknowledge This used next page function indicate that device ability comply with message. When this indicates device cannot comply with message. When this indicates device will comply with message. Toggle. This used arbitration function ensure synchronization with link partner during next page exchange. This will always take opposite value toggle previously exchanged link code word. logic previous value transmitted link code word logic previous value transmitted link code word initial value toggle first next page transmitted inverse value base link code word, assume value Message/Unformatted Code Field. With these bits, there 2048 possible messages. Message code field definitions described annex IEEE 802.3u standard.
MESSAGE
ACK2
TOGGLE
10~0
read, write, latch high, applicable.
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AL216 Preliminary
Table MR20-LED FIFO Configuration
15~11 NAME Reserved AUTO_MODE TYPEa Reserved Automatic Mode. Disable bicolor automatic mode, when written When bicolor automatic mode disabled, forced bicolor mode entered such that register bits nine eight activated. When automatic mode (default), link will whenever activity high. Default This only valid bicolor mode. Reserved Link Flash. Force link flash high/low time, when written Default This only valid when bicolor mode with automatic mode disabled. FDUPLED Force FDUPLED when written Default FDULED Off. Force FDUPLED off, when written (FDUPLED overrides this). Default Reserved. This must Reserved. This must Force Speed Force speed when written Default Force Speed Off. Force speed off, when written (speed overrides this). Default Force LINKLED Force link when written Default Force LINKLED Off. Force link when written (LINKLED overrides this). Default DESCRIPTION
Reserved LINKLED_FLASH
FDUPLED_ON FDUPLED_OFF Reserved Reserved SPEEDLED_ON SPEEDLED_OFF LINKLED_ON LINKLED_OFF
read, write, latch high, applicable.
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AL216 Preliminary
Table MR21-RXER Counter
NAME COUNT_MODE TYPEa DESCRIPTION Counter Mode. When this puts this register 16-bit counter mode. When puts this register eight-bit counter mode. This reset cannot read. 16-Bit Counter Mode 15~0 RX_ER16 Counter Value 16-Bit Mode. When 16-bit counter mode, these bits maintain count RXERs (receive errors). reset read operation. 8-Bit Counter Mode 15~12 DIS_CNT Disconnect Count. When eight-bit mode, these bits contain count disconnect events (Link Unstable 802.3 Section 27.3.1.5.1). They reset read operation. False Carrier Count. When eight-bit mode, these bits contain count false carrier events (802.3 Section 27.3.1.5.1). reset read operation. Counter Value 8-Bit Mode. When eight-bit counter mode, these bits maintain count RXERs (receive errors). reset read operation.
11~8
FALSE_CNT
RX_ERR8
read, write, latch high, applicable.
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AL216 Preliminary
Table MR28-Device-Specific Register (Status Register)
15~9 NAME UNUSED BAD_FRM TYPEa R/LH Unused. Read Frame. this indicates frame been received without SFD. This only valid Mbit/s mode. This latching high will only clear after been read device been reset. Code Violation. When this indicates Manchester code violation occurred. error code will output RRXD lines. Refer Table detailed description RRXD error codes. This only valid Mbit/s mode. This latching high will only clear after been read device been reset. Auto-polarity Status. When register three this indicates AL216 detected corrected polarity reversal twisted pair. APF_EN (register set, reversal will corrected inside AL216. This valid Mbit/s operation. Disconnect. this indicates disconnect. This will latch high until read. This only valid Mbit/s mode. Unlocked. Indicates that scrambler lost lock. This will latch high until read. This only valid Mbit/s mode. Error Status. Indicates false carrier. This will latch high until read. This only valid Mbit/s mode. Force Jam. This will latch high until read. This only valid Mbit/s mode. Link 100. This bit, when indicates Mbit/s transceiver operational. Link This bit, when indicates Mbit/s transceiver operational. DESCRIPTION
CODE
R/LH
DISCON
R/LH
UNLOCKED
R/LH
RXERR_ST FRC_JAM LNK100UP LNK10UP
R/LH R/LH
read, write, latch high, applicable.
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AL216 Preliminary
Table MR29 Device-Specific Register (100 Mbit/s Control)
NAME LOCALRST TYPEa DESCRIPTION Management Reset. This local management reset bit. Writing logic this will cause lower registers registers reset their default values. This self-clearing. Generic Reset This register used manufacture test only. Generic Reset This register used manufacture test only. Mbit/s Transmitter Off. When this forces TPIP TPIN- high. This defaults Blinking. This register, when enables blinking. This ORed with BLINK_LED (C18). Default Carrier Sense Select. RCRS_DV will asserted receive only when this this logic RCRS_DV will asserted receive transmit. Link Error Indication. When this link error code will reported RRXD[1:0] AL216 when RRX_ER asserted MII. will disable this function. Frame Error Indication Enable. When this frame error code, which indicates that scrambler locked, will reported receive data outputs AL216 when RRX_ER asserted RMII. When this will disable this function. Pulse Stretching. When this activity collision output signals will stretched between approximately ms-84 this will disable this feature. default state this Encoder/Decoder Bypass. This mode longer supported; keep this (default).
RST1 RST2 100_OFF
LED_BLINK
CRS_SEL
LINK_ERR
FRM_ERR
PULSE_STR
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