201A072 225A837 Other Read/Write Cycle Times (-55°C 125°C) Number
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256K Radiation Hardened Static
201A072 225A837
Other Read/Write Cycle Times (-55°C 125°C) Number 5962H99541 Asynchronous Operation CMOS Compatible Single ±10% Power Supply Operating Power Packaging Options 40-Lead Dual Flat Pack (0.855" 0.710")
Radiation Fabricated with Bulk CMOS Process Total Dose Hardness through 1x106 rad(Si) Neutron Hardness through 1x1014 N/cm2 Dynamic Static Transient Upset Hardness through 1x109 rad(Si)/s Soft Error Rate 1x10-11 Upsets/Bit-Day Dose Rate Survivability through 1x1012 rad(Si)/s Latchup Free
General Description
256K radiation hardened static composed 128K SRAM memory assembled single, double-sided ceramic substrate. Each high performance 131,072 word 8-bit static random access memory with industry-standard functionality. fabricated with SYSTEMS' radiation hardened technology designed systems operating radiation environments. operates over full military temperature range requires single ±10% power supply. available with either CMOS compatible I/O. Power consumption typically less than mW/MHz operation, less than power disabled mode. read operation fully asynchronous, with associated typical access time nanoseconds. SYSTEMS' enhanced bulk CMOS technology radiation hardened through advanced proprietary design, layout, process hardening techniques.
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Functional Diagram Bottom SRAMs
Top/Bottom Decoder Note: package leads common bottom SRAM devices except bottom SRAM SRAM.
Block Address Decoder
Side/Block ((256 Memory Cell Array
Address Decoder
Word Input/Output Column Address Decoder
DQ0-DQ7 A4-A8
Signal Definitions
0-16
Address input pins that select particular eight-bit word within memory array. Bi-directional data pins that serve data outputs during read operation data inputs during write operation. Negative chip select, when level, allows normal read write operation. When high level, forces SRAM precharge condition, holds data output drivers high impedance state disables data input buffers only. this signal used, must connected GND.
Negative write enable, when level, activates write operation holds data output drivers high impedance state. When high level, allows normal read operation. Negative output enable, when high level holds data output drivers high impedance state. When level, data output driver state defined this signal used must connected GND. Chip enable, when high level allows normal operation. When level, forces SRAM precharge condition, holds data output drivers high impedance state disables input buffers except input buffer. this signal used, must connected VDD.
(Bottom) (Top)
Truth Table
Mode Write1 Read1 Write2 Read2 Standby Standby(3) Inputs(1),(2) High High High High High High High High High High High High Data-In Data-Out Data-In Data-Out High-Z High-Z Power Active Active Active Active Standby Standby Notes: don't care inputs VIH. When high, high-Z. dissipate minimum amount standby power when standby mode: VDD. other input levels float.
Absolute Maximum Ratings
Applied Conditions(1) Minimum Maximum
Storage Temperature Range (Ambient) Operating Temperature Range (Tcase) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering sec) Electrostatic Discharge Sensitivity(4)
Notes:
-70°C -55°C -0.5 -0.5 -0.5
+150°C +125°C +7.0 VDD+ VDD+
+250°C (Class
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. voltages with reference module ground leads. Maximum applied voltage shall exceed +7.0 Guaranteed design; tested. Class defined MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol Parameters(1) Minimum Maximum Units
Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" CMOS Input Logic "Low" Input Logic "High" CMOS Input Logic "High"
Note:
+4.5 -0.3 +3.5 +2.0
+5.5 +125 +1.5 +0.8
Volt Volt Celsius Volt Volt
1)All voltages referenced GND.
Power Sequencing
Power shall applied device only following sequences prevent damage excessive currents: Power-Up Sequence: GND, VDD, Inputs Power-Down Sequence: Inputs, VDD,
Electrical Characteristics
Limits Minimum Maximum 0.05
Test
Symbol
Test Conditions(1)
Device Type
Units
Supply Current (Cycling Selected)
IDD1
FMAX 1/tAVAV(min) (Except GND) Engineering Level) GND) Engineering Level Output Load FMAX 1/tAVAV(min) (Except Engineering Level) Engineering Level (Except Engineering Level) Engineering Level (Except Engineering Level) Engineering Level
Supply Current (Cycling De-Selected) Supply Current (Standby)
IDD2
IDD3
Data Retention Current
VDD= IOH= -200 IOL=
High Level Output Voltage Level Output Voltage Data Retention Voltage High Level Input Voltage Level Input Voltage Input Leakage Output Leakage
IILK IOLK
CMOS CMOS
VOUT Design/ Verified Characterization Design/ Verified Characterization
CMOS (Except Engineering Level) CMOS Engineering Level CMOS (Except Engineering Level) CMOS Engineering Level
Cout
Notes:
Typical operating conditions: -55°C Tcase +125°C; unless otherwise specified. high, high, must occur while address transitions. Guaranteed design verified periodic characterization.
Output Load Circuit
2.8V
Read Cycle Timing Characteristics(1)
Minimum Maximum Minimum
Test
Symbol
Device Type CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS
Limits Units
Read Cycle Time
tAVAV
Address Access Time
tAVQV
Maximum
Chip Select Access Time
tSLQV
Maximum
Chip Enable Access Time
tEHQV
Maximum
Output Enable Access Time Chip Select Output Active Chip Enable Output Active Output Enable Output Active Output Hold After Address Change Chip Select Output Disable Chip Disable Output Disable Output Enable Output Disable Chip Select1 Chip Select2 Chip Select2 Chip Select1(3)
tGLQV tSLQX tEHQX tGLQX tAHQX tSHQZ tELQZ tGHQZ tS1HS2L tS2HS1L
Maximum Minimum Minimum Minimum Minimum Maximum Maximum Maximum Minimum Minimum
Notes: Test conditions: input switching levels VIL/VIH V/VDD (CMOS), VIL/VIH (TTL), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading derate access times 0.02 ns/pF (typical). -55°C Tcase +125°C; unless otherwise specified. Cycle time individual die. Parameter guaranteed tested. Parameter tSLQX tSHQZ; both these parameters tested.
Write Cycle Timing Characteristics(1)
Minimum Maximum Minimum
Test
Symbol
Device Type CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS, X41, CMOS, CMOS CMOS CMOS CMOS
Limits Units
Write Cycle Time
tAVAV
Address Setup Write
tAVWH
Minimum
Chip Select Write
tSLWH
Minimum
Chip Enable Write
tEHWH
Minimum
Write Pulse Width Access Time
tWLWH
Minimum
Data Setup Write Data Hold After Write Address Setup Start Write Address Hold After Write Output Active After Write
tDVWH tWHDX tAVWL tWHAX tWHQX
Minimum Minimum Minimum Minimum Minimum
Write Enable Output Disable
tWLQZ
Maximum
Write Disable Pulse Width
tWHWL
Minimum
Note:
Test conditions: input switching levels VIL/VIH V/VDD (CMOS), VIL/VIH (TTL), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading -55°C Tcase +125°C; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
tAXQX
tSLQX tEHQV
tSHQZ
tEHQX tGLQV
tELQZ
tGLQX
Data
tGHQZ
Valid Data
High Impedance
Write Cycle Timing Diagram
tAVAV
Address
Valid Address tAVWH tSLWH tWHAX
tEHWH tWLWH
tAVWL
Data
tWLQZ High Impedance tDVWH
tWHWL tWHQX
High Impedance
tWHDX
Data
High Impedance
Valid Data
High Impedance
Select1 Select2 Timing Diagram
tS1HS2L
tS2HS1L
Dynamic Electrical Characteristics
Read Cycle asynchronous operation, allowing read cycle controlled address, chip select S2), chip enable (refer Read Cycle Timing diagram). perform valid read operation, both chip select output enable must chip enable write enable must high. output drivers controlled independently signal. Consecutive read cycles executed with held continuously low, with held continuously high, toggling addresses. address-activated read cycle, must valid prior coincident with activating address edge transition(s). amount toggling skew between address edge transitions permissible; however, data outputs will become valid tAVQV time following latest occurring address edge transition. minimum address activated read cycle time tAVAV When operated minimum address-activated read cycle time, data outputs will remain valid until tAXQX time following next sequential address transition. control read cycle with addresses must valid prior coincident with enabling edge transition. Address edge transitions occur later than specified setup times however, valid data access time will delayed. address edge transition, that occurs during time when low, will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tSHQZ time following disabling edge transition. control read cycle with addresses must valid prior coincident with enabling edge transition. Address edge transitions occur later than specified setup times however, valid data access time will delayed. address edge transition that occurs during time when high will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tELQZ time following disabling edge transition.
Write Cycle write operation synchronous with respect address bits, control governed write enable (W), chip select S2), chip enable edge transitions (refer Write Cycle Timing diagrams). perform write operation, both must low, must high. Consecutive write cycles performed with held continuously low, held continuously high. least control signals must transition opposite state between consecutive write operations. write mode controlled three different control signals: three modes control similar except controlled modes actually disable during write recovery pulse. Only controlled mode shown table diagram previous page simplicity. However, each mode control provides same write cycle timing characteristics. Thus, some parameter names referenced below shown write cycle table diagram, indicate which control control switches high low. write data into RAM, must held must held high least tWLWH /tSLSH /tEHEL time. amount edge skew between signals tolerated control signals initiate terminate write operation. consecutive write operations, write pulses must separated minimum specified tWHWL /tSHSL /tELEH time. Address inputs must valid least tAVWL /tAVSL /tAVEH time before enabling W/S1 S2/E edge transition, must remain valid during entire write time. valid data overlap write pulse width time tDVWH /tDVSH /tDVEL, address valid write time tAVWH /tAVSH /tAVEL also must provided during write operation. Hold times address inputs data inputs with respect disabling W/S1 S2/E edge transition must minimum tWHAX /tSHAX /tELAX time tWHDX /tSHDX /tELDX time, respectively. minimum write cycle time tAVAV.
Radiation Characteristics
Total Ionizing Radiation Dose SRAM will meet stated functional electrical specifications over entire operating temperature range after total ionizing radiation dose 1x106 rad(Si). electrical timing performance parameters will remain within specifications after rebound 125°C extrapolated years operation. Total dose hardness assured wafer level testing process monitor transistors product using X-ray Co60 radiation sources. Transistor gate threshold shift correlations have been made between X-rays applied dose rate 1x105 rad(Si)/min 25°C gamma rays (Cobalt source) ensure that wafer level X-ray testing consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation SRAM capable writing, reading, retaining stored data during after exposure transient ionizing radiation pulse duration 1x109 rad(Si)/s, when applied under recommended operating conditions. ensure validity specified performance parameters before, during, after radiation (timing degradation during transient pulse radiation 10%), stiffening capacitance placed package between package (chip) with inductance between package (chip) stiffening capacitance kept minimum. there operatethrough valid stored data requirements, typical de-coupling capacitors should mounted circuit board close possible each device. SRAM will meet functional electrical specification after exposure radiation pulse duration 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that current conducted during pulse inputs, outputs, power supply significantly exceed normal operating levels. application design must accommodate these effects. Neutron Radiation SRAM will meet functional timing specification after total neutron fluence 1x1014 cm-2 applied under recommended operating storage conditions. This assumes equivalent neutron energy MeV. Soft Error Rate SRAM soft error rate (SER) performance <1x10-11 upsets/bit-day, under recommended operating conditions. This hardness level defined Adams worst case cosmic environment. Latchup SRAM will latch above radiation exposure conditions when applied under recommended operating conditions.
Radiation Hardness Ratings (1),(2)
Symbol
Characteristics
Conditions
Minimum
Maximum
Units
RPRU SEU1 SEU2
Total Dose Prompt Dose Upset Survivability Single Event Upset Single Event Upset Neutron Fluence Single Event Induced Latchup
MIL-STD-883, 1019.5 Condition Pulse Width Tcase 25°C 125°C Pulse Width Tcase 125°C -55°C Tcase 80°C -55°C Tcase 125°C
rad(Si) rad(Si)/s rad(Si)/s Upsets/Bit-Day Upsets/Bit-Day N/cm2 Immune
-55°C Tcase 125°C
Notes: Measured room temperature unless otherwise stated. Verification test approved test plan. Device electrical characteristics guaranteed post irradiation levels 25°C. worst case particle environment, geosynchronous orbit, 0.025'' aluminum shielding. Specification using CREME code upset rate calculation method with thickness. Immune MeV/mg/cm
Tester Timing Characteristics
Configuration
CMOS Configuration
Input Levels*
VDD-
Output Sense Levels
VDD- High
High
VDD- High
High
High
High
*Input rise fall times
Radiation Hardness Assurance
SYSTEMS provides superior quality level radiation hardness assurance products. excellent product quality sustained qualified operation which requires process control with statistical process control, radiation hardness assurance procedures rigid computer controlled manufacturing operation monitoring tracking system. SYSTEMS technology built with resistance radiation effects. product designed exhibit fails/bit-day worst case geosynchronous orbit under worst case operating conditions. Total dose hardness assured irradiating test structures every total dose exposure with Cobalt testing performed quarterly lots assure product meeting radiation hardness requirements.
Reliability
SYSTEMS' reliability starts with overall product assurance system that utilizes quality system involving employees including operators, process engineers product assurance personnel. extensive wafer acceptance methodology, using in-line electrical data well physical data, assures product quality prior assembly. continuous reliability monitoring program evaluates every wafer level, utilizing test structures well product testing. Test structures placed every wafer, allowing correlation checks within-wafer, wafer-to-wafer, from lot-to-lot. Reliability attributes CMOS process characterized testing both irradiated non-irradiated test structures. evaluations allow design model process changes incorporated specific failure mechanisms, i.e., carriers, electromigration, time dependent dielectric breakdown. These enhancements operation create more reliable product. process reliability further enhanced accelerated dynamic life tests both irradiated non-irradiated test structures. Screening testing procedures from customer followed qualify product. final periodic verification quality reliability product validated (Technology Conformance Inspection).
Screening Levels
SYSTEMS screen levels meet full compliant space applications. limited performance evaluation situations, SYSTEMS offers engineering screen level.
Standard Screening Procedure
Level
Flow
Comments
Wafer Acceptance Serialization Destructive Bond Pull Internal Visual Temperature Cycle Constant Acceleration PIND Radiography Electrical Test Dynamic Burn-In Electrical Test Static Burn-In Final Electrical Fine Gross Leak External Visual
Sample
Sample
Alternate Method Used Traceability MIL-STD-883, 2010
125°C, Hours Meets Group Fallout MIL-STD-883, 2009
Burn-In Circuit
Stress Methodology
There methods burn-in defined. "Static" burn-in, possible addresses written with logic half burn-in duration logic remaining half. "Dynamic" burn-in, possible addresses written with alternating high data. pins specified static dynamic burn-in lists driven through individual series resistors (1.6K ±10%). burn-in circuit diagram shown right. Voltage Levels Vin(0): level programmed signals High level programmed signals (-0% +10%) pins tied this level Float pins tied this level (±10%) 1.6K (±10%)
256K SRAM
Listing dynamic burn-in listing shown right. square wave, MHz.
Input
Signal F/16 F/32 F/64
Input
Signal F/128 F/256 F/512 F/1024 F/2048 F/4096
Input
Signal F/8192 F/16384 F/32768 F/65536 F/131072 F/262144
Input
Signal F/524288 First Half Second Half First Half Second Half
Packaging
256K SRAM offered custom 40-lead dual packages constructed multilayer ceramic (AI2O3) feature internal power ground planes. Optional capacitors mounted package maximize supply noise decoupling increase board packing density. These capacitors attach directly internal package power ground planes. This design minimizes resistance inductance bond wire package, both which critical transient radiation environment. pins must connected either VDD, active driver prevent charge build radiation environment. connect.)
40-Lead Dual Flat Pack Pinout
View
40-Lead Dual Flat Pack
Lead Lead
Ordering Information
256K CMOS Memory Device Number 201A072 256K Memory Device Number 225A837
(1),
Lead
Lead
Package Designation 1=40-Lead
Speed Designation Engineering Screen
Screen Designation 1=QML 3=Engineering 4=QML 5=QML 7=Customer Specific
A=1.635 B=.885 .008 C=.710 .008
D=.245 .015 E=.135 F=.164 G=.030
H=.775 J=.048 K=.045
SYSTEMS reserves right make changes products herein improve reliability, function design. SYSTEMS does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others.
Notes:
Part mark device specification. ``QML'' required device specification. Dimensions inches. Lead cross-section: .008"W .006" lead pitch: .025", lead plating: uin, over uin, over Kovar. Unless otherwise specified, tolerances .005." Cleared Public Domain Release ©2001 SYSTEMS, Rights Reserved
SYSTEMS 9001, AS9000, 14001, Level Company 9300 Wellington Road, Manassas, 20110-4122 866-530-8104 0039_256K_8_SRAM.ppt
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
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