AHA3520 MBytes/sec ALDC Data Compression Coprocessor PS3520_
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AHA3520
MBytes/sec ALDC Data Compression Coprocessor
PS3520_1098
subsidiary Comtech Telecommunications Corporation
2345 Hopkins Court
Pullman 99163
tel: 509.334.1000
fax: 509.334.9000
www.aha.com
Table Contents
Introduction Conventions, Notations Definitions. Features Applications Functional Description. 1.4.1 Port Port Interfaces 1.4.2 FIFO Operation. 1.4.3 Data Expansion During Compression Compression Operation Compression Pass Through Compression Decompression Operation Decompression Pass Through Decompression Decompression Output Disabled Mode. Microprocessor Interface Register Access Microprocessor Interface 4.1.1 Interrupts 4.1.2 Resets Register Access. Pausing Port Port Configuration. Register Description Status (STAT0) Port Configuration (ACNF0) Port Configuration (ACNF1) Port Configuration (BCNF0) Port Configuration (BCNF1) Identification (ID) Port Polarity (APOL). Port Polarity (BPOL). Port Transfer Count (ATC0, ATC1, ATC2, ATC3) 6.10 Port Transfer Count (BTC0, BTC1, BTC2, BTC3) 6.11 Error Status (ERRS) 6.12 Interrupt Status (INTS) 6.13 Command (CMND) 6.14 Transfer Size (TS0, TS1, TS2, TS3) 6.15 Data Disabled Count (DDC0, DDC1, DDC2, DDC3). 6.16 error mask (EMSK) 6.17 Interrupt Mask (IMSK) Signal Descriptions Microprocessor Interface Port Interface Port Interface Pinout Electrical Specifications Absolute Maximum Ratings. Recommended Operating Conditions Specifications 10.0 Timing Specifications 11.0 Packaging 12.0 Ordering Information
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12.1 Available Parts. 12.2 Part Numbering 13.0 Related Technical Publications
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PS3520_1098
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Functional Block Diagram Pinout Clock Timing Reset Timing Almost Full/Almost Empty Timing Processor Read Timing, MMODE Processor Write Timing, MMODE Processor Read Timing, MMODE Processor Write Timing, MMODE Port Timing, Four Edge, Master Mode Port Timing, Four Edge, Slave Mode Port Timing, Burst, Master Mode Port Timing, Burst, Slave Mode Peripheral Access Read Timing, MMODE Peripheral Access Write Timing, MMODE Peripheral Access Read Timing, MMODE Peripheral Access Write Timing, MMODE AHA3520 PQFP Package Specifications
PS3520_1098
subsidiary Comtech Telecommunications Corporation
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Microprocessor Interface Control Signals Port Interface Signals Port Interface Signals Clock Timing Reset Timing Almost Full/Almost Empty Timing Processor Read Timing, MMODE Processor Write Timing, MMODE Processor Read Timing, MMODE Processor Write Timing, MMODE Port Timing, Four Edge, Master Mode Port Timing, Four Edge, Slave Mode Port Timing, Burst, Master Mode Port Timing, Burst, Slave Mode Peripheral Access Read Timing, MMODE Peripheral Access Write Timing, MMODE Peripheral Access Read Timing, MMODE Peripheral Access Write Timing, MMODE PQFP (Plastic Quad Flat Pack) Package Dimensions.
subsidiary Comtech Telecommunications Corporation
PS3520_1098
INTRODUCTION
AHA3520 single chip lossless compression decompression integrated circuit implementing industry standard adaptive lossless data compression algorithm, also known ALDC. device compresses, decompresses passes through data unchanged depending operating mode selected. This device achieves average compression ratio typical computer files. flexible hardware interface makes this part suitable many applications. 3520 algorithm pinout compatible ALDC device. Compressed files between IBM's implementation algorithm always produce same compressed code stream. However, decompressed results always same. Files compressed either device interchanged decompressed either device. Content Addressable Memory (CAM) within compression/decompression engine eliminates need external SRAMS. This part connects directly industry standard peripheral chips. Included this specification functional overview, operation modes, register descriptions, Electrical characteristics, ordering information, listing related technical publications. intended hardware software engineers designing compression system using AHA3520. designs develops lossless compression, forward error correction data storage formatter/controller ICs. Other ALDC product offering includes AHA3521. This firmware compatible device that includes additional features. Technical publications available upon request.
followed least significant bit. example, MDATA[7:0] indicates signal names MDATA7 through MDATA0. Mega Bytes second referred MBytes/sec MB/sec. Reserved bits registers referred "res".
FEATURES
CONVENTIONS, NOTATIONS DEFINITIONS
PERFORMANCE: MB/s data compression, decompression pass-through rate with single clock average compression ratio four byte Transfer Size register allows block transfers gigabytes Error checking decompression mode reportable interrupt FLEXIBILITY: In-line Look-aside architectures supported Polled interrupt driven independent ports programmable 16-bit transfers, handshaking modes master slave operation Programmable polarity control signals SYSTEM INTERFACE: Single chip data compression solution selectable microprocessor interfaces Programmable Interrupts Interfaces directly with AHA5140 tape formatter industry standard SCSI chips OTHERS: Open standard ALDC adaptive lossless compression algorithm Complies QIC-154, ECMA 222, ANSI X3.280-1996 15200 standard specifications Compatible ALDC1-20S-HA specification package PQFP
APPLICATIONS
Active signals have appended signal name. example, WRITEN. "Signal assertion" means output signal logically true. values represented with prefix "0x", such Register "0x00". Binary values contain prefix, example, MMODE prefix suffix indicates letter missing register name signal name. example, xCNF0 refers ACNF0 BCNF0 register. range signal names register bits denoted colons between numbers. Most significant always shown first,
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FUNCTIONAL DESCRIPTION
AHA3520 compression/decompression device residing between host interface, usually SCSI, buffer manager ASIC. Major blocks this device Microprocessor Interface, Port Interface, Port Interface, Compression/ Decompression Engine. Microprocessor Interface provides status control information register access. Port Port Interfaces ports configurable width, polarity, handshaking modes, other options.
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operating mode establishes direction both Port Port Interfaces. Compression Compression Pass Through sets Port Interface input Port Interface output. Conversely Decompression Decompression Pass Through sets Port Interface output Port Interface input. Decompression Output Disabled mode allows device decompress block data predetermined point while dumping uncompressed data, then automatically begin outputting remaining uncompressed data that block record. four byte Transfer Size counter allows user partition data into blocks four gigabytes less process. Compression Pass Through mode Decompression Pass Through modes allow data transfers through device without changing data. Both Port Interface Port Interface have 16-byte FIFO with Almost Empty Almost Full signal pins programmable thresholds. Both interfaces, Port Port have programmable wait states addition four selectable transfer modes: asynchronous request/acknowledge pair, asynchronous burst mode, peripheral access modes that correlate with microprocessor modes.
1.4.2
FIFO OPERATION
1.4.1
PORT PORT INTERFACES
Both Port Port Interfaces independently configurable Port Configuration registers (ACNFx), Port Polarity register (APOL), Port Configuration registers (BCNFx), Port Polarity register (BPOL). Both operate four modes. Four-edge mode asynchronous data transfer requiring request acknowledge pulse each transfer bytes, depending width configuration Interface. four edge transfer begins asserting request signal, followed acknowledge response request, which causes request deassert, finally this causes acknowledge deassert. Data transferred trailing edge acknowledge signal. Burst mode similar four-edge mode except there many acknowledges while request held asserted. advantage this mode that requires fewer clocks transfer. peripheral access modes exist selected MMODE pin. Peripheral access allows microprocessor write read from peripheral device connected Port Interface Port Interface. This mode relatively slow, asynchronous transfer. This mode allowed during data transfer operation.
Port Port Interfaces both contain sixteen-byte FIFOs with programmable thresholds. AHA3520 Almost Full Almost Empty signal associated with each Data Interfaces. FIFO thresholds programmed configuration registers (ACNF0 BCNF0). Data Interface configured either four-edge burst mode operation FIFO threshold determines when request gets asserted deasserted. During output transfer request signal asserts when number bytes FIFO greater than equal programmed FIFO threshold. interface continues request data transfers until FIFO becomes empty. When transferring data into either Port Port Interfaces, request signal asserts when number empty byte locations FIFO greater than equal programmed FIFO threshold. interface continues request data transfers until FIFO full. almost full (xAF) almost empty (xAE) signals always available user. Almost Full used early warning indicator stop transferring data into Port Interface Port Interface. signal used stop transfers Port Interface Port Interface signal deasserts when transfer operation begins. asserts clock after number empty byte locations FIFO less than equal FIFO threshold. signal deasserts clock after number empty byte locations FIFO greater than FIFO threshold. signal asserts when transfer operation begins. deasserts clock after number available bytes FIFO greater than FIFO threshold. signal asserts after clock when number available bytes FIFO less than equal FIFO threshold.
1.4.3
DATA EXPANSION DURING COMPRESSION
Data expansion occurs when size data increases during compression operation. This typically occurs when data compressed prior input into chip.The EXPAND status Port Transfer Count larger than Transfer Size register. data expansion caused Port Transfer Count exceed maximum 4-byte value then Overflow Error status gets set. Worst case expansion allowable algorithm 12.5% (9/8 times uncompressed transfer size).
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comtech corporation Figure Functional Block Diagram AHA3520 Compression Chip
ADATA[15:0] APARITY[1:0] ACOUT APCS ACIN
PORT INTERFACE PORT STATE MACHINE PORT TRANSFER COUNTER
PORT INTERFACE PORT STATE MACHINE PORT TRANSFER COUNTER
BDATA[15:0] BPARITY[1:0] BCOUT BPCS BCIN
ALDC ENGINE
PASS THROUGH CONTROLLER
CLOCK
CLOCK GENERATION
PROCESSOR INTERFACE
PROCESSOR INTERFACE STATE MACHINE
INTERRUPT LOGIC
MMODE
ADDR[4:0]
MCIN[1:0]
RESETN
MDATA[7:0]
WAITN
COMPRESSION OPERATION
COMPRESSION PASS THROUGH
Compression Pass Through mode allows data enter Port Interface, transfer through device unchanged exit through Port Interface. Pass through mode uses Port Transfer counter, Port Transfer counter Transfer Size register. DONE status interrupt masked) when transfer completes.
COMPRESSION
During compression operation, uncompressed data flows into Port Interface, compressed compression engine compressed data transferred Port Interface. device contains Content Addressable Memory (CAM). history buffer during compression operation. compressor appends marker control code compressed data. also pads transfer
PS3520_1098
byte boundary with zeroes. marker control codewords monitored during decompression, determine Decompression errors. compression engine constantly monitors performance compression expansion during compression operation. EXPAND Port Transfer Count larger than transfer size compression operation. When Port Transfer Count higher than Port Transfer Count EXPAND Status register indicating data expansion during compression operation. Port Interface count increments with each byte received when this count equals transfer size, bytes this transfer have been received into Port compression operation complete when last byte transfers Port Interface Port Interface count zero, thus setting DONE status generating Done Interrupt masked.
IREQN
IREQ
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DECOMPRESSION OPERATION
DECOMPRESSION PASS THROUGH
Decompression Pass Through mode allows data enter Port Interface, transfer through device unchanged exit through Port Interface. Pass through mode uses Port Transfer counter, Port Transfer counter Transfer Size register. DONE status interrupt masked) when transfer completes.
reached where user wants data (Port Transfer Count equal greater than Data Disable Count), device switches normal decompression mode remainder that file decompressed transferred Port Interface. Removal headers also applies this mode.
MICROPROCESSOR INTERFACE REGISTER ACCESS
MICROPROCESSOR INTERFACE
DECOMPRESSION
During Decompression mode, compressed data flows into Port Interface decompressed. resulting uncompressed data transferred Port Interface. number compressed bytes transfer programmed into four byte Transfer Size register. decompression operation complete when last byte transfers Port Interface, thus setting DONE status generating Done Interrupt masked. types errors detected reported during decompression. Decoder Control Coder Errors caused detection invalid control codes compressed data stream. Decoder Errors detected when either decompressor encountered control code before expected record indicated Transfer Size register, record reached according Transfer Size register control code detected. These errors reported Error Status register.
Microprocessor Interface configuration determined MMODE pin. MMODE tied high transfers controlled chip select signal (CSN) read/write signal (RWN), otherwise transfers controlled separate read (READN), write (WRITEN) signals. Refer Section 10.0 Timing Specifications timing diagrams.
4.1.1
INTERRUPTS
DECOMPRESSION OUTPUT DISABLED MODE
Decompressed output disabled mode allows user decompress point record block rebuild history buffer while discarding uncompressed data. After point file
IREQ IREQN hardware interrupt signals. IREQN negative active open-drain output that requires pull-up resistor used. IREQ standard output. When active they indicate interrupt device. microprocessor determine cause interrupt reading Interrupt Status register. Masking individual interrupts with Interrupt Mask register disables particular interrupts from causing interrupt signal pins assert (IREQ IREQN). They disable bits Interrupt Status register. interrupt signals reset their inactive state when either hardware software reset occurs, when data transfer operation resumes, when data transfer operation begins. addition, disabling Interrupt Mask bits after Interrupt asserted, clears interrupt deasserts Interrupt pin.
Table
Microprocessor Interface Control Signals MMODE TIED
READN WRITEN WAITN ADDR[0] selects register bits ADDR[0] selects register bits 15:8
NAME
MCIN[0] MCIN[1] WAITN ADDR[0]
MMODE TIED HIGH
WAITN ADDR[0] selects register bits 15:8 ADDR[0] selects register bits
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PAUSING
AHA3520 hardware reset signal software reset. When RESETN signal asserted registers except Identification registers reset, current operations cancelled, history buffer cleared. software reset Command register does affect Configuration registers (ACNFx BCNFx), Identification registers (IDx), either Polarity registers (APOL BPOL), Command register (CMND). other registers reset, current operations cancelled history buffer cleared.
When Pause command issued, device pauses next break handshaking. When port slave mode, pauses after xCOUT (DACKx) deasserts. When port master mode xCOUT (DREQx) asserted, port does pause until xCIN (DACKx) recieved from external device. AHA3520 waits until both ports paused, which time BUSY status clears PAUSED status interrupt set.
REGISTER ACCESS
PORT PORT CONFIGURATION
MMODE determines whether ADDR[0] selects even addressed registers. When MMODE high ADDR[0]=0, addressed registers accessible. MMODE=1 causes ADDR[0] input signal inverted. following registers stable BUSY set: Status Status Port Transfer Count, Port Transfer Count, Error Status, Interrupt Status FIFO Access.
Port Port operate identically. They both 16-bit bidirectional data ports with parity checking generation. There three configuration registers associated with each port polarity register that determines polarity control signals that port. function control determined either xCNF0[13, bits Command register programmed peripheral access. polarity control signals controlled specific bits Polarity registers.
Table
Port Interface Signals SIGNAL NAME
ACIN ACOUT APCS
MASTER
SLAVE=0 DACKA DREQA deasserted deasserted APCS
SLAVE
SLAVE=1 DREQA DACKA APCS
APOL
DIRECTION
Table
Port Interface Signals SIGNAL NAME
BCIN BCOUT BPCS
MASTER
SLAVE=0 DACKB DREQB deasserted deasserted BPCS
SLAVE
SLAVE=1 DREQB DACKB BPCS
BPOL
DIRECTION
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REGISTER DESCRIPTION
ADDR[4:0] REGISTER RESET VALUE MNEMONIC
STAT0 ACNF0 ACNF1 BCNF0 BCNF1 APOL BPOL ATC2 ATC3 ATC0 ATC1 BTC2 BTC3 BTC0 BTC1 ERRS INTS CMND DDC2 DDC3 DDC0 DDC1 EMSK IMSK
MMODE=0 MMODE=1
REGISTER NAME
Status Reserved Port Configuration Port Configuration Port Configuration Port Configuration Identification Reserved Port Polarity Reserved Port Polarity Reserved Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Port Transfer Count, Byte Error Status Reserved Interrupt Status Reserved Reserved Command Reserved Reserved Transfer Size, Byte Transfer Size, Byte Transfer Size, Byte Transfer Size, Byte Data Disabled Count, Byte Data Disabled Count, Byte Data Disabled Count, Byte Data Disabled Count, Byte Error Mask Reserved Interrupt Mask Reserved
NOTES HARDWARE
RESET
0x00 0x01 0x00 0x01 0x00 0x01 0x02 0x03 0x02 0x03 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Notes:
0x01 0x00 0x01 0x00 0x01 0x00 0x03 0x02 0x03 0x02 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0B 0x0A 0x0D 0x0C 0x0F 0x0E 0x11 0x10 0x13 0x12 0x15 0x14 0x17 0x16 0x19 0x18 0x1B 0x1A 0x1D 0x1C 0x1F 0x1E
0x00 0x00 0x00 0x00 0x00 0xC1 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
RESET TRANSFER COMMAND COMMAND 0x00 0x80
unchanged unchanged unchanged unchanged 0xC1
unchanged unchanged unchanged unchanged 0xC1
unchanged unchanged unchanged unchanged 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00
0x00
0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
unchanged unchanged unchanged unchanged unchanged unchanged unchanged unchanged unchanged unchanged
When CMND Selection Command. When CMND Select Port Configuration Command. When CMND Select Port Configuration Command. When CMND Transfer Command Select Port Configuration Command. When CMND Transfer Command Select Port Configuration Command.
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STATUS (STAT0)
Read Only Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
BUSY
bit6
paused
bit5
bit4
bit3
bit2
bit1
bit0
DONE
0x00 0x01 BUSY
OUTDIS BYPASS EXPAND ANYINT ANYERR
Busy. This when data transfer operation begins. cleared when data transfer operation completes successfully, when unmasked error occurs, when reset occurs, when paused command issued microprocessor. Paused. This when data transfer operation currently paused. cleared when paused data transfer operation resumed when reset occurs.
paused
OUTDIS Output Disabled. This when Port Interface output disabled. cleared when Port Interface output re-enabled when reset occurs. BYPASS Bypass. This after Start Compression Bypass Start Decompression Bypass command written Command register. cleared after Start Compression, Start Decompression when reset occurs. EXPAND Expansion. This when Port Transfer Count register larger than Transfer Size register compression operation. cleared when another data transfer operation begins when reset occurs. ANYINT Interrupt. This while unmasked interrupt active. This signal mirrors Interrupt signal pin. ANYERR Error. This when unmasked error occurs. cleared when data transfer operation begins when reset occurs. DONE Done. This when current data transfer operation complete. cleared when data transfer operation begins when reset occurs.
PORT CONFIGURATION (ACNF0)
Read/Write Reset Value 0x00 Software Reset Value unchanged
MMODE
bit7
bit6
bit5
WAITST[2:0]
bit4
bit3
bit2
bit1
bit0
0x00 0x01 reserved
FIFOTH[3:0]
WAITST[2:0]-Wait State. These bits configure number wait states used during Port Interface peripheral access. values through valid. FIFOTH[3:0]-FIFO Threshold. These bits configure Port FIFO threshold value. Values from 0000 through 1111 valid.
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PORT CONFIGURATION (ACNF1)
Read/Write Reset Value 0x00 Software Reset Value unchanged
MMODE
bit7
bit6
bit5
SLAVE
bit4
bit3
bit2
WIDE
bit1
bit0
0x01 0x00 PARITY
MODE[1:0]
reserved
PARITY Parity. When set, parity checking enabled ADATA[15:0] data bus. When cleared, parity checking disabled ADATA[15:0] bus. Odd. Setting this along with PARITY enables parity checking generation ADATA[15:0] data bus. When cleared with PARITY even parity checking generation enabled ADATA[15:0] data bus. Slave. When set, Port Interface acts slave device generates acknowledges response requests. When cleared, Port Interface acts master, generates requests expects acknowledges.
SLAVE
MODE[1:0]-DMA Mode. These bits configure interface mode Port Interface with values defined below.
MODE[1:0]
WIDE
TYPE
Four Edge Burst reserved reserved
Byte. When set, ADATA[15:0] PARITY[1:0] used. When cleared, AD[7:0] PARITY[0] used.
PORT CONFIGURATION (BCNF0)
Read/Write Reset Value 0x00 Software Reset Value unchanged
MMODE
bit7
bit6
bit5
WAITST[2:0]
bit4
bit3
bit2
bit1
bit0
0x00 0x01 reserved
FIFOTH[3:0]
WAITST[2:0]-Wait State. These bits configure number wait states used during Port Interface peripheral access. values through valid. Values 000, 001, result wait states. FIFOTH[3:0]-FIFO Threshold. These bits configure Port FIFO threshold value. Values from 0001 through 1111 valid. value 0000 results same operation 0001.
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PS3520_1098
PORT CONFIGURATION (BCNF1)
Read/Write Reset Value 0x00 Software Reset Value unchanged
MMODE
bit7
bit6
bit5
SLAVE
bit4
bit3
bit2
WIDE
bit1
bit0
0x01 0x00 PARITY
MODE[1:0]
reserved
PARITY Parity. When set, parity checking enabled BDATA[15:0] data bus. When cleared, parity checking disabled BDATA[15:0] bus. SLAVE Odd. When set, parity checking generation used BDATA[15:0] data bus. When cleared, even parity checking generation used BDATA[15:0] data bus. Slave. When set, Port Interface acts slave device generates acknowledges response requests. When cleared, Port Interface acts master, generates requests expects acknowledges.
MODE[1:0]-DMA Mode. These bits configure interface mode Port Interface with values defined below.
MODE[1:0]
WIDE
TYPE
Four Edge Burst reserved reserved
Byte. When set, BDATA[15:0] PARITY[1:0] used. When cleared, BD[7:0] PARITY[0] used.
IDENTIFICATION (ID)
Read Only Value Contact Applications Engineering
MMODE
bit7
bit6
bit5
bit4
bit3
id[7:0]
bit2
bit1
bit0
0x02 0x03 id[7:0]-
bits this register correspond identification code chip. This register accessible when CMND Selection Command.
PORT POLARITY (APOL)
Read/Write Reset Value 0xFF Software Reset Value unchanged
MMODE
bit7
ACIN
bit6
reserved
bit5
ACOUT
bit4
bit3
bit2
APCS
bit1
bit0
0x02 0x03
bits this register correspond Port Interface signals. programs corresponding signal active low. cleared programs corresponding signal active high. This register only accessible when CMND Select Port Configuration.
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PORT POLARITY (BPOL)
Read/Write Reset Value 0xFF Software Reset Value unchanged
MMODE
bit7
BCIN
bit6
reserved
bit5
BCOUT
bit4
bit3
bit2
BPCS
bit1
bit0
0x02 0x03
bits this register correspond Port Interface signals. programs corresponding signal active low. cleared programs corresponding signal active high.This register only accessible when CMND Select Port Configuration.
PORT TRANSFER COUNT (ATC0, ATC1, ATC2, ATC3)
Read Only Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0x06 0x07 0x04 0x05
0x07 0x06 0x05 0x04
ATC[7:0] ATC[15:8] ATC[23:16] ATC[31:24]
ATC[31:0]- Port Transfer Count. These registers provide status information number bytes transferred current data transfer operation. During compression operation, incremented each original data byte received Port Interface. When equals during compression, bytes compression operation have been received AHA3520. During decompression operation, incremented each decompressed data byte sent Port Interface. This register only accessible when CMND Selection Command.
6.10 PORT TRANSFER COUNT (BTC0, BTC1, BTC2, BTC3)
Read Only Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0x00 0x01 0x00 0x01
0x01 0x00 0x01 0x00
BTC[7:0] BTC[15:8] BTC[23:16] BTC[31:24]
BTC[31:0] -Port Transfer Count. These registers provide status information number bytes transferred current data transfer operation. During compression operation, incremented each compressed data byte sent Port Interface. During decompression operation, incremented each compressed data byte received Port Interface. When equals during decompression, bytes decompression operation have been received AHA3520 host interface.This register only accessible when CMND Selection Command.
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6.11 ERROR STATUS (ERRS)
Read Only Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
aperr
bit5
bperr
bit4
reserved
bit3
BTCO
bit2
ATCO
bit1
ADCC
bit0
0x0C 0x0D reserved
Error Status register provides error status bits microprocessor. This register should only read when CMND Selection Command. These bits regardless error mask settings. APerr Port Interface Parity Error. This when parity error detected during transfer into ADATA[15:0] Port Interface Parity set. cleared when data transfer operation begins when reset occurs. Port Interface Parity Error. This when parity error detected during transfer into BDATA[15:0] Port Interface Parity set. cleared when data transfer operation begins when reset occurs. Port Transfer Count Overflow Error. This when carry detected Port Transfer Count register. cleared when data transfer operation begins when reset occurs. Port Transfer Count Overflow Error. This when carry detected Port Transfer Count register. cleared when data transfer operation begins when reset occurs. ALDC Decoder Control Code Error. This during decompression when invalid control code detected compressed data stream. cleared when data transfer operation begins when reset occurs. ALDC Decoder Error. This during decompression when control code detected while Port Transfer Count less than Transfer Size when equals control code detected compressed data stream. cleared when data transfer operation begins when reset occurs.
BPerr
BTCO ATCO ADCC
6.12 INTERRUPT STATUS (INTS)
Read Only Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
DONE
bit6
paused
bit5
bit4
bit3
reserved
bit2
bit1
bit0
ERROR
0x0E 0x0F DONE
Done Interrupt. This when data transfer completed Port Interface during compression when data transfer completed Port Interface during decompression. cleared when data transfer operation begins when reset occurs. Paused Interrupt. This when current transfer step after microprocessor issues Pause command completed. cleared when microprocessor issues Resume command, when data transfer operation begins, when reset occurs.
paused
ERROR Error Interrupt. This when error occurs. cleared when data transfer operation begins when reset occurs. Error Status register used determine cause error.
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6.13 COMMAND (CMND)
Read/Write Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0x11 0x10
CMND[7:0]
Command register used program operation compression subsystem. CMND[7:0]-Command.This register provides operation described following table.
CMND[7:0]
0xC1 0xC2 0xC4 0xC8
ACTION SELECTION COMMANDS
Select Port Configuration. Port Configuration Port Polarity registers enabled reads writes. Select Port Configuration. Port Configuration Port Polarity registers enabled reads writes. Select Port Interface Peripheral Access. peripheral access addresses enabled reads writes Port Interface attached peripheral. Select Port Interface Peripheral Access. peripheral access addresses enabled reads writes Port Interface attached peripheral.
TRANSFER COMMANDS
(Described Sections 3.0)
0x50 0x58 0x60 0x68 0x6C
Start Compression Bypass. Start Compression. Start Decompression Bypass. Start Decompression. Start Decompression Output Disabled.
CONTROL COMMANDS
0x42 Pause. When data transfer operation progress, current operation steps completed Port Interface Port Interface data busses placed into high impedance state. Paused Interrupt Paused Status bits then set. data currently being processed data transfer operation preserved. Resume. previously paused data transfer operation resumes processing. Paused Interrupt Paused status bits cleared Busy status set. Software Reset. Port Configuration, Port Configuration, Identification, Port Polarity, Port Polarity, Command registers affected this command. other registers reset, current operations cancelled, history buffer cleared.
0x44
0xA0
MISCELLANEOUS COMMANDS
0x00 NOP, operation performed.
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6.14 TRANSFER SIZE (TS0, TS1, TS2, TS3)
Read/Write Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
bit4
bit3
TS[7:0] TS[15:8] TS[23:16] TS[31:24]
bit2
bit1
bit0
0x16 0x17 0x14 0x15
0x17 0x16 0x15 0x14
TS[31:0]-
Transfer Size. Transfer Size register provides microprocessor control number bytes transferred during data transfer operation. direction data transfer operation specifies whether Port Transfer Count register Port Transfer Count register used determine when data bytes have been received data transfer operation. During compression, used. During decompression, used. When appropriate Transfer Count register (ATC BTC) equals bytes current data transfer operation have been received compression module.
6.15 DATA DISABLED COUNT (DDC0, DDC1, DDC2, DDC3)
Read/Write Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0x1A 0x1B 0x18 0x19
0x1B 0x1A 0x19 0x18
DDC[7:0] DDC[15:8] DDC[23:16] DDC[31:24]
DDC[31:0]- Data Disabled Count.The Data Disabled Count register provides microprocessor control number bytes skipped during Start Decompression Output Disabled operation. Data Disabled Count 0x00 during Start Decompression Output Disabled operation greater than Transfer Size (TS) during Start Decompression Output Disabled operation, then Port Interface output disabled entire transfer.
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6.16 ERROR MASK (EMSK)
Read/Write Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
bit5
BPerrm
bit4
reserved
bit3
BTCOm
bit2
ATCOm
bit1
ADCom
bit0
ADEm
0x1C 0x1D reserved APerrm
Error Mask register provides error reporting configuration microprocessor. unmasked error status active, ANYERR status ERROR interrupts set. APerrm Port Interface Parity Error Mask. BPerrm Port Interface Parity Error Mask.
BTCOm Port Transfer Count Overflow Error Mask. ATCOm Port Transfer Count Overflow Error Mask. ADCom ALDC Decoder Control Code Error Mask. ADEm ALDC Decoder Error Mask.
6.17 INTERRUPT MASK (IMSK)
Read/Write Reset Value 0x00 Software Reset Value 0x00
MMODE
bit7
bit6
pausedm
bit5
bit4
bit3
reserved
bit2
bit1
bit0
ERRORm
0x1E 0x1F DONEm
Interrupt Mask register masks individual interrupts allowing user control which ones cause Interrupt signal pins (IREQ IREQN) assert. example, DONE PAUSED with ERROR cleared, only ERROR interrupt will cause Interrupt signal pins assert. DONEm Done Interrupt Mask. pausedm Paused Interrupt Mask. ERRORm -Error Interrupt Mask.
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PS3520_1098
SIGNAL DESCRIPTIONS
This section contains descriptions pins. Each signal type code associated with type codes described following table.
TYPE CODE
DESCRIPTION
Input only Output only Input/Output
MICROPROCESSOR INTERFACE
MICROPROCESSOR INTERFACE SIGNAL TYPE
DESCRIPTION
Microprocessor data Microprocessor interface control [0]. MMODE high this CSN. MMODE this READN. Microprocessor interface control [1]. MMODE high this RWN. MMODE this WRITEN. Microprocessor output signal. WAITN driven during then goes tristate with resistive pullup. Microprocessor Interface address bus, used select internal registers. Microprocessor Interface mode selector pin. Hardware reset signal, resets registers except Identification register. Interrupt request output signal, open drain output. This signal requires pull-up resistor used system. Interrupt request output signal, active high. Clock input Active test pins. These pins must tied high system. Active testpin. Tristates pads
DEFAULT AFTER RESET
Hi-Z Input Input High (internal pullup) Input Input Input Hi-Z Input Input Input
MDATA[7:0] MCIN[0] MCIN[1] WAITN ADDR[4:0] MMODE RESETN IREQN IREQ CLOCK TESTN[6:0] TRISTATEN
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PORT INTERFACE
PORT INTERFACE SIGNAL TYPE
DESCRIPTION
Port Interface Control Input signal. This signal functions DACKA DREQA. Polarity programmed APOL[7]. Port Interface Control Output signal. This signal functions DACKA DREQA. Polarity programmed APOL[5]. Port Interface Control Output signal. Polarity controlled APOL[4]. Port Interface Control Output signal. Polarity controlled APOL[3]. Port Interface Control Output signal. Polarity controlled APOL[2]. Port Interface Output signal. Port FIFO almost full signal. Polarity programmed APOL[1]. Exactly when this flag gets depends threshold bits Port Configuration register. Port Interface Output signal. Port almost empty signal. Polarity programmed APOL[0]. Exactly when this flag gets depends threshold bits Port Configuration register. When enabled, this checks parity input generates parity output bus. APARITY[0] used AD[7:0], APARITY[1] used AD[15:8]. Setting ACNF[15]=1 enables APARITY[0]. Setting ACNF[15]=1 ACNF[10]=1 enables APARITY[1]. When disabled these pins tied high, tied connected. Port Interface Data bus. upper eight bits [15:8] enabled setting ACNF[10]=1. When upper eight bits disabled they tied high, tied low, connected.
DEFAULT AFTER RESET
Input High High High High High
ACIN ACOUT APCS
APARITY[1:0]
Hi-Z
ADATA[15:0]
Note:
Hi-Z
Refer Section Port Port Configuration Table configuration Port control signals.
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PS3520_1098
PORT INTERFACE
PORT INTERFACE SIGNAL TYPE
DESCRIPTION
Port Interface Control Input signal. This signal functions DACKB DREQB. Polarity programmed BPOL[7]. Port Interface Control Output signal. This signal functions DACKB DREQB. Polarity programmed BPOL[5]. Port Interface Control Output signal. Polarity controlled BPOL[4]. Port Interface Control Output signal. Polarity controlled BPOL[3]. Port Interface Control Output signal. Polarity controlled BPOL[2]. Port Interface Output signal. Port FIFO almost full signal. Polarity programmed BPOL[1]. Exactly when this flag gets depends threshold bits Port Configuration register. Port Interface Output signal. Port almost empty signal. Polarity programmed BPOL[0]. Exactly when this flag gets depends threshold bits Port Configuration register. When enabled, this checks parity input generates parity output bus. BPARITY[0] used BD[7:0], BPARITY[1] used BD[15:8]. Setting BCNF[15]=1 enables BPARITY[0]. Setting BCNF[15]=1 BCNF[10]=1 enables BPARITY[1]. When disabled these pins tied high, tied connected. Port Interface Data bus. upper eight bits [15:8] enabled setting BCNF[10]=1. When upper eight bits disabled they tied high, tied low, connected.
DEFAULT AFTER RESET
Input High High High High High
BCIN BCOUT BPCS
BPARITY[1:0]
Hi-Z
BDATA[15:0]
Note:
Hi-Z
Refer Section Port Port Configuration Table configuration Port control signals.
PS3520_1098
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PINOUT
SIGNAL
BDATA[7] BDATA[6] BDATA[5] BDATA[4] BDATA[3] BDATA[2] BDATA[1] BDATA[0] BDATA[15] BDATA[14] BDATA[13] BDATA[12] BDATA[11] BDATA[10] BDATA[9] BDATA[8] BPARITY[0] BPARITY[1] IREQN IREQ BPCS WAITN BCOUT RESETN TRISTATEN ADDR[4] ADDR[3] TESTN[0] BCIN TESTN[1] ADDR[2] ADDR[1] ADDR[0]
SIGNAL
ACIN ADATA[7] ADATA[6] TESTN[2] ADATA[5] ADATA[4] ADATA[3] ADATA[2] APCS ADATA[1] ADATA[0] ADATA[15] ADATA[14] ADATA[13] ADATA[12] ADATA[11] ADATA[10] ADATA[9] ADATA[8] APARITY[0] APARITY[1] MDATA[7] TESTN[3] TESTN[4] MDATA[6] MDATA[5] MDATA[4] MDATA[3] ACOUT MCIN[0] MCIN[1] MDATA[2] MDATA[1] MDATA[0] MMODE TESTN[5] TESTN[6]
PS3520_1098
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Figure
PS3520_1098
MDATA[7] TESTN[3] TESTN[4] MDATA[6] MDATA[5] MDATA[4] MDATA[3] ACOUT MCIN[0] MCIN[1] MDATA[2] MDATA[1] MDATA[0] MMODE TESTN[5] TESTN[6]
Pinout
AHA3520A-040
subsidiary Comtech Telecommunications Corporation
BDATA[7] BDATA[6] BDATA[5] BDATA[4] BDATA[3] BDATA[2] BDATA[1] BDATA[0] BDATA[15] BDATA[14] BDATA[13] BDATA[12] BDATA[11] BDATA[10] BDATA[9] BDATA[8] BPARITY[0] BPARITY[1] IREQN
ADDR[0] ADDR[1] ADDR[2] TESTN[1] BCIN TESTN[0] ADDR[3] ADDR[4] TRISTATEN RESETN BCOUT WAITN BPCS IREQ
APARITY[1] APARITY[0] ADATA[8] ADATA[9] ADATA[10] ADATA[11] ADATA[12] ADATA[13] ADATA[14] ADATA[15] ADATA[0] ADATA[1] APCS ADATA[2] ADATA[3] ADATA[4] ADATA[5] TESTN[2] ADATA[6] ADATA[7] ACIN
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS PARAMETER
Power supply voltage Voltage applied -0.5
SYMBOL
Vpin
UNITS
Volts Volts
NOTES
RECOMMENDED OPERATING CONDITIONS
RECOMMENDED OPERATING CONDITIONS PARAMETER
Power supply voltage Operating temperature 4.75 5.25
SYMBOL
UNITS
Volts
NOTES
SPECIFICATIONS
SPECIFICATIONS CONDITIONS
mAmps -0.4 mAmps Volts Volts Vout Volts Vout Volts 5.25 Volts
SYMBOL
Iozl Iozh IddA Cout CI/O
PARAMETER
Input voltage Input high voltage Output voltage Output high voltage Input current Input high current Output tristate current Output tristate high current Active current Supply current (static) level output current (except IREQN) IREQN (open drain) High level output current Input capacitance Output capacitance capacitance Load Capacitance
UNITS
Volts Volts Volts Volts µAmps µAmps µAmps µAmps mAmps mAmps mAmps mAmps
NOTES
Notes: Test Conditions: worst case compression current; loads.
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PS3520_1098
10.0 TIMING SPECIFICATIONS
Notes: timings referenced Volts.
Figure
Clock Timing
CLOCK
Table NUMBER
Notes:
Clock Timing PARAMETER
period pulsewidth high pulsewidth rise time fall time
Timings referenced Volts Rise fall times between Volts Volts.
UNITS NOTES
Figure
Reset Timing
RESETN
MCIN[0] MCIN[1] (CSN, READN WRITEN)
Table NUMBER
Reset Timing PARAMETER
RESETN pulsewidth RESETN delay CSN, READN WRITEN
UNITS NOTES
clocks clocks
Figure
Almost Full/Almost Empty Timing
CLOCK (input)
Table NUMBER
PS3520_1098
Almost Full/Almost Empty Timing PARAMETER
asserted from CLOCK rise deasserted from CLOCK rise
UNITS NOTES
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Notes: These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals.
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PS3520_1098
comtech corporation Figure Processor Read Timing, MMODE
MCIN[1] (RWN)
MCIN[0] (CSN)
WAITN
(Note Valid
ADDR
Valid Tristate
MDATA
Tristate
Table NUMBER
Note:
Processor Read Timing, MMODE PARAMETER
setup asserted hold from asserted pulsewidth Delay from deasserted until next asserted WAITN asserted hold from WAITN deasserted WAITN deasserted from asserted ADDR setup asserted ADDR hold from asserted MDATA valid from asserted MDATA tristate from deasserted MDATA hold from deasserted asserted MDATA driven deasserted WAITN tristate
clock+5
UNITS NOTES
clocks
clocks clock clocks+18
clocks+24
When WAITN causes deassert, ignore number otherwise ignore number device latches ADDR falling edge CSN. user should latch MDATA rising edge CSN. WAITN pulled internally with resistor when active driven low.
PS3520_1098
subsidiary Comtech Telecommunications Corporation
Page
comtech corporation Figure Processor Write Timing, MMODE
MCIN[1] (RWN)
MCIN[0] (CSN)
WAITN
(Note Valid
ADDR
Valid
MDATA
Table NUMBER
Notes:
Processor Write Timing, MMODE PARAMETER
setup asserted hold from asserted pulsewidth Delay from deasserted until next asserted WAITN asserted hold from WAITN deasserted WAITN deasserted from asserted ADDR setup asserted ADDR hold from asserted MDATA valid before deasserted MDATA hold from deasserted deasserted WAITN tristate
clock+5
UNITS NOTES
clocks
clock clocks+18
When WAITN causes deassert, ignore number otherwise ignore number When read register immediately follows write that same register command register, must deassert minimum clocks after write. device latches ADDR falling edge CSN. WAITN pulled internally with resistor when active driven low.
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subsidiary Comtech Telecommunications Corporation
PS3520_1098
comtech corporation Figure Processor Read Timing, MMODE
MCIN[0] (READN)
(Note
WAITN
(Note Valid Valid Tristate
ADDR
MDATA
Tristate
Table NUMBER
Notes:
Processor Read Timing, MMODE PARAMETER
READN pulsewidth Delay from READN deasserted until next READN READN asserted WAITN asserted READN hold from WAITN deasserted WAITN deasserted from READN asserted ADDR setup READN asserted ADDR hold from READN asserted MDATA valid from READN asserted MDATA tristate from READN deasserted MDATA hold from READN deasserted MDATA asserted from READN asserted READN deasserted WAITN tristate
UNITS NOTES
clocks clocks
clocks clock clocks+18
clocks+24
When WAITN causes READN deassert ignore number otherwise ignore number device latches ADDR falling edge READN. user should latch MDATA rising edge READN. WRITEN must deasserted during register reads. WAITN pulled internally with resistor when active driven low.
PS3520_1098
subsidiary Comtech Telecommunications Corporation
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comtech corporation Figure Processor Write Timing, MMODE
MCIN[1] (WRITEN)
(Note
WAITN
(Note Valid Valid
ADDR
MDATA
Table NUMBER
Notes:
Processor Write Timing, MMODE PARAMETER
WRITEN pulsewidth Delay from WRITEN deasserted until next WRITEN WRITEN asserted WAITN asserted WRITEN hold from WAITN deasserted WAITN deasserted from WRITEN asserted ADDR setup WRITEN asserted ADDR hold from WRITEN asserted MDATA valid before WRITEN deasserted MDATA hold from WRITEN deasserted WRITEN deasserted WAITN tristate
UNITS NOTES
clocks clocks
clock clocks+18
When WAITN causes WRITEN deassert ignore number otherwise ignore number device latches ADDR falling edge WRITEN. READN must deasserted during register writes. WAITN pulled internally with resistor when active driven low.
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PS3520_1098
comtech corporation Figure Port Timing, Four Edge, Master Mode
xCOUT (DREQx output)
xCIN (DACKx input)
Valid Valid Tristate Tristate
xDATA (output)
Tristate
xDATA (input)
Tristate
Table NUMBER
Notes:
Port Timing, Four Edge, Master Mode PARAMETER
UNITS NOTES
clocks clocks clocks
DACKx asserted DREQx deasserted Delay from DREQx deasserted next clocks-5 DREQx DREQx asserted DACKx asserted DACKx pulsewidth Delay from DACKx deasserted next DREQx xDATA (output) driven from DACKx asserted xDATA (output) hold from DACKx deasserted xDATA (input) valid before DACKx deasserted xDATA (input) hold from DACKx deasserted xDATA (output) valid from DACKx asserted
These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. Internal keepers hold xDATA until overdriven.
PS3520_1098
subsidiary Comtech Telecommunications Corporation
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comtech corporation Figure Port Timing, Four Edge, Slave Mode
xCIN (DREQx input)
xCOUT (DACKx output)
(output)
Valid Valid Tristate Tristate
xDATA (output)
Tristate
xDATA (input)
Tristate
Table NUMBER
Notes:
Port Timing, Four Edge, Slave Mode PARAMETER UNITS NOTES
DREQx pulsewidth clocks DACKx deasserted from DREQx deasserted clock clocks+22 Delay from DACKx deasserted next DREQx DREQx asserted DACKx asserted clocks DACKx pulsewidth clocks-8 xDATA (output) driven from DACKx clock-5 asserted xDATA (output) hold from DACKx deasserted clock-10 clock+5 xDATA (input) valid after DREQx deasserted clock-5 xDATA (input) hold from DACKx deasserted xDATA (output) valid from DACKx asserted clock+10
These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. Internal keepers hold xDATA until overdriven.
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PS3520_1098
comtech corporation Figure Port Timing, Burst, Master Mode
xCOUT (DREQx output)
xCIN (DACKx input)
Valid Valid Valid Tristate
xDATA (output)
Tristate
xDATA (input)
Tristate
Valid
Valid
Valid
Tristate
Table NUMBER
Notes:
Port Timing, Burst, Master Mode PARAMETER
UNITS NOTES
clocks clocks
Last DACKx asserted DREQx deasserted, burst DREQx asserted first DACKx asserted, start burst DACKx pulsewidth clocks-10 DACKx deasserted DACKx asserted clocks-10 Last DACKx deasserted next DREQx asserted, next burst xDATA (output) driven from DACKx asserted xDATA (output) hold from DACKx deasserted xDATA (input) valid before DACKx deasserted xDATA (input) hold from DACKx deasserted DACKx cycle time xDATA (output) valid from DACKx asserted
clocks
These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. Internal keepers hold xDATA until overdriven.
PS3520_1098
subsidiary Comtech Telecommunications Corporation
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comtech corporation Figure Port Timing, Burst, Slave Mode
xCIN (DREQx input)
xCOUT (DACKx output)
(output)
Valid Valid Valid Valid Tristate Valid Valid Tristate
xDATA (output)
Tristate
xDATA (input)
Tristate
Table NUMBER
Notes:
Port Timing, Burst, Slave Mode PARAMETER
Last DACKx asserted DREQx deasserted, burst DREQx asserted first DACKx asserted, start burst DACKx pulsewidth DACKx deasserted DACKx asserted Last DACKx deasserted next DREQx asserted, next burst xDATA (output) driven from DACKx asserted xDATA (output) hold from DACKx deasserted xDATA (input) valid after DACKx asserted xDATA (input) hold from DACKx deasserted xDATA (output) valid from DACKx asserted
clocks-22
UNITS NOTES
clocks clocks
clocks-8 clocks+8 clocks-8 clock-5 clock-10 clock+5 clocks-18 clock+10
These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. Internal keepers hold xDATA until overdriven.
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PS3520_1098
comtech corporation Figure Peripheral Access Read Timing, MMODE
MCIN[1] (RWN)
MCIN[0] (CSN)
WAITN
(Note Valid
ADDR
Tristate
MDATA (output)
Valid
Tristate
xRDN
xPCSN
xDATA (input)
Valid
Table NUMBER
Notes:
PS3520_1098
Peripheral Access Read Timing, MMODE PARAMETER
setup asserted hold from asserted pulsewidth Delay from deasserted until next asserted WAITN asserted hold from WAITN deasserted WAITN deasserted from asserted ADDR setup asserted ADDR hold from asserted MDATA (output) hold from deasserted MDATA (output) valid from xDATA (input) valid xRDN asserted from asserted xRDN deasserted from deasserted xPCSN asserted from asserted xPCSN deasserted from deasserted deasserted WAITN tristate
(n+1) clocks clock clock clock clock
UNITS NOTES
clocks clocks
(n+1) clocks clocks+21 clocks+21 clocks+21 clocks+21
When WAITN causes deassert ignore number otherwise ignore number number wait states programmed into xCNF registers. device latches ADDR falling edge CSN. user should latch MDATA rising edge CSN. These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. WAITN pulled internally with resistor when active driven low.
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comtech corporation Figure Peripheral Access Write Timing, MMODE
MCIN[1] (RWN)
MCIN[0] (CSN)
WAITN
(Note Valid
ADDR
Valid Tristate
MDATA
Tristate
xWRN
xPCSN
xDATA (output) Tristate
Valid
Tristate
Table Peripheral Access Write Timing, MMODE NUMBER PARAMETER
Notes:
UNITS NOTES
clocks clocks
setup asserted hold from asserted pulsewidth Delay from deasserted until next asserted WAITN asserted hold from WAITN deasserted WAITN deasserted from asserted ADDR setup asserted ADDR hold from asserted MDATA valid before deasserted MDATA hold from deasserted xWRN asserted from asserted xWRN deasserted from deasserted xPCSN asserted from asserted xPCSN deasserted from deasserted xDATA (output) tristated from deasserted xDATA valid from deasserted asserted xDATA driven MCIN[0] inactive WAITN tristate
(n+1) clocks clock clock clock clock clocks clock
(n+1) clocks+18
clocks+21 clocks+21 clocks+21 clocks+21 clocks+17
When WAITN causes deassert ignore number otherwise ignore number number wait states programmed into xCNF registers. device latches ADDR falling edge CSN. These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals.
subsidiary Comtech Telecommunications Corporation
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PS3520_1098
WAITN pulled internally with resistor when active driven low. This timing applies before write access well after.
PS3520_1098
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comtech corporation Figure Peripheral Access Read Timing, MMODE
MCIN[0] (READN)
WAITN
(Note Valid
ADDR
MDATA (output)
Tristate
Valid
Tristate
xRDN
xPCSN
xDATA (input)
Valid
Table NUMBER
Notes:
Peripheral Access Read Timing, MMODE PARAMETER UNITS NOTES
READN pulsewidth (n+1) clocks Delay from READN deasserted until next clocks READN READN asserted WAITN asserted READN hold from WAITN deasserted WAITN deasserted from READN asserted clocks (n+1) clocks+18 ADDR setup from READN asserted ADDR hold from READN asserted MDATA (output) hold from READN deasserted MDATA (output) valid from xDATA (input) valid xRDN asserted from READN asserted clock clocks+21 xRDN deasserted from READN deasserted clock clocks+21 xPCSN asserted from READN asserted clock clocks+21 xPCSN deasserted from READN deasserted clock clocks+21 READN deasserted WAITN tristate
When WAITN causes READN deassert ignore number otherwise ignore number device latches ADDR falling edge READN. user should latch MDATA rising edge READN. WRITEN must deasserted during register reads. number wait states programmed into xCNF registers. These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. WAITN pulled internally with resistor when active driven low.
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PS3520_1098
comtech corporation Figure Peripheral Access Write Timing, MMODE
MCIN[1] (WRITEN)
WAITN
(Note Valid
ADDR
Valid Tristate
MDATA (input)
Tristate
xWRN
xPCSN
xDATA (output)
Tristate
Valid
Tristate
Table NUMBER
Notes:
Peripheral Access Write Timing, MMODE PARAMETER
WRITEN pulsewidth Delay from WRITEN deasserted until next WRITEN WRITEN asserted WAITN asserted WRITEN hold from WAITN deasserted WAITN deasserted from WRITEN asserted ADDR setup from WRITEN asserted ADDR hold from WRITEN asserted MDATA valid before WRITEN deasserted MDATA hold from WRITEN deasserted xWRN asserted from WRITEN asserted xWRN deasserted from WRITEN deasserted xPCSN asserted from WRITEN asserted xPCSN deasserted from WRITEN deasserted xDATA (output) tristated from WRITEN deasserted xDATA valid from WRITEN deasserted WRITEN asserted xDATA driven WRITEN inactive WAITN tristate
(n+1) clocks clock clock clock clock clocks clock
UNITS NOTES
clocks clocks
(n+1) clocks+18
clocks+21 clocks+21 clocks+21 clocks+21 clocks+17
When WAITN causes WRITEN deassert ignore number otherwise ignore number device latches ADDR falling edge WRITEN. READN must deasserted during register writes. number wait states programmed into xCNF registers. These timings valid both Port Port inverted signal polarities. Replace with Port signals Port signals. WAITN pulled internally with resistor when active driven low.
PS3520_1098
subsidiary Comtech Telecommunications Corporation
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11.0 PACKAGING
Figure AHA3520 PQFP Package Specifications
AHA3520A-040
(LCA)
(LCB)
Table
PQFP (Plastic Quad Flat Pack) Package Dimensions
(All dimensions
NUMBER SPECIFICATION DIMENSION SYMBOL
(LCA) (LCB)
Page
0.23 2.71 23.9 17.9 0.88 0.65
0.36 2.87 24.15 20.1 18.15 14.1 1.03 0.33
PS3520_1098
2.57 23.65 19.9 17.65 13.9 0.73 0.22
subsidiary Comtech Telecommunications Corporation
JEDEC Outline MO-112
PS3520_1098
subsidiary Comtech Telecommunications Corporation
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12.0 ORDERING INFORMATION
12.1 AVAILABLE PARTS
PART NUMBER
AHA3520A-040
DESCRIPTION
MBytes/sec ALDC Data Compression Coprocessor with Enhanced Features, PQFP
12.2 PART NUMBERING
Manufacturer
3520
Device Number
ARevision Level
Speed Designation
Package Material
Package Type
Test Specification
Device Number:
3520
Revision Letter:
Package Material Codes:
PPlastic
Package Type Codes:
Quad Flat Pack
Test Specifications:
Commercial0°C +70°C
13.0 RELATED TECHNICAL PUBLICATIONS
DOCUMENT
PB3520 PB3521 PS3521 ANDC18 ANDC19
DESCRIPTION
Product Brief AHA3520 MBytes/sec ALDC Data Compression Coprocessor Product Brief AHA3521 MBytes/sec ALDC Data Compression Coprocessor with Enhanced Features Product Specification AHA3521 MBytes/sec ALDC Data Compression Coprocessor with Enhanced Features Application Note Differences between Devices Application Note Designer's Guide ALDC Compression/ Decompression Devices: AHA3520 AHA3521
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PS3520_1098
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