198A854 Other Read/Write Cycle Times (-30 90°C) Number Pending As

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198A854 Other Read/Write Cycle Times (-30 90°C) Number Pending As

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128K Radiation Hardened Static MCM-
198A854
Other Read/Write Cycle Times (-30 90°C) Number Pending Asynchronous Operation CMOS Compatible Single Power Supply Operating Power Packaging Options 308-Lead Quad Flat Pack (2.050" 2.050")
Radiation Fabricated with Bulk CMOS Process Total Dose Hardness through 1x106 rad(Si) Neutron Hardness through 1x1014 N/cm2 Dynamic Static Transient Upset Hardness through 1x109 rad(Si)/s Soft Error Rate 1x10-11 Upsets/Bit-Day Dose Rate Survivability through 1x1012 rad(Si)/s Latchup Free
General Description
128K radiation hardened static composed 128K SRAM memory assembled single, doublesided ceramic substrate. Each high performance 131,072 word 8-bit static random access memory with industrystandard functionality. fabricated with SYSTEMS' radiation hardened technology designed systems operating radiation environments. operates over full military temperature range requires single power supply. available with CMOS compatible I/O. Power consumption less than mW/MHz operation, less than power disabled mode. read operation fully asynchronous, with associated typical access time nanoseconds. SYSTEMS' enhanced bulk CMOS technology radiation hardened through advanced proprietary design, layout, process hardening techniques.
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Functional Diagram
(for Lead Data Bottom (for Bottom Bottom Bottom Bottom Bottom (for U17) (for U17) Lead Data Bottom
Signal Definitions
0-16
Address input pins that select particular eight-bit word within memory array. Bi-directional data pins that serve data outputs during read operation data inputs during write operation. Negative chip select, when level, allows normal read write operation. When high level, through forces SRAM precharge condition, holds data output drivers high impedance state disables data input buffers only. this signal used, must connected GND.
Negative write enable, when level, activates write operation holds data output drivers Bottom high impedance state. When high level, allows normal read operation.
0-71 Bottom
Negative output enable, when high level holds data output drivers high impedance state. When Bottom
level, data output driver state defined through S18, through E18. this signal used must connected GND.
Chip enable, when high level allows normal
operation. When level, through forces SRAM precharge condition, holds data output drivers high impedance state disables input buffers except through input buffer. this signal used, must connected VDD.
Truth Table
Inputs(1),(2)
Mode
Power
Write Read Standby
High
High High
High
Data-In Data-Out High-Z
Active Active Standby
Notes: don't care inputs VIH. When high, high-Z. dissipate minimum amount standby power when standby mode: VDD. other input levels float.
Absolute Maximum Ratings
Applied Conditions(1) Minimum Maximum
Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage Output Voltage Power Dissipation Lead Temperature (Soldering sec) Electrostatic Discharge Sensitivity
Notes:
-65°C -30°C -0.5 -0.5 -0.5
+150°C +105°C +5.5 VDD+ VDD+ 4.04 +250°C
(Class
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. voltages with reference module ground leads. Maximum applied voltage shall exceed +5.5 Guaranteed design; tested. Class defined MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol Data Data Address Clock Address Clock Parameters(1) Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" (Data) Input Logic "High" (Data) Input Logic "Low" (Address Clocks) Input Logic "High" (Address Clocks) Minimum +3.14 +2.0 +2.0 Maximum +3.46 +1.0 +1.0 Units Volt Volt Celsius Volt Volt Volt Volt
Note:
1)All voltages referenced GND.
Power Sequencing
substrate this module connected directly Ground. Power shall applied device only following sequences prevent damage excessive currents: Power-Up Sequence: GND, VDD, Inputs Power-Down Sequence: Inputs, VDD,
Electrical Characteristics
Group Sub-Groups Device Type Limits Minimum Maximum
Test
Symbol Test Conditions(1) FMAX 1/tAVAV(min)
Units
Supply Current (Cycling Selected)
IDD1
Output Load
3240
Supply Current (Standby)
IDD3
IOH= -200 IOL=
High Level Output Voltage
0.05
Level Output Voltage High Level Input Voltage Data Level Input Voltage Data High Level Input Voltage Address Clocks Level Input Voltage Address Clocks Input Leakage Address, Output Leakage Address Lines CDATA Data In/Data
VIH_DI/O VIL_DI/O
IOLK
VOUT 3.47
Note:
Typical operating conditions: -30°C Tcase +105°C; 3.14 3.46 unless otherwise specified. Limit specified Tcase 80°C. Guaranteed, tested. Guaranteed design verified periodic characterization
Output Load Circuit
1.73
Read Cycle Timing Characteristics(1)
Test Read Cycle Time Address Access Time Output Hold After Address Change Chip Select Access Time Chip Select Output Active Chip Select Output Disable Chip Enable Access Time Chip Enable Output Active Chip Disable Output Disable Output Enable Access Time Output Enable Output Active Output Enable Output Disable Symbol tAVAV tAVQV tAXQX tSLQV tSLQX tSHQZ tEHQV tEHQX tELQZ tGLQV tGHQZ tGHQZ Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Maximum Minimum Maximum Maximum Minimum Maximum Limits Units
Notes: Test conditions: input switching levels VIL/VIH V/VDD -0.5 (CMOS), VIL/VIH 0V/3 (TTL), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading derate access times 0.02 ns/pF (typical). Tcase +90°C; 3.14 3.46 unless otherwise specified. Cycle time individual die.
Read Cycle Timing Diagram
tAVAV
Address Bottom
Valid Address tAVQV tSLQV tAXQX
S1/SN
tSLQX tEHQV
E1/EN
tSHQZ
Note:
tEHQX tGLQV
G1/GN
tELQZ
S1/SN, E1/EN, G1/GN respectively represent clock inputs.
tGLQX
Data Bottom
tGHQZ Valid Data
High Impedance
Write Cycle Timing Characteristics(1)
Minimum Maximum Minimum Minimum Minimum Minimum Minimum Minimum Minimum Minimum Maximum Minimum Minimum Minimum
Test Write Cycle Time Write Pulse Width Chip Select Write Data Setup Write Address Setup Write Data Hold After Write Address Setup Start Write Address Hold After Write Write Enable Output Disable Output Active After Write Write Disable Pulse Width Chip Enable Write
Symbol tAVAV tWLWH tSLWH tDVWH tAVWH tWHDX tAVWL tWHAX tWLQZ tWHQX tWHWL tEHWH
Limits
Units
Notse:
Test conditions: input switching levels VIL/VIH V/VDD (CMOS), VIL/VIH 0V/3 (TTL), input rise fall times input output timing reference levels shown Tester Timing Characteristics table, capacitive output loading Tcase +90°C; 3.14 3.46 unless otherwise specified. Cycle time individual die.
Write Cycle Timing Diagram
tAVAV
Address Bottom
Valid Address tAVWH tSLWH tWHAX
S1/SN
E1/EN
Note:
tEHWH
Bottom
tWLWH tWHWL tWHQX High Impedance tDVWH
1)S1/SN, E1/EN, G1/GN respectively represent clock inputs.
tAVWL
Data Bottom Data Bottom
tWLQZ
High Impedance
tWHDX High Impedance Valid Data High Impedance
Dynamic Electrical Characteristics
Read Cycle asynchronous operation, allowing read cycle controlled address, chip select through S18), chip enable through E18) (refer Read Cycle Timing diagram). perform valid read operation, both chip select output enable must chip enable write enable must high. output drivers controlled independently signal. Consecutive read cycles executed with through held continuously low, with through held continuously high, toggling addresses. address-activated read cycle, through through must valid prior coincident with activating address edge transition(s). amount toggling skew between address edge transitions permissible; however, data outputs will become valid tAVQV time following latest occurring address edge transition. minimum address activated read cycle time tAVQV When operated minimum addressactivated read cycle time, data outputs will remain valid until tAXQX time following next sequential address transition. control read cycle with through S18, addresses through must valid prior coincident with enabling through edge transitions. Address through edge transitions occur later than specified setup times through S18; however, valid data access time will delayed. address edge transition, that occurs during time when through low, will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tSHQZ time following disabling through edge transition. control read cycle with through E18, addresses through must valid prior coincident with enabling through edge transition. Address through edge transitions occur later than specified setup times through E18; however, valid data access time will delayed. address edge transition that occurs during time when through high will initiate read access, data outputs will become valid until tAVQV time following address edge transition. Data outputs will enter high impedance state tELQZ time following disabling through edge transition.
Write Cycle write operation synchronous with respect address bits, control governed write enable (W), chip select through S18), chip enable through E18) edge transitions (refer Write Cycle Timing diagrams). perform write operation, both through must low, through must high. Consecutive write cycles performed with through held continuously low, through held continuously high. least control signals must transition opposite state between consecutive write operations. write mode controlled three different control signals: through S18, through E18. three modes control similar except through through controlled modes actually disable during write recovery pulse. Only controlled mode shown table diagram previous page simplicity. However, each mode control provides same write cycle timing characteristics. Thus, some parameter names referenced below shown write cycle table diagram, indicate which control control switches high low. write data into RAM, through must held through must held high least tWLWH /tSLSH /tEHEL time. amount edge skew between signals tolerated control signals initiate terminate write operation. consecutive write operations, write pulses must separated minimum specified tWHWL /tSHSL /tELEH time. Address inputs must valid least tAVWL /tAVSL /tAVEH time before enabling W/S1 through S18/E1 through edge transition, must remain valid during entire write time. valid data overlap write pulse width time tDVWH /tDVSH /tDVEL, address valid write time tAVWH /tAVSH /tAVEL also must provided during write operation. Hold times address inputs data inputs with respect disabling W/S1 through S18/E1 through edge transition must minimum tWHAX /tSHAX /tELAX time tWHDX /tSHDX /tELDX time, respectively. minimum write cycle time tAVAV.
Radiation Characteristics
Total Ionizing Radiation Dose SRAM will meet stated functional electrical specifications over entire operating temperature range after total ionizing radiation dose 1x106 rad(Si). electrical timing performance parameters will remain within specifications after rebound 125°C extrapolated years operation. Total dose hardness assured wafer level testing process monitor transistors product using X-ray Co60 radiation sources. Transistor gate threshold shift correlations have been made between X-rays applied dose rate 1x105 rad(Si)/min 25°C gamma rays (Cobalt source) ensure that wafer level X-ray testing consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation SRAM capable writing, reading, retaining stored data during after exposure transient ionizing radiation pulse duration 1x109 rad(Si)/s, when applied under recommended operating conditions. ensure validity specified performance parameters before, during, after radiation (timing degradation during transient pulse radiation 10%), stiffening capacitance placed package between package (chip) with inductance between package (chip) stiffening capacitance kept minimum. there operatethrough valid stored data requirements, typical de-coupling capacitors should mounted circuit board close possible each device. SRAM will meet functional electrical specification after exposure radiation pulse duration 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that current conducted during pulse inputs, outputs, power supply significantly exceed normal operating levels. application design must accommodate these effects. Neutron Radiation SRAM will meet functional timing specification after total neutron fluence 1x1014 cm-2 applied under recommended operating storage conditions. This assumes equivalent neutron energy MeV. Soft Error Rate SRAM soft error rate (SER) performance <1x10-11 upsets/bit-day, under recommended operating conditions. This hardness level defined Adams worst case cosmic environment. Latchup SRAM will latch above radiation exposure conditions when applied under recommended operating conditions.
Radiation Hardness Ratings (1),(2)
Symbol
Characteristics Total Dose Single Event Upset Neutron Fluence Single Event Induced Latchup
Conditions
Minimum
Maximum
Units rad(Si)
-40°C Tcase 90°C 3.14 -40°C Tcase 90°C 3.46
Upsets/Bit-Day N/cm Immune
Notes: Measured room temperature unless otherwise stated. Verification test approved test plan. Device electrical characteristics guaranteed post irradiation levels 25°C. worst case particle environment, geosynchronous orbit, 0.025'' aluminum shielding. Specification using CREME code upset rate calculation method with thickness. Immune MeV/mg/cm
Tester Timing Characteristics
Configuration
CMOS Configuration
Input Levels*
VDD-
Output Sense Levels
VDD- High High
VDD- High High *Input rise fall times
High
High
Radiation Hardness Assurance
SYSTEMS provides superior quality level radiation hardness assurance products. excellent product quality sustained qualified operation which requires process control with statistical process control, radiation hardness assurance procedures rigid computer controlled manufacturing operation monitoring tracking system. SYSTEMS technology built with resistance radiation effects. product designed exhibit fails/bit-day worst case geosynchronous orbit under worst case operating conditions. Total dose hardness assured irradiating test structures every total dose exposure with Cobalt testing performed quarterly lots assure product meeting radiation hardness requirements.
Reliability
SYSTEMS' reliability starts with overall product assurance system that utilizes quality system involving employees including operators, process engineers product assurance personnel. extensive wafer acceptance methodology, using in-line electrical data well physical data, assures product quality prior assembly. continuous reliability monitoring program evaluates every wafer level, utilizing test structures well product testing. Test structures placed every wafer, allowing correlation checks within-wafer, wafer-to-wafer, from lot-to-lot. Reliability attributes CMOS process characterized testing both irradiated non-irradiated test structures. evaluations allow design model process changes incorporated specific failure mechanisms, i.e., carriers, electromigration, time dependent dielectric breakdown. These enhancements operation create more reliable product. process reliability further enhanced accelerated dynamic life tests both irradiated non-irradiated test structures. Screening testing procedures from customer followed qualify product. final periodic verification quality reliability product validated (Technology Conformance Inspection).
Screening Levels
SYSTEMS screen levels meet full compliant space applications. limited performance evaluation situations, SYSTEMS offers engineering screen level.
Standard Screening Procedure
Flow Wafer Acceptance Serialization Destructive Bond Pull Internal Visual Temperature Cycle Constant Acceleration PIND Radiography Electrical Test Dynamic Burn-In Electrical Test Static Burn-In Final Electrical Fine Gross Leak External Visual Level Sample Sample Comments Alternate Method Used Traceability MIL-STD-883, 2010, 2017
3.46V, 125°C, Hours Meets Group Fallout MIL-STD-883, 2009
Burn-In Circuit
Stress Methodology
There methods burn-in defined. "Static" burn-in, possible addresses written with logic half burn-in duration logic remaining half. "Dynamic" burn-in, possible addresses written with alternating high data. pins specified static dynamic burn-in lists driven through individual series resistors (1.6K ±10%). burn-in circuit diagram shown right. Voltage Levels Vin(0): level programmed signals High level programmed signals 3.45 (-0% +10%) pins tied this level Float pins tied this level Bottom Bottom Bottom
(±10%) 1.6K (±10%)
128K SRAM
Bottom Bottom DQ72 Bottom
Bottom
Listing dynamic burn-in listing shown right. square wave, MHz.
Input
Signal F/16 F/32
Input
Signal F/64 F/128 F/256 F/512 F/1024 F/2048
Input
Signal F/4096 F/8192 F/16384 F/32768 F/65536 F/131072
Input
Signal F/262144 F/524288 F/1048576 F/2097152
Packaging
128K SRAM offered custom 64-lead dual packages constructed multilayer ceramic (AI2O3) feature internal power ground planes. Optional capacitors mounted package maximize supply noise decoupling increase board packing density. These capacitors attach directly internal package power ground planes. This design minimizes resistance inductance bond wire package, both which critical transient radiation environment. pins must connected either VDD, active driver prevent charge build radiation environment. connect.)
308-Lead Quad Flat Pack
Lead Lead
Lead Lead
(Width)
(Pitch)
A=3.050 B=2.050 0.010 C=1.900 0.010 D=0.950 E=.025 0.002 F=.340 0.010 G=.250 H=.171
Notes: Part mark device specification. Dimensions inches.
Lead Lead Lead Lead
Lead width: .008 .002 Lead height: .005 +.0015, -.0010 Unless otherwise specified, tolerances .005".
Ordering Information
128K CMOS Memory Device (3.3 Number 198A854
Screen Designation 3=Engineering 7=Modified 8=Customer Specific Modified
SYSTEMS reserves right make changes products herein improve reliability, function design. SYSTEMS does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others.
Cleared Public Domain Release ©2001 SYSTEMS, Rights Reserved
SYSTEMS 9001, AS9000, 14001, Level Company 9300 Wellington Road, Manassas, 20110-4122 866-530-8104 0038_128K_72_2_SRAM.ppt
SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122

198A854 Other Read/Write Cycle Times (-30 90°C) Number Pending As

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