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RAD750Board Hardware User's Manual
234A533
Release Date December 2000
Copyright SYSTEMS
Rights Reserved
Document 234A533
RAD750 CompactPCI Hardware Users Manual
Notices
Before using this information product supports, sure read general information back cover this book. Trademarks following trademarks International Business Machines Corporation United States, other countries, both: PowerPC Logo PowerPC
following trademarks SYSTEMS United States, other countries, both: RAD750 following registered trademarks Industrial Computer Manufacturing Group United States, other countries, both: PICMG CompactPCI
Other company, product, service names trademarks service marks others.
Preliminary Edition (Version 2.10, 12/21/2000) This unpublished document RAD750Board Hardware Users Manual. Make sure using correct edition level product. This document contains information product under development SYSTEMS. SYSTEMS reserves right change discontinue this product without notice. SYSTEMS 2001. rights reserved.
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Preface Notice reviewers:
This update preliminary release this document. this time, some information contained this document state flux until completion first Flight unit bring-up, slightly behind hardware specifications. Items marked will filled subsequent release. When reviewing document, please keep following mind when providing comments: document presented usable order? need include test information? Since this intended all-encompassing, standalone document, there information that found somewhere else that should included here Does document provide enough information stand-alone? much detail been provided some areas? What document should that detail placed? What information missing should added? Does appendix belong separate document should merged into this document?
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Table Contents
USING THIS MANUAL AUDIENCE HARDWARE USERS MANUAL OVERVIEW MANUAL SOFTWARE USERS MANUAL RAD750 POWER DATA SHEETS REVISION HISTORY CONVENTIONS NOMENCLATURE TERMINOLOGY
OVERVIEW.5 RAD750 COMPACTPCI BOARD FUNCTIONS 2.1.1 RAD750 PowerPC Processor.6 2.1.2 Power Bridge Function 2.1.3 SUROM 2.1.4 Local Memory 2.1.5 Clocking.7 2.1.6 Power Regulation Consumption SPECIFICATION ORDERING INFORMATION SUROM DESCRIPTION
INSTALLATION INSTRUCTIONS.11 SAFETY PRECAUTIONS UNPACKING INSPECTING 3.2.1 Unpacking.11 3.2.2 Board Identification 3.2.3 Malfunction damage board connected components ARNINGS COMPACTPCI CONNECTOR KEYING.12 INSERTION LEVERS/ JACK SCREWS EDGELOCKS POWER REQUIREMENTS BACKPLANE DESIGN GUIDELINES POWER-UP OPERATIONAL DESCRIPTION 3.9.1 Power-up 3.9.2 Operation Description 3.9.3 Resetting RAD750 board.13 3.10 TROUBLESHOOTING 3.10.2 Debugging.16 3.11 RAD750 BOARD ELECTRICAL CONNECTORS 3.11.1 Connector Assignment 3.11.2 Connector Assignments.18 3.12 COMPACTPCI SLOT GUIDELINES MULTIPROCESSOR CONFIGURATIONS 3.13 COMPATIBILITY WITH RAD6000
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3.14 FRONT PANEL CONNECTOR 3.14.1 Assignments.20 HARDWARE ELECTRICAL.21 RAD750.21 4.1.1 RAD750 Microprocessor Features POWER 4.2.1 Environment.26 4.2.2 Compliance Summary.26 4.2.3 Architecture Overview 4.2.4 Power Features.27 4.2.5 Endian Conventions 4.2.6 RAD750 Interrupts Vector Interrupts.42 EXTERNAL ELECTRICAL INTERFACE.50 COMPACTPCI DEFINED SIGNALS 5.1.1 Interface 5.1.2 Central Resource (external) 5.1.3 Miscellaneous Interface.61 NON-PCI INTERFACES 5.2.1 JTAG Interfaces.66 5.2.2 UART Interface 5.2.3 Interrupts Discretes 5.2.4 Resets Clocks 5.2.5 Configuration Inputs POWER INTERFACES HARDWARE MECHANICAL LOCATION OVERVIEW GROUNDING 6.2.1 Structural Grounding 6.2.2 Circuit Grounding, General.79 6.2.3 Wire Shield Grounding 6.2.4 Grounding.79 MANUFACTURING ORGANIC MATERIALS INORGANIC MATERIALS PROCESSES BILL MATERIALS
DOCUMENTATION SUGGESTED READING 8.1.1 General PowerPC Information.88 8.1.2 PowerPC Documentation.88 APPLICABLE DOCUMENTS 8.2.1 Specifications.89 8.2.2 Standards
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8.2.3 Design Descriptions Design Guides.90 COMMENTS
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List Figures
Figure Notional C&DH Architecture using RAD750 board Figure RAD750 Board Block Diagram Figure Board identification label Figure RAD750 Microprocessor Block Diagram.22 Figure Power Chip Processor Board Figure Power Cores Figure Core Block Diagram Figure Core functional block diagram Figure Timer Functional Block Diagram.35 Figure Clock Generation Logic Figure Data Transfers Endian Mode. Figure Data Transfers Little Endian Mode.42 Figure Power Interrupt Collection Figure Power INT_L Interrupt Tree Figure Power Generation Tree.46 Figure Power Checkstop Generation Tree Vector Interrupt Tree Figure JTAG Backpanel Interface Figure JTAG RAD750 Interface Figure JTAG Slave Interface I/O.70 Figure Peripheral Device Interface I/O.71 Figure Isometric View RAD750 Board Layout Figure Standard View RAD750 Board Layout Figure RAD750 Board Layout
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List Tables
Table RAD750 CompactPCI board Maximum Power Consumption with 3.3± VDC, VDC, 125oC.8 Table RAD750 CompactPCI board Typical Power Consumption with VDC, VDC, 25oC.8 Table Specification RAD750 board (Flight Configuration) Table RAD750 board Part Number Listing Table CompactPCI Connector Signals Table CompactPCI Connector Pinouts Table Front Panel Connector Assignments.20 Table User Defined Register Definitions Table UART Baud Rate Programming Table Power Power Management Operational Modes Table Interrupt Register Definition.45 Table Error Mechanisms Table RAD750 board Interrupt Latencies.49 Table X2000 System Flight Computer Interface Signals Table X2000 System Flight Computer Non-PCI Signals Table Definition Table Table Organic Materials Table Inorganic Materials.83 Table Processes Table Bill Materials.85
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Using This Manual
This section does provide information product, features manual itself: structure, special layout conventions, related documents.
This manual separated into parts: main Hardware User's Manual (this document), Appendix. Appendix contains detailed register maps descriptions that part Power ASIC they utilized this board.
Audience Hardware Users Manual
Hardware Users Manual intended hardware software developers installing integrating RAD750 CompactPCI board into their systems. Software engineers developing troubleshooting code expected interface portion this manual. manual includes full descriptions dedicated locations, specific commands registers, programmed I/O, command partitioning. includes detailed memory with paging scheme.
Overview Manual
Hardware Users Manual provides comprehensive hardware guide your board. IMPORTANT: Take moment examine "Table Contents" Hardware Users Manual this documentation structured. This will value when looking information future. Hardware Users Manual includes: brief overview product, specifications, ordering information: Section "Overview". installation instructions powering board: Section "Installation Instructions". includes default configuration, initialization, connector pinouts. detailed hardware description: Section 4"Hardware Electrical". detailed description CompactPCI connector I/O: Section "CompactPCI Defined Signals". detailed mechanical description RAD750 board: Section "Hardware Mechanical". description RAD750 board manufacturing processes: Section "Manufacturing". Sources additional information, including latest version document: Section "Documentation".
This manual includes pictorial/diagrammatic description RAD750 board hardware internal functions. External interfaces included ensure logical written pictorial continuity completeness. descriptions written that reference other documents required immediate understanding. manual includes explanations internal hardware. Power internal controller, it's addressing modes, control memory mapping explained detail. Interrupts, status registers, fault types, causes protection included. Error detection correction strategies, used, detailed. test, power, electronic electrical interface specifics described. Mechanical, structural environmental requirements interfaces also detailed. troubleshooting tree included. implemented commands included. This manual includes detailed coverage explanation interrupts, memory mapping. Peculiar system interfaces such dedicated memory locations, channel register definitions, command code assignments definitions, multiple channel priorities, page register access detailed. Although this manual software tool, hardware handling process internal external hardware/software included. hardware/software configurations included. Interfaces peculiar test configuration clearly described illustrated.
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Hardware Users Manual addresses engineering model flight versions RAD750 board detail.
Software Users Manual
addition Hardware Users Manual, SYSTEMS provides software Users Manual Support Equipment Users Manual. These documents describe develop software RAD750 CompactPCI board, describe Board Support Package (BSP) SUROM products, recommended test development environment RAD750 board. Section obtain copies these documents.
RAD750 Power Data Sheets
RAD750 Power Data Sheets, which contains data sheets relevant configuring integrating board into systems, packaged separate binder ease handling. always shipped together with Hardware Users Manual. RAD750 Power Data Sheets includes following datasheets: LM/STC RAD750 LM/STC PowerPC-to-PCI Bridge Q-Tech Oscillator LM/STC Mbit SDRAM Stack EEPROM OmniRel Voltage DC/DC Converter
Revision History
REVISION HISTORY Initial release Updated Release Environmental Spec changes, minor updates DATE 9/9/99 4/28/00 12/20/00
REVISION
Conventions Nomenclature
following conventions used text this document: following conventions apply except were specifically noted. PowerPC terminology, multiple fields numbered from where LSB. terminology follows convention that MSB. When counting elements, first element designated element last element designated element N-1. Information particular importance bold typeface further highlighted NOTE reference. Signal names fully capitalized bold font: SIGNAL1 Active signals suffixed with symbol consistent with specification. other active signals suffixed with `_L'. Note that this does supersede coding requirement that active signal names coded using `_L' suffix: FRAME#, SIGNAL2_L Internal register names have leading caps bold font: Device Status Register field names have leading caps bold italicized font: Master numbers expressed decimal, except addresses memory register data, which expressed hexadecimal: 0x'0F'; binary: 0b'0110' `1', following programming language convention.
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denotes definitions. `xnnnn' denotes word definitions. multipliers 'k', have their conventional scientific engineering meanings *103, *106 *109, respectively. only exception this description size memory areas, when 'K', mean *210, *220 *230, respectively. When describing transfer rates, `k', mean *103, *106 *109, *210, *220 *230, respectively. Names external signals which have single destination form <source block>_<destination block>_<signal>. Names external signals which have multiple destinations form <source block>_<signal>.
Terminology
Description physical bank sub-bank) SDRAM which already received "Bank Activate" command, thereby selecting row. Once bank active, bank must precharged before another "Bank Activate" command issued select different row. memory scrubbing process which memory controller inserts extra memory read operations during idle cycles detect correct data errors. Application Specific Integrated Circuit memory part (or, more typically, group memory parts) which provides complete data vector. complete data vector typically contains 64-bits data bits. memory operation that does address open bank. Base Address register ordering data such that most significant byte stored lowest order address. Built-in Self Test 8-bit value. write which some bytes data beat stored memory. cache line consists double words bytes). this document character refers byte data that stored into FIFO. context internal SDRAM layout, column used conjunction with SDRAM select single (per data output bit) from SDRAM memory matrix. single unit data, usually data beat double word. 64-bit value. power management mode that consumes more power than Sleep Mode, less power than Normal Mode. also Nap, Normal Sleep Modes. 32-bit block data bytes) First First Out. Bank registers that store data, such that first data stored first data that read out. 16-bit value. Hardware Description Language language describing digital electronic systems. Joint Test Action Group Interface. Refers test interface standardized IEEE 1149.1a Controller associated logic that controls JTAG Slave(s) located outside function. ordering data such that most significant byte stored highest
following terms used throughout this document. Term Active Bank
Active Scrubbing ASIC Bank
Bank Miss Endian BIST Byte Byte-Enabled Write Cache Line Character Column
Data Beat Double word Doze Mode DWORD FIFO Half word JTAG JTAG Master Little Endian
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Term Description order address. endian ordering data never extends beyond byte group storage. least-significant Least-Significant Byte Logic `1'. process writing memory correct data error memory. process using extra spare) columns memory replace failed columns. Most-significant Most-Significant Byte transformation address convert between endian modes. power management mode RAD750 Power PCI, which consumes more power than Sleep Mode, less power than Normal Mode. also Normal, Doze Sleep Modes. typical (full-power) operational mode RAD750 Power PCI. also Doze, Sleep Modes. Each state state machine register bit. Same Active Bank. even. Even Parity indicates that number ones data parity even, likewise parity indicates that number ones odd. memory scrubbing process which Power memory controller only looks corrects data errors memory locations that Power read. Peripheral Component Interconnect. Refers Local defined Local Specification. Version specification developed Intel Corporation released 6/22/92. Special Interest Group (SIG) currently manages specification. Power Reset SDRAM command that closes open bank. VHDL construct that contain many signals different types. context internal SDRAM layout, single bit-line selected Bank Activate command. When used conjunction with SDRAM column, single (per data output bit) selected from SDRAM memory matrix. Register Transfer Level. Refers coding style that characterized explicit definition register register transfers within device being described. lowest power operational mode RAD750 Power PCI. also Normal, Doze Modes. Logic `0'. single internal bank SDRAM part with multiple internal banks. VHSIC Hardware Description Language standardized IEEE standard 1076 Very High Speed Integrated Circuit 32-bit value.
Marking State Memory Scrubbing Memory Sparing Munging Mode
Normal Mode One-hot State Machine Open Bank Parity
Passive Scrubbing
Precharge Record
Sleep Mode Spacing State Sub-bank VHDL VHSIC Word
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Overview
RAD750 CompactPCI board designed provide main computational capability spacecraft. Figure shows RAD750 CompactPCI board combined with other memory boards form main processing elements spacecraft avionics command data handling (C&DH) system.
Bulk Memory Bulk Memory
Spacecraft Spacecraft I/Oand TT&C TT&C
RAD750 RAD750
Payload Payload
JTAG Buses
Figure Notional C&DH Architecture using RAD750 board
RAD750 CompactPCI Board Functions
RAD750 PowerPC processor 3.3V/2.5V regulator, Power Bridge function oscillator, SUROM, Local Memory.
shown Figure RAD750 board consists following major functions:
following section divided into subsections corresponding top-level capabilities each these major functions.
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2.5V
RAD750
2.5V Regulator
3.3V
RAD750 JTAG Port
Address Control
Clocks, Interrupts Data Controls
Slave JTAG Port Memory Control UART Port Memory Address Memory Data
SUROM
Local Memory
Master JTAG Port Reset,Interrupts Discretes
Power Bridge
Clock
Configuration
Figure RAD750 Board Block Diagram
2.1.1 RAD750 PowerPC Processor
RAD750 functionally pin-for-pin compatible with commercial PowerPC 750. RAD750 PowerPC processor provides RAD750 board with following functions: PowerPC Instruction Architecture (ISA), Floating Point Unit which implements IEEE-754 floating point standard Kbytes instruction cache, Kbytes data cache, cache interface cache implemented RAD750 board).
more detailed description found Section 4.1.1.
2.1.2 Power Bridge Function
primary function Power Bridge provide bridge between native RAD750 Version compatible bus. Power Bridge provides RAD750 board Version compatible interface, burst mode with contiguous data transfers, arbitration resource control, Memory data address interface, Memory error detection correction (EDAC), Auto memory scrub, Cache snooping system memory accesses, 16550 compatible UART interface, RAD750, JTAG clock control, Three programmable timers which used provide operating system tick cycle start interrupts,
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watchdog timer, Interrupts discretes, Embedded micro-controller that control complex operations, Power saving modes match RAD750, Dual JTAG master interfaces, JTAG controller.
Power provides enhanced features over most used COTS PowerPC bridge chip (Motorola MPC-106), thus compatible with COTS bridge chip. More details Power chip found Section 4.2. addition, many registers Power chip discussed more detail Appendix this User's Manual.
2.1.3 SUROM
SUROM consists Kbytes nonvolatile EEPROM memory provides nonvolatile program store initial program load RAD750. SUROM organized 128K with bits data bits error correction code. SUROM memory directly addressed RAD750 internal master function Power PCI. This includes internal EMC, external JTAG master connected through backpanel Power JTAG port RAD750 board, initiator device connected RAD750 board. error correction code provides single error correction double error detection. Section provides brief description contents SUROM. more detailed description found software Users Manual (see Section directions obtaining manual).
2.1.4 Local Memory
Local Memory consists Mbytes Synchronous DRAM (SDRAM) provides processor program data store. local memory directly addressable RAD750 internal master function Power PCI. local memory organized with bits data bits error correction code. error correction coding provides single nibble error correction double nibble error detection that cluster events within SDRAM components will correctable. Local Memory, when placed self-refresh mode software, retains contents during reset duration long RAD750 CompactPCI board power input interrupted, however, scrubbing memory disabled during self-refresh errors will accumulating.
2.1.5 Clocking
RAD750 board uses single Oscillator drive Clock, Processor Clock Real Time Clock inputs Power chip. Section 4.2.4.7 provides more details clock generation logic, which contained Power chip. Details configuration status registers used control clock function found Appendix this User's Manual. RAD750 board configurable Oscillator RAD750 following speeds: using (Full speed mode) using using using 16.5 using divide (half speed mode) 8.25 using divide (quarter speed mode), 4.125 using divide (eighth speed mode).
Clock speeds higher than will available future date.
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RAD750 board configurable Oscillator following speeds: 16.5 8.25 4.125
RAD750 board uses Oscillator real time clock divided down
2.1.6 Power Regulation Consumption
RAD750 board draws required power from external 3.3V supply. power source expected regulated 3.3V maximum ripple with power converter switching frequency MHz. on-card regulator provides +2.5V required RAD750. RAD750 board power consumption characteristics listed Table Table Maximum power includes worst case temperature, voltage, post-radiation exposure. Typical power average value measured 3.3V +25°C system executing typical applications benchmarks. Table RAD750 CompactPCI board Maximum Power Consumption with 3.3± VDC, VDC, 125oC Mode Full-On Doze Sleep 14.5 11.5 10.0 16.5 8.25 4.125
Table RAD750 CompactPCI board Typical Power Consumption with VDC, VDC, 25oC Mode Full-On Doze Sleep 10.0 1.9W 16.5 8.25 4.125
Specification
Table provides high level specification RAD750 board Flight Unit. Table Specification RAD750 board (Flight Configuration) Item Processor Description RAD750
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Item Shared main memory Board CompactPCI interface Serial Counters/timers SUROM Additional features Power consumption Environmental Conditions: Temperature (operating) Temperature (storage) Humidity Thermal Shock Vibration Radiation +125 non-condensing minute 2000 12.3grms KRad Total dose Performance: RAD750 Read(*) Write(*) Dhrystone MIPS, 5.75 SPECint95 3.25 SPECfp95 Mbytes second Mbytes second Local Specification Rev. CompactPCI Specification Rev. D1.10 Description 128-MByte SDRAM with Conduction Cooled, double sided, CompactPCI RAD750 format PowerPC-to-PCI bridge, bit, MHz, full system slot function peripheral slot. JTAG UART front panel CompactPCI connector (factory option) Three 32-bit, programmable, Watchdog Timer KByte On-board programmable, Hardware write protection Programmable discrete Interrupts CompactPCI connector, Ready Parity CompactPCI connector Section 2.1.6 "Power Regulation Consumption"
Standards compliance
External controller with snooping HITS during transfer
Ordering Information
This section provides part numbering nomenclature RAD750 boards. Note that individual part numbers correspond combinations processor core frequencies, populated memory, environmental levels. availability RAD750 board variations, contact SYSTEMS Manassas, Virginia visit site www.rad750.com. Table shows designated part numbers that currently offered.
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Table RAD750 board Part Number Listing Part Number Designation 244A325 Commercial Configuration 234A510 Engineering Model Maximum Processor Frequency SUROM SDRAM Environmental Available
EEPROM EEPROM
Commercial Parts, different vendors Equivalent Flight burnin screening; Available Qualification Space Qualified
234A511 Flight Model
EEPROM
2001
SUROM Description
RAD750 boards contain embedded software initial program load RAD750 Power Embedded Microcontroller SUROM. embedded software contains following elements: Boot routine load image into DRAM transfer control this image Initialization routines push button reset Self test routines RAD750 Power ASIC Software interface drivers functions interfaces Power ASIC Memory test routines Exception handling routine(s) VxWorks loader Support software debug using UART interface Support hardware debug using JTAG interface
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Installation Instructions
Safety Precautions
ensure proper functioning product during usual lifetime, take following precautions before handling board.
Unpacking Inspecting
This section gives guidelines unpacking inspecting RAD750 Board.
3.2.1 Unpacking
Note: This product Class Electrostatic Discharge Sensitive. precautionary measures when handling antistatic envelope protects RAD750 boards. Observe antistatic precautions work approved antistatic workstation when unpacking board. RAD750 board shipped individual, reusable shipping box. When receive shipping container, inspect evidence physical damage. container damaged, request that carrier's agent present when carton opened. Keep contents packing materials agent's inspection notify SYSTEMS customer service department incident. Retain packing list reference. Assuming that there obvious damage, still want keep shipping carton case want ship RAD750 board elsewhere.
3.2.2 Board Identification
SYSTEMS RAD750 boards identified label non-component side board near front panel, front panel itself. This label gives revision state board, root code part number, board serial number, etc. shown following diagram:
Figure Board identification label
3.2.3 Malfunction damage board connected components
Electrostatic discharge incorrect board installation uninstallation damage circuits shorten their lifetime.
Before installing uninstalling board read this Installation section. Before installing uninstalling board CompactPCI rack: Check installed boards steps that have take before turning power. Take those steps. Ensure that board connected CompactPCI both connectors that power available both CompactPCI connectors. Finally turn power.
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Before touching integrated circuits ensure that working electrostatic free environment, tested wrist heel grounding strap.
Warnings
such
exceed maximum rated input voltages apply reversed bias assembly. conditions occur, toxic fumes produced destruction components.
Only RAD750 board backplanes that supply power both connectors. Failure observe this warning result damage board.
CompactPCI Connector Keying
According CompactPCI Specification 2.0, R2.1, boards marked keyed according their slot type power supply voltages. RAD750 board keyed 3.3V signaling board. RAD750 board will operate CompactPCI slot.
Insertion Levers/ Jack Screws
RAD750 board comes with insertion jacks front panel. Exercise caution when applying pressure levers during board insertion. Improper seating board will cause damage CompactPCI connectors. When plugging board out, press front panel, otherwise front panel damaged. handle plugging board out. With without insertion levers, apply more than pounds force when inserting this card CompactPCI rack.
Wedgelocks
RAD750 board conduction-cooled design, utilizing industry standard, multiple segment, wedgelock retainers stiffeners. RAD750 board operated without wedgelocks stiffeners plugged into commercial CompactPCI rack. wedgelocks stiffeners removed simply unscrewing them. When using board with wedgelocks, make sure that wedgelocks tightened down properly. Wedgelocks should tightened with torque wrench pounds torque. When using board without wedgelocks mounted, make sure there sufficient cooling that components damaged.
Power Requirements
RAD750 board operates single +3.3V power supply keyed operation 3.3V signaling CompactPCI system. Power supply must capable supplying minimum plus additional 3.3V power other voltages) other boards unit. voltage should highly regulated worst case ±10% (+/-5% recommended). operating temperature board -55°C +70°C noncondensing humidity). operation RAD750 board maximum operating temperature requires minimum airflow (linear feet minute) operated without wedgelocks installed.
Backplane Design Guidelines
RAD750 board fully compliant with CompactPCI assignments called CompactPCI Specification 2.0, R2.1. RAD750 board connects PCI_RDY_PAR Sideband Signal from Power bridge, which currently specified reserved. This signal added increased fault tolerance complies with specification sideband signals. Boards devices that utilize this signal need connect B09.
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Power-up Operational Description
This chapter describes power-up subsequent operation RAD750 board.
3.9.1 Power-up
Having configured backplane taken note system configuration suggestions previously, with RAD750 board firmly secured rack, power-up rack. SUROM RAD750 board, which controls operation after power-up, described RAD750 Software Reference Manual.
3.9.2 Operation Description
signal into processor board must held active while power applied. signal processor board will result automatic hardware flush reset ASIC's, leaving them their default state. Power will then take over operational control board desired initialization steps programmed into SUROM (checkout CPU, Initialization structures such address control registers, etc.). will then hand-off control initialization RAD750 releasing reset line processor. code that will well code processor programmable different each mission.
3.9.3 Resetting RAD750 board
following section will briefly describe each resets available RAD750 CompactPCI card. These resets are: Power Reset Reset JTAG TRST JTAG Reset Software Activated Reset RAD750 Software Activated Reset Card Internal Hardware Critical Error Reset Built Self Test (BIST) Reset
above reset types basic types reset classes board from hardware perspective. Software also provide some tailored Reset options through leaving fingerprints memory prior reset through looking state Programmable Interrupts Discretes (PIDS) into card select different grouping instructions during bring-up following reset. During speed change RAD750, bridge chip will generate HRESET signal RAD750 (not SRESET). reset will issued since that effected. source reset recorded BIST Core Status register that will flushed reset. Bits this register will indicate source reset follows: Logic BIST JTAG Reset Power internal Software Reset (soft reset) Internal Hardware Reset (Critical Error)
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3.9.3.1 Power Reset
Power Reset caused either signal from backpanel Reset signal from test connector being activated. This reset causes flush-reset registers Power their Reset Value outputs will placed safe state documented RAD750 CompactPCI Board Hardware User's manual. HRESET signal RAD750 also activated during POR. After flush reset completes, Power then used check board health reinitialize chip (dependent Power code written). Control generally then passed RAD750 complete bring-up sequence.
3.9.3.2 Reset
When Power configured central resource (primary input CENTRAL_RESOURCE `1') Power holds PCI_RESET# active while Power Reset state until Reset Reset register cleared. When Power central resource PCI_RESET# input Power reset some logic entire Power PCI. Power generates RST# when configured central resource BIST active, Reset Active Reset register. Reset Active read/write from both Power internal interfaces Power Internal register space. Additionally, this automatically under following conditions: Data Phase Timeout detected Arbitration Latency Timeout detected
Reset Active flush reset. Once this (and RST# active), only reset Power internal interface. software's responsibility ensure that minimum reset requirement Specification met. With exception external tri-state control, Power responds reset same manner, whether generating responding reset handled broad side reset Power PCI, following affects: defined registers reset states required Specification. non-PCI defined internal registers remain unchanged. state machines returned their idle states. Power internal Master completes current transaction(s) then terminate. internal buffers invalidated with exception Power internal reads writes internal register space.
During reset, Power internal access internal register space. However, defined registers will held reset long RST# active, writes these registers have affect. attempted Power internal access other than internal register spaces during reset causes Invalid Power internal access error. This results error signaling back Power internal bus, setting Invalid Power internal Access Status register, INTERRUPT_OUT signal going active masked Status Mask register.
3.9.3.3 JTAG TRST
Power tri-states Master JTAG Tap-Reset outputs (JTM_TRST_L JTMS_TRST_L) while Power Reset state. JTM_TRST_L JTMS_TRST_L will pulled down card force
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JTAG interface attached ASICs into Test-Logic-Reset state during anytime TRST_L tristated. When JTMS_TRST_L active Power PCI's JTAG slave port will forced Test-LogicReset state. This signal effect other Power logic.
3.9.3.4 JTAG Reset
Power reset JTAG slave interface using clock control instruction code `010') JTAG Address (2:0) `011'. This Reset identical Power Reset.
3.9.3.5 Software Activated Reset RAD750
Power bridge chip also contains RAD750 Discretes register which initiate HRESET signal RAD750 setting register. This register used part error recovery routines, clock change routines, etc. determined application.
3.9.3.6 Software Activated Reset Card
addition, write 0x`BF86 0040' from interfaces initiates full reset Power PCI.
3.9.3.7 Internal Hardware Critical Error Reset
When Power internal logic generates critical error, Power attempts handle error vector interrupt Power cannot successfully resolve error condition, will issue software reset. internal error prevents Power from accessing memory, Power PCI's Watchdog timer expires, causing internal hardware generated reset.
3.9.3.8 Built Self Test (BIST) Reset
Power enters BIST Reset state just before exiting BIST. Only bistable logic will reset during BIST reset. During BIST reset Power initializes internal registers their Reset Value with exception Clock Test registers JTAG Controller.
3.10 Troubleshooting
This chapter gives some suggestions what when your RAD750 board doesn't work. Don't panic! step-by-step method looking problem. diagnose problem type (i.e., hardware software). else fails, phone your nearest SYSTEMS technical support office assistance.
3.10.1.1
Step Power
Check that your enclosure's mains power lead plugged into main outlet into chassis. Remove board during remainder power debug procedure. Check that have switched mains system. Check that receiving power from main outlet (test this with lamp example). Ensure that fuses have blown. system refuses start this suggests problem with power supply. essential that only qualified personnel deal with problem from
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3.10.1.2
Step Power Unexpected Behavior
Power equipment off. Ensure that board firmly seated secured rack that male/female connectors mate together correctly. Check links board system backplane. unsure which link configuration use, default configuration initially. Check that CompactPCI rack diode terminators, these built (the manual your rack should tell whether terminators built in). Check that power supply within CompactPCI limits +3.3V, +5V, +12V -12V with digital voltmeter. Note: RAD750 board only operates +3.3V. Check that there only board configured system controller that this slot keyed receive Check that there vacant slots rack without jumpers that automatic daisy chaining backplane being used). still getting unexpected behavior, removing other CompactPCI boards from rack proving RAD750 board's operation isolation, then adding board time until offending element found.
3.10.1.3
Step Power Terminal Display Support Equipment
Check that cables plugged correctly. have made your cable, check that pinout wiring correct. Note that lines switched cable. Section 5.2for description cable. Check that connections tight. Check that terminal receiving power Check that terminal Kbaud, bits/character, stop bit, parity disabled).
3.10.1.4
Step Overheating
Check that grilles blocked chassis, either internally externally. Check that fans working. Clean replace filters fitted fans. Check that there free airflow around chassis exterior (i.e., should alcove other confined space, thick pile carpet). Check that enclosure next radiator other heat source.
3.10.1.5
Step RAD750 board Locks
resetting RAD750 board powering system down then again.
3.10.2 Debugging
When debugging software, disable caches make tracing software execution easier.
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3.11 RAD750 Board Electrical Connectors
connectors load shield board. This shield covers IEC-1076 connector help provide impedance return path ground between board CompactPCI backpanel. lower shield option that provided IEC-1076 required loaded protrudes into interboard separation plane. Descriptions signals connectors found Section
3.11.1 Connector Assignment
connector primary interface RAD750 board assembly resides main backpanel JTAG signals mostly routed this connector. following color coding used Table Table Black Power Ground Assignments Base CompactPCI System Mappings Blue Fully Compliant Mappings Unused 64-bit System Signals Green Mapping onto Reserved Signals Purple Unused Reserved Signals Table CompactPCI Connector Signals
12-14
3.3V 3.3V AD12 3.3V SERR# 3.3V DEVSEL# 3.3V
REQ64# AD15 SDONE FRAME#
ENUM# PID20 V(I/O) 3.3V V(I/O) AD14 3.3V SBO# V(I/O) IRDY# AREA
3.3V AD11 STOP#
ACK64# C/BE0# AD10 AD13 C/BE1# PERR# LOCK# TRDY#
AD18 AD21 C/BE3# AD26
AD17 IDSEL
AD16 3.3V AD23 V(I/O)
AD20 AD25
C/BE2# AD19 AD22 AD24
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AD30 REQ# BRSV BRSV INTA# PID16 UART_OUT2
AD29 RDY_PARITY INTB# PID17 -12V
AD28 3.3V RST# V(I/O) INTC# PID28 TRST_L
INTP-PID14 +12V
AD27 AD31 GNT# INTS-PID15 INTD# PID29
3.11.2 Connector Assignments
connector provides additional signals resource controller user-defined pins backpanel. Table CompactPCI Connector Pinouts
CLK6 CLK5 BRSV BRSV ROM_ON_PCI BRSV UART_OUT1
I2C_1 CHAS_GND_0 PID21
CLK7 UART_RTS_L I2C_0 PRST# DEG# PID18 FAL# PID19 PID31 V(I/O) PID25 V(I/O) PID26 V(I/O) PID27 V(I/O)
UART_RX_DAT REQ6# REQ5# PID08 PID09 PID10 PID11
JTMS_MSTR_E UART_CTS_L UART_TX_DAT GNT6# CHAS_GND_1 GNT5# PID30 PID00 PID01 PID02 PID03 PID04 PID05 PID06
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V(I/O) CLK4 CLK2 CLK1
PID22 POR_N CLK3
PID24 V(I/O) PID23 GNT3 SYSEN# REQ1#
REQ4# GNT2# GNT1#
PID07 PID12 PID13 GNT4# REQ3# REQ2#
3.12 CompactPCI Slot Guidelines Multiprocessor Configurations
Power Bridge chip designed SYSTEMS used RAD750 processor card enhanced over commercially available MPC-106 chip allow multiple processor cards combined single compact backpanel. Cards constructed using Power Bridge chip used either system controller non-system controller slot without changes being required card design. Power chip RAD750 processor board uses SYS_EN signal from compact backpanel determine system controller backpanel. When this signal active (i.e., card plugged into slot standard CompactPCI backpanel), Power bridge chip board will controller (arbiter). When acting controller, Power will supply then release (under control) reset signal rest backpanel. Each Power chip contains Base Address Registers (BARs) which used follows: BAR1 defines base address system memory. size selectable external chip pins GByte, GByte, MByte, 256Mbyte. Furthermore, internal Power configuration register (SM_SIZE) used determine number KByte pages that mapped bus. number pages ranges from 32768. BAR2 defines base address internally architected Power registers. defines MByte Memory region. Write access lower half BAR2 memory region from enabled BAR2_WE stored configuration space. following example BARs: BAR1 0x'1000 0000' with window size 256MB. requests between 0x'1000 0000' 0x'1FFF FFFF' translated memory (local memory) requests between 0x'0FFF FFFF' BAR2 0x'2000 0000' requests between 0x'2000 0000' 0x'200F FFFF' translated memory (Power register) requests between 0x'BD80 0000' 0x'BF8F FFFF'.
BARs must order access Power target. Both BARs will reset base address zero they must avoid conflicts. local processor BARs once Reset removed, other masters BARs using configuration cycles. Power Bridge chips used designs, such memory cards, which contain processor. these applications, outside master would generally used supply configuration cycles configure registers required address range.
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3.13 Compatibility with RAD6000
RAD750 processor card fully compatible with previous RAD6000 based product set. Power Bridge backward compatible version used RAD6000 family designs. required endian conversions controlled software through endian conversion hardware Power bridge.
3.14 Front Panel Connector
Front Panel connector provides external UART, debug test signals that brought front panel. front panel connector wired shown Table front panel connector Nanonics Dualobe connector.
3.14.1 Assignments
Table Front Panel Connector Assignments Signal JTM_TDO JTM_TDI JTM_TCLK JTM_TMS CPU_CKSTP_L JTS_TDI JTS_TDO JTS_TMS JTS_TCLK JTS_PROBE_PR_L X_SYS_OSC Signal JTM_TRST_L JTM_POWER JTM_SRESET_L JTM_RESET_L JT7_MSTR_EN_IN UART_RX_DATA UART_TX_DATA UART_RTS_L UART_CTS_L JTS_TRST_L X_SYS_OSC_SEL_L
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Hardware Electrical
This section describes electrical functional characteristics RAD750 board. Included descriptions RAD750, memory maps, register descriptions, etc. Details register section predominantly about Power chip.
RAD750
Users should refer Section
RAD750 functionally equivalent PowerPC 750. information PowerPC Users Manual.
This section briefly describes features general operation RAD750 provides block diagram showing major functional units. RAD750 implementation PowerPC microprocessor family reduced instruction computer (RISC) microprocessors. RAD750 implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits, floating-point data types bits. RAD750 superscalar processor that complete instructions simultaneously. incorporates following execution units: Floating-point unit (FPU) Branch processing unit (BPU) System register unit (SRU) Load/store unit (LSU) integer units (IUs): executes integer instructions. executes integer instructions except multiply divide instructions.
ability execute several instructions parallel simple instructions with rapid execution times yield high efficiency throughput RAD750-based systems. Most integer instructions execute clock cycle. pipelined, tasks performs broken into subtasks, then implemented three successive stages. Typically, floating-point instruction occupy only three stages time, freeing previous stage work next floating-point instruction. Thus, three single-precision floating-point instructions execute stage time. Double-precision instructions have three-cycle latency; double-precision multiply multiply-add instructions have four-cycle latency. Figure shows parallel organization execution units (shaded diagram). instruction unit fetches, dispatches, predicts branch instructions. Note that this conceptual model that shows basic features rather than attempting show features implemented physically. RAD750 independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed caches instructions data independent instruction data memory management units (MMUs). Each 128-entry, two-way set-associative translation lookaside buffer (DTLB ITLB) that saves recently used page address translations. Block address translation done through four-entry instruction data block address translation (IBAT DBAT) arrays, defined PowerPC architecture. During block translation, effective addresses compared simultaneously with four entries. cache supported with on-chip, two-way, set-associative memory. External, synchronous SRAMs then added data storage. external SRAMs accessed through dedicated cache port that supports single bank MByte synchronous SRAMs. cache implemented RAD750 board. RAD750 32-bit address 64-bit data bus. Multiple devices compete system resources through central external arbiter. RAD750's three-state cache-coherency protocol (MEI) supports exclusive, modified, invalid states, compatible subset MESI four-state protocol, operates coherently systems with four-
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state caches. RAD750 supports single-beat burst data transfers memory accesses memory-mapped operations. RAD750 four software-controllable power-saving modes. Three static modes, doze, nap, sleep progressively reduce power dissipation. When functional units idle, dynamic power management mode causes those units enter low-power mode automatically without affecting operational performance, software execution, external hardware. RAD750 also provides thermal assist unit (TAU) reduce instruction fetch rate limiting power dissipation.
Figure RAD750 Microprocessor Block Diagram
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4.1.1 RAD750 Microprocessor Features
This section lists features RAD750. interrelationship these features shown Figure
4.1.1.1 Overview PowerPC RAD750 Microprocessor Features
Major features RAD750 follows: High-performance, superscalar microprocessor many four instructions fetched from instruction cache clock cycle many instructions dispatched clock many instructions execute clock (including integer instructions) Single-clock-cycle execution most instructions independent execution units register files featuring both static dynamic branch prediction 64-entry (16-set, four-way set-associative) branch target instruction cache (BTIC), cache branch instructions that have been encountered branch/loop code sequences. target instruction BTIC, fetched into instruction queue cycle sooner than made available from instruction cache. Typically, fetch access hits BTIC, provides first instructions target stream. 512-entry branch history table (BHT) with bits entry four levels predictionnot-taken, strongly not-taken, taken, strongly taken Branch instructions that update count register (CTR) link register (LR) removed from instruction stream. integer units (IUs) that share thirty-two GPRs integer operands execute integer instruction. execute integer instructions except multiply divide instructions (multiply, divide, shift, rotate, arithmetic, logical instructions). Most instructions that execute take cycle execute. single-entry reservation station. Three-stage Fully IEEE 754-1985-compliant both single- double-precision operations Supports non-IEEE mode time-critical operations Hardware support denormalized numbers Single-entry reservation station Thirty-two 64-bit FPRs single- double-precision operands Two-stage Two-entry reservation station Single-cycle, pipelined cache access Dedicated adder performs calculations Performs alignment precision conversion floating-point data Performs alignment sign extension integer data Three-entry store queue Supports both big- little-endian modes handles miscellaneous instructions Executes logical Move to/Move from instructions (mtspr mfspr) Single-entry reservation station Rename buffers
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rename buffers rename buffers Condition register buffering supports writes clock Completion unit completion unit retires instruction from six-entry reorder buffer (completion queue) when instructions ahead have been completed, instruction finished execution, exceptions pending. Guarantees sequential programming model (precise exception model) Monitors dispatched instructions retires them order Tracks unresolved branches flushes instructions from mispredicted branch Retires many instructions clock Separate on-chip instruction data caches (Harvard architecture) 32-Kbyte, eight-way set-associative instruction data caches Pseudo least-recently-used (PLRU) replacement algorithm 32-byte (eight-word) cache block Physically indexed/physical tags. (Note that PowerPC architecture refers physical address space real address space.) Cache write-back write-through operation programmable per-page per-block basis Instruction cache provide four instructions clock; data cache provide words clock Caches disabled software Caches locked software Data cache coherency (MEI) maintained hardware critical double word made available requesting unit when burst into linefill buffer. cache nonblocking, accessed during this operation. Level (L2) cache interface (The cache implemented RAD750 board.) On-chip two-way set-associative cache controller tags External data SRAMs Support 256-Kbyte, 512-Kbyte, 1-Mbyte caches 64-byte (256-Kbyte/512-Kbyte) 128-byte MByte) sectored line size Supports flow-through (register-buffer), pipelined (register-register), pipelined late-write (register-register) synchronous burst SRAMs Separate memory management units (MMUs) instructions data 52-bit virtual address; 32-bit physical address Address translation 4-Kbyte pages, variable-sized blocks, 256-Mbyte segments
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Memory programmable write-back/write-through, cacheable/non-cacheable, coherency enforced/coherency enforced page block basis Separate IBATs DBATs (four each) also defined SPRs Separate instruction data translation lookaside buffers (TLBs) Both TLBs 128-entry, two-way associative, replacement algorithm TLBs hardware-reloadable (that page table search performed hardware) Separate interface units system memory cache interface features include following: Selectable bus-to-core clock frequency ratios 2.5x, 3.5x, 64-bit, split-transaction external data with burst transfers Support address pipelining limited out-of-order transactions Single-entry load queue Single-entry instruction fetch queue Two-entry cache castout queue No-DRTRY mode eliminates DRTRY signal from qualified grant. This allows forwarding data during load operations internal core cycle sooner than DRTRY enabled. cache interface features (The cache implemented RAD750 board) include following: Core-to-L2 frequency divisors 1.5, 2.5, Four-entry cache castout queue cache 17-bit address 64-bit data Multiprocessing support features include following: Hardware-enforced, three-state cache coherency protocol (MEI) data cache. Load/store with reservation instruction pair atomic memory references, semaphores, other multiprocessor operations Power thermal management Three static modes, doze, nap, sleep, progressively reduce power dissipation: Doze functional units disabled except time base/decrementer registers snooping logic. mode further reduces power consumption disabling snooping, leaving only time base register powered state. Sleep internal functional units disabled, after which external system logic disable SYSCLK. Thermal management facility provides software-controllable thermal management. Thermal management performed through three supervisor-level registers RAD750-specific thermal management exception. Instruction cache throttling provides control instruction fetching limit power consumption. Performance monitor used help debug system designs improve software efficiency. In-system testability debugging features through JTAG boundary-scan capability
Power
Power ASIC single support chip required System Flight computer card. provides bridge from processor local memory, SUROM, 3.3V 32-bit interface
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(compatible with compact standard). 16550 compatible UART, 1149.1a JTAG master slave interfaces. Figure Power Chip Processor Board Power designed support embedded space applications thus features such timers, programmable discrete I/O, programmable interrupt controller, simple embedded microcontroller functions including fault handling recovery. Power ASIC operates majority functions architecture supports operating asynchronous chip clock frequency.
33MHz
RAD750
Power PCI/Mem. Bridge
UART
SDRAM SRAM
4.2.1 Environment
functional block diagram Power chip incorporated onto processor board shown
RAD750
33MHz
Power PCI/Mem. Bridge
UART
SDRAM SRAM
Figure main function Power ASIC bridge single support chip PowerPC processor connected bus. Both PowerPC 740/750 microprocessors supported Power design. chip architecture extremely flexible supports multiple memory types several schemes.
4.2.2 Compliance Summary
Power supports connection either PowerPC PowerPC 740/750 processor chip. interface compatible with version Local specification memory interface compatible with JEDEC standard SDRAM Architectural Operational Features.
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4.2.3 Architecture Overview
Power functions partitioned into functional blocks cores. On-Chip-Bus (OCB) used interconnect cores. configured crossbar switch prevent from becoming performance bottleneck. Each core uses common interface, known stub. cores follows: PCI, P60X, MCC, EMC, CAT, MISC, JTAG Master (two copies), JTAG Slave, UART, Connection Medium. P60X, PCI, cores have both master slave capabilities therefore have access memory internal registers excluding JTAG Slave registers. JTAG Slave core master capable only therefore access memory internal registers. UART, JTAG Masters, MISC, cores slave only OCB. cores except JTAG's have capability generating interrupt when error encountered service required. Core interrupts collected MISC Interrupt Collection Register MISC Interrupt Status Register.
Memory JTAG Master
Cntl
P60X
Master Slave
Master Slave
Master Slave
JTAG Master
Slave
Connection Medium
Slave
Slave
Master
Slave
Slave
UART
JTAG Master
JTAG Slave
Misc
(CAT) Power
JTAG Boundary
UART
JTAG Master
JTAG Slave Probe Present
PID's
Clocks/Reset
Figure Power Cores
4.2.4 Power Features
Power provides enhanced features over most used COTS PowerPC bridge chip (Motorola MPC-106), thus compatible with COTS bridge chip. following sections provide details functions contained design. Details individual register definitions found appendix this document.
4.2.4.1
interface Power ASIC provides 32-bit master target interface, also includes optional central resource function. central resource function enabled when RAD750 CompactPCI board placed System Controller slot Compact backpanel.
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core supports asynchronous operation relative remainder logic RAD750 CompactPCI board. Internal buffering data command queues provided. Some general features Interface supports are: 32-bit address data path operating frequency Asynchronous application interface Zero wait-state burst transactions types abort, retry, disconnect Delayed transactions Posted memory writes Configurable prefetching read data 64-bit interface remainder RAD750 CompactPCI board
block diagram core shown Figure indicates interconnections between various features design. core contains User Defined registers known User Defined Registers These registers supply configuration controls other areas Power chip described Table general, these used maintain compatibility with commercial MPC-106 bridge chip.
Core
Slave Stub
Master Stub
Write Buffer
Read Buffer
Buffer Control
Write Buffer
Read Buffer
Buffers Control
Initiator Internal Registers
Target
Blocks
Monitor
Arbiter
Interface
Boundary
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Figure Core Block Diagram Table User Defined Register Definitions
Bits
USER_DEFINED_A(0) USER_DEFINED_B(11) USER_DEFINED_B(5) USER_DEFINED_C(27) USER_DEFINED_C(26) USER_DEFINED_C(19:18) USER_DEFINED_C(15) USER_DEFINED_C(3:2) 4.2.4.1.1 Arbiter
Function
P60x_ERROR_EN MISC_MCP_ENABLE P60x_ENDIAN_MODE P60x_NO_SNOOP_EN P60x_FF0_LOCAL P60x_SNOOP_WS P60x_DBWO_EN P60x_APHASE_WS
Destination
Core Misc Core Core Core Core, Core Core Core
Comments
error enable Machine Enable Check Interrupt
Defines endian mode Enables Snoop P60X Additional SUROM location control Snoop wait states Enables DBWO Address wait states
When RAD750 CompactPCI board placed system controller slot standard Compact backpanel will central resource bus. central resource, Power will provide central arbitration accesses. three level arbitration scheme used. based fixed priorities within level between levels, with fairness built higher priority levels ensure that priority device locked should higher priority devices continuously request bus. eight masters requesting access simultaneously supported. Power chip considered these eight masters. Each eight sets Request/Grant signals assigned three priority levels disabled) using Arbitration Priority Register ASIC. request/grant pair were disabled, that master would never granted bus. This violates specification's arbitration fairness requirement, however provides capability central resource turn errant master should that necessary. three arbitration priority levels have fixed priorities relation each other with level having highest priority level three lowest. Within each level, priorities also fixed with lowest order request having highest priority. (i.e., REQ0# REQ1# programmed same arbitration level, ARB_REQ0# higher priority.) Level level have fairness built This means that addition request/grant pairs assigned level Arbitration Priority Level register, level also contains level fairness chit. level fairness chit lower priority than other level requesters, enables lower level requester granted before level requester that already used granted second time. Once lower level requester used bus, level requesters given opportunity take another turn before level fairness chit used again. Similarly, level contains level three fairness chit, allowing level three device turn after level requesters have used bus. case where level requesters have already
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used bus, level requesters have just finished using bus, then device from level three allowed since both level level chits would active that time. arbiter always grants highest priority `non-masked' requester. requester masked arbiter soon becomes owner bus. requester becomes unmasked arbiter when there longer unmasked devices level requesting including fairness chit. devices requesting bus, then arbitration algorithm essentially reset. that point, multiple devices request same time, highest priority requester would always granted first regardless previous ownership parking). Also, note that only device requesting bus, will granted continuously, until second device requests (even though still essentially `masked' using previous definition). absence active requests, arbiter parks last used requester. After reset, when there `last used requester', Core drives AD(31:0), C/BE(3:0)#, although actually parked GNT(7:0)# active). 4.2.4.1.2 Compliance Summary
interface designed requirements forth Local Specification, 2.2. deviations from Specification detailed here. This section does describe optional features that were implemented. Specification Chapter Electrical Specification: logic Power chip does enforce minimum length RST# when generating reset central resource. Software must adhere this requirement. Specification Chapter Mechanical Specification: These expansion card requirements dealt with card level. interface contained ASIC does claim compliance requirements Chapter Specification. Specification Chapter Specification: current version Power dies support PCI. M66EN signal generated ASIC. Transaction Ordering: core Power ASIC only order transactions with respect interface. knowledge what goes beyond OCB. Therefore, possible that transaction ordering entire ASIC device violated assuming that there buffering beyond from core. SERR#: Specification defines SERR# type signal (i.e., open drain). only discusses SERR# output. Core defines this signal bi-directional open drain signal that when acting Central Resource bus, latch active SERR# input report When central resource, Core ignores SERR# input. Subsystem Specification requires that Subsystem Vendor Subsystem registers loaded with valid information prior software accessing them Configuration Space. specification suggests responding with Retry reads this register until that happens. Core allows these registers written from interface, provides logic prevent from reading these registers prior that occurring. Core relies system specific software ensure that this requirement met. Transaction Ordering Configuration Accesses: Core does allow configuration access participate transaction ordering. That configuration reads writes occur without regard whether data posted buffers. Specification implies that target read should flush write buffers, including configuration reads. This `noncompliancy' precludes Core internal registers `flags' data completion. example, device were execute memory write Core which posted, then `flag' Core internal registers, another device could read `flag' before posted write data written OCB. Similarly, configuration write Core internal configuration type
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register could occur before posted data flushed OCB, potentially inadvertently modifying transfer. Ordering Delayed Transactions: Core Power ASIC does support Rule appendix which states that Posted Memory Write must allowed pass Delayed Request avoid deadlocks. lack retry capability interface prohibits adherence this rule. However, this rule stated prevent particular deadlock scenario that occurs when PCI-to-PCI bridge that supports delayed transactions used with PCI-to-PCI bridge that doesn't support delayed transactions. Core therefore does support this configuration. Memory Write maximum Completion Time Limit: This system level requirement beyond scope Interface Power chip. Status Register: Core enhances error reporting including Status register. compile error bits into same register (the Status register), Core mirrors bits from specification defined Status register into Status register. mirroring these bits, Core allows some Status register bits reset writing `1's corresponding locations Status register. This action considered compliant. Specification requires agent driving data drive even parity PAR. Power violates this requirement when internal register data intended contains parity. Core passes internal register parity PCI. Under normal conditions internal register parity errors), Core does pass even parity required. Core does fully support transaction ordering Target that core does prohibit Target reads from completing when posted Slave write data exists Slave Write Buffer Slave write completed prior Target read having completed OCB.
4.2.4.2 Interface
Interface core contained Power (shown Figure transmits receives data between used RAD750, memory controller interface internal Power PCI, Power PCI's internal Chip (OCB). provides bridge from processor memory core well bridge from Chip memory core. functional unit master (PCI, JTAG Slave, EMC) capability accessing memory core core interface. core ensures processor cache coherency these accesses snooping processor bus. core also supports functions such BIST, boundary scan capabilities.
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CORE
Memory Controller Core Subcore Slave Stub Subcore
Memory Request Slave Stub
Endian Conversion
Boundary Subcore
Master Stub Subcore
Master Stub
Config Registers
Error Misc
Slave Stub Subcore Subcore
Subcore Boundary Subcore
Figure Core functional block diagram major functions core are: Separate Master Slave interfaces internal Power Subcore Interface Master Slave Arbitrator Memory Request Interface Configuration Register Block Error Interface Endian Conversion Logic (see Section 4.2.5 details) Clock Test Logic Interface
4.2.4.3 Memory Interface
Power supports banks memory components though only banks used RAD750 CompactPCI board. While banks combination three types memory (SRAM, PROM/EEPROM, SDRAM), RAD750 CompactPCI board, Bank contains 256KB EEPROM SUROM Bank contains 128MB SDRAM.
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Power highly configurable internal registers. Each bank programmed error correction mode (SECDED, Parity, Nibble Correction), timing parameters, etc. Advanced functions including built scrubbing initialization memory ranges supported. Sparing memory devices fault tolerance also supported. RAD750 board provides ability enable disable local SUROM memory EDAC mechanisms. local SUROM memory EDAC mechanisms enabled when board reset. RAD750 board provides visibility into number memory corrections address correction. RAD750 board counts single nibble errors. Multiple errors that uncorrectable generate maskable interrupt RAD750. RAD750 board provides ability program different access times SUROM DRAM. RAD750 board supports writing SUROM Error Injection. Either disabled following different non-trivial software sequence.
4.2.4.4 JTAG Interfaces
Power contains three IEEE 1149.1 test ports. first slave port, which used directly connect Power JTAG tester. next JTAG master port, which used allow Power perform JTAG test initialization functions PowerPC CPU. `Probe Connected' signal provided along with this port allow connection disabled should direct connection JTAG tester PowerPC desired test operations. last JTAG port combined Master/Slave port, which used incorporate Power into JTAG test ring. general, this port that would used Master JTAG driving ASIC JTAG ports system.
4.2.4.5 UART
Power contains 16550 compatible UART interface. ASIC itself support full suite signals including: Serial Data Serial Data Out, Request Send (RTS), Clear Send (CTS), Data Ready (DSR), Data Carrier Detect (DCD), Ring Indicator (RI), Data Terminal Ready (DTR) general purpose output signals. However, four these signals (DSR, DCD, DTR) brought RAD750 CompactPCI board card. Details control usage UART function Power ASIC found RAD750 CompactPCI board Software User's Manual. UART function Power contains Baud Rate Generator that takes clock input divide divisor from 216-1. This clock input chip, RAD750 CompactPCI board system clock divided output frequency Baud Generator Baud Rate [divisor (frequency input) (baud rate 16)]. divisor stored 8-bit latches called Divisor High Register Divisor Low. These divisor latches must loaded during initialization ensure proper operation Baud Rate Generator. divisor zero recommended. Upon loading either these registers, 16-bit Baud rate counter immediately loaded. Table below shows example desired baud rates their necessary divisors four potential input clock frequencies. accuracy desired baud rate dependent input frequency chosen baud rate. formula percent error follows: (Input frequency Divisor *16) Desired Baud Rate Percent Error.
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Table UART Baud Rate Programming 8.25 BAUD RATE 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 28800 38400 56000 128000 256000 Divisor Error (Decimal) 10312 6875 4687 3834 3437 1719 0.005 0.000 0.011 0.009 0.015 0.015 0.044 0.073 0.160 0.073 0.073 0.160 0.394 0.535 0.535 0.535 0.535 3.290 2.307 0.708 0.708 4.125 Divisor Error (Decimal) 5156 3437 2344 1917 1719 0.005 0.015 0.011 0.009 0.015 0.044 0.073 0.073 0.160 0.073 0.394 0.535 0.535 0.535 0.535 3.290 0.535 4.088 7.924 0.708 0.708 2.0625 Divisor Error (Decimal) 2578 1719 1172 0.005 0.015 0.011 0.043 0.044 0.073 0.073 0.394 0.535 0.708 0.535 0.535 0.535 0.535 3.290 4.088 11.898 11.898 15.095 0.708 1.03125 Divisor Error (Decimal) 1289 0.005 0.044 0.011 0.043 0.073 0.073 0.394 0.535 0.535 0.708 0.535 0.535 3.290 0.535 4.088 11.898 11.898 16.077 15.095
4.2.4.6 Timers
Power contains three identical General Purpose Timers, which each independently programmable support following functions: Selectable Up/Down count direction Selectable External clocking (using PID) Internal clocking divide RTC) Programmable Reload Value Reload hold terminal count Interrupt, Discrete output (using PID) behavior terminal Count Capture timer value Snapshot register (PID used) Functional Clear signal (using PID)
Figure shows basic block diagram General Purpose Timers included Power PCI. Each three timers shall programmable independent other timers.
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Implemantation Note: Reload Snapshot same physical register
`0's
Reload Select
Clear Up/Down
Select Timer
Snapshot
Terminal Detect
Interrupt
Snapshot Load
Discrete (Pulse Leve)
Figure Timer Functional Block Diagram
4.2.4.7 Clock Control
Power chip contains clock generation logic CPU/SDRAM, RTC, JTAG clocks. input source clock generation function either on-card oscillator input signal when OSC_SEL EXT_OSC input signal when OSC_SEL 0b`0'. Software configure frequency each clock using clock generation divide registers. Changes divide frequency clock register cause specified clock adjust glitch-free-manner rate. block diagram clock generation function shown Figure
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DELAY POWER LOGIC DELAY 2/4/8/./256
SDRAM MEMORY
JTAG
JTMS_TCLK
EXT_OSC_SEL EXT_OSC
2/4/8/./256 1/2/4/8 DELAY
RAD750
SYS_CLK
1/2/4/8
PCI_CLK(1:6) PCI_CLK(7) PCI_CLK
PCI_SYSEN#
POWER LOGIC
4/8/16/32 POWER UART TIMERS
RTC_CLK
POWER BRIDGE
X2000
Figure Clock Generation Logic CPU/System clock generated Power consists three identical signals, each which represents input oscillator frequency divided either determined CPU/System Clock divide register. first these signals connected oscillator input RAD750 chip while second signal wrapped back system clock input Power PCI. third signal available provide monitor point debug use. These clocks active power saving modes. Power also capable generating required control signal sequence RAD750 safely control it's transitions between clock frequencies modes. This described more detail section Power Saving Modes operation. Clock generated Power consists identical signals, each which represents input oscillator frequency divided either determined Clock divide register. these pins wrapped back Power clock input control internal timers, UART, SDRAM refresh functions. second signal available provide monitor point debug use. These clocks active power saving modes. Clock generated Power consists eight identical signals, each which represents input oscillator frequency divided either determined Clock divide register. these pins wrapped back clock input Power PCI. These clocks active Full, Doze, modes operation. sleep mode, clocks disabled Sleep disable Clock divide register. JTAG clocks generated internal Power system clock divided between 256.
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4.2.4.8 Embedded Micro Controller (EMC)
Power ASIC contains simple Embedded Microcontroller (EMC) that provides flexibility handling reset initialization sequences error handling functions. RISC based microcontroller that provides simple logical, arithmetic, branch, vector interrupt capabilities. Features include: Program Counter General Purpose Registers (GPRs) Special Purpose Registers (SPRs) Vector Interrupts Full debug facilities Small Cache cache lines Bytes each) structure allowing short routines operate without need accessing microinstructions from memory Microinstruction program control centers around Program Counter. This allows fetch instructions from anywhere within available address space. general Program Counter increments each instruction executed unless branch specified. Program execution centers around 32-bit GPR's. Simple logical arithmetic operations performed GPR's along with ability load store them to/from address space OCB. Initial execution begins `FFF0 0020'X. This value parameterizable core. provides means vector program control order service critical events timely manner. Vector Control register contains Vector Pending bits, Vector Enable bits, Stop Vector bits. Vector Interrupt occurs when Vector Pending bits corresponding Vector Enable set. enters Stop state corresponding Stop Vector also set. When Vector Interrupt occurs saves current contents Program Counter into Vector Interrupt Address register then begin fetching instructions from indexed location from address stored Vector Table Anchor register. Vector Table Anchor register points consecutive branch instructions, each vector. index Vector Interrupt while index Vector Interrupt hex. Multiple Vector Interrupts handled priority basis with Vector Interrupt being highest Vector Interrupt being lowest. When processes Vector Interrupt automatically clears Vector Enables maskable Vector Interrupts, thus disabling Vector Interrupts. following lists microinstructions supported sequencer. valid assignments Source Destination fields instructions General Purpose Registers, Condition/Status Register, Vector Interrupt Address Register, Vector Control Register, Vector Anchor Register, Watch Timer, zero value. Dest= Src1 AND: Dest= Src1 XOR: Dest= Src1 ADD: Dest= Src1 Src2 Immediate: Dest= Src1 Immed (immediate data sign extended bits)
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SUB: Dest= Src1 Src2 SUBI (Sub Immediate): Dest= Src1 Immed (Immediate data sign extended bits) Load Dest LDB: load, byte determined lsb's effective address LDIU: Load Immediate Upper: Dest(31:16) Immed LDIL: Load Immediate Lower: Dest (15:0) Immed LDBS: load, data byte swapped LD8: Eight 32-bit loads from consecutive locations into GPR0-7 LD8BS: Eight 32-bit loads from consecutive locations into GPR0-7; Data byte swapped store STB: store, byte determined lsb's effective address STBS: store, data byte swapped ST8: Eight 32-bit stores consecutive locations from GPR0-7 ST8BS: Eight 32-bit stores consecutive locations GPR0-7, data byte swapped BCI: Branch immediate condition true BNCI: Branch immediate condition false BRI: Branch immediate unconditional BAL: Branch Link Monitor: Enter Monitor State Stop: Enter Stop State
4.2.4.9 Power Control Modes
Power supports reduced power operation clock control function, however care must taken dividing down clocks system where Power based processor used. RAD750 contains internal Phase Lock Loop (PLL) which allows internal logic multiplied value input clock. example, RAD750 CompactPCI computer board clock sent CPU, which then multiplies allow internal logic MHz. possible change input clock rate while running without potentially damaging PLL. However, possible with bypassed clock sent directly from outside. this bypass mode that clock divide power savings features used. Power capable supplying 4-bit wide configuration RAD750 enable disable select multiplier that will use. systems requiring less than MIPS, processor with configuration always disable PLL. Software then used divide input clock rate from half, fourth, eighth this rate. This done glitch free virtually same fashion chip. necessary switch between having enabled bypassed, that also accomplished Power PCI, during transitioning RAD750 will held reset Power PCI, meaning transition will glitch free. addition clock divide power savings modes supported Power PCI, also supports PowerPC Nap/Doze/Sleep capabilities. power management mode selected setting
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appropriate bits Power Management Control Register (configuration offset 70). bits from this register that defined Power are: Power Management Enable Doze Sleep
power management operational modes Power shown Table Power disables clocks those internal functions that required operational during selected power savings mode. Each operational units Power supplies internal clock function with status signals indicating when they busy performing operations capable entering reduced power mode. clock function uses these signals ensure that disabling clocks shut-off functions does occur until on-going operations have completed. difference between Doze slight, with only difference being that chip chip mode will return full power mode after request. Doze mode would return Doze rather than going back full power. When Power chip placed Doze mode, various elements have their clocks stopped internal chip. Included elements which stopped are: logic, except portion monitoring requests Memory Interface core logic, except SDRAM refresh scrubbing functions ONLY source clocks system disables clocks addition, lack transactions occurring from (and likely bus) will also cause decrease power simply reduction internal logic switching factor.
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Table Power Power Management Operational Modes Mode Full Power Doze Functioning Units Same Same Sleep target arbiter clocks DRAM Scrub DRAM refresh (active self refresh supported) DRAM refresh (Selfrefresh supported) request monitoring monitoring Interrupt/Discrete logic Machine Check monitoring JTAG slave Timers Vector Interrupt monitoring Checkstop Monitoring Clocks (Configurable off) Sleep assertion QREQ Reset request Interrupt Machine Check JTAG slave access Internal Vector Interrupt Checkstop from request returns full power others return Sleep Activation -Doze assertion QREQ Wake Same Same Sleep target transaction Return Mode Doze request returns full power others return Doze
Sleep
4.2.5 Endian Conventions
Power performs required endian conversions between interfaces. following sections describe various `interfaces' will required perform endian translations.
4.2.5.1 Interface
done MPC-106, configuration either Endian Little Endian. Memory accesses coming from must setup match this mode Power performs direct pass data internal Power PCI. remaining interfaces, conversion will made depending endian mode. mode Endian, then Power performs byte swapping accesses. Otherwise, Power will unmunge address. Endian systems, data byte swapped. Little Endian systems, address Munged.
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4.2.5.2 Memory Interface
uses memory addresses stores data unchanged from what passed also uses register addresses stores data unchanged (Little Endian) from what passed
4.2.5.3 Interface
interface specification Little Endian, registers, byte ordering changes performed.
4.2.5.4 UART
UART simple, byte-oriented interface endian conversion required. accesses bits time.
4.2.5.5 Power Flow
following diagrams show bytes transferred between functions each endian configuration. Figure below shows data transfers Endian Mode, Figure shows data transfers Little Endian Mode.
MSB(0)
Processor Registers
LSB(3)
MSB(0)
Processor Registers
LSB(3)
Processor Processor Memory
Processor Processor Memory
MSB(0)
LSB(7)
MSB(0)
LSB(7)
Config. Registers, PPCI Regs, Targets
MSB(3)
LSB(0)
LSB(7)
Config. Registers, PPCI Regs, Targets
MSB(3)
LSB(0) LSB(7)
PLASMA MSB(0) AMBI, PMBI, PHASOR, PMP, QHSS, Targets
PLASMA MSB(0) AMBI, PMBI, PHASOR, PMP, QHSS, Targets
Figure Data Transfers Endian Mode.
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MSB(0)
Processor Registers
LSB(3)
MSB(0)
Processor Registers
LSB(3)
Processor Processor Memory
Processor Processor Memory
MSB(0)
LSB(7)
MSB(0)
LSB(7)
Config. Registers, PPCI Regs, Targets
MSB(3)
LSB(0)
LSB(7)
Config. Registers, PPCI Regs, Targets
MSB(3)
LSB(0) LSB(7)
PLASMA MSB(0) AMBI, PMBI, PHASOR, PMP, QHSS, Targets
PLASMA MSB(0) AMBI, PMBI, PHASOR, PMP, QHSS, Targets
Figure Data Transfers Little Endian Mode
4.2.6 RAD750 Interrupts Vector Interrupts
PowerPC architecture supports number interrupt mechanisms from CPU. following sections cover each mechanisms describes interrupt RAD750 processor card. last subsection also describes Vector Interrupts Power design. Vector interrupts used signal interrupts Embedded Microcontroller (EMC) Power chip handling.
4.2.6.1 MISC_INT_L (INT)
Source: Power Destination: RAD750 Description: General Interrupt from Bridge chip RAD750 Embedded Programmable Interrupt Collection subfunction Power Bridge chip provides collection interrupts from internal external sources. collapses these interrupts into single interrupt RAD750, MISC_IO_INT_L.
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MISC INTERRUPT ENABLE REG(31:0) MISC INTERRUPT COLLECTION REG(31:0) MISC INTERRUPT STATUS REG(10) MISC_IO_INT_L (Interrupt CPU)
(31:21) Interrupt Interrupt Cntl High Priority Cntl Priority UART Interrupt Interrupt MISC Interrupt Interrupt Power Core Interrupts
(15) Interrupt
(14) Multiprocessor Signaling Interrupt
MISC VECTOR ENABLE REG(31:0) MISC INPUT REG(31:0)
Cntl Logic
MISC SIGNALING ENABLE REG(31:0) MULTIPROCESSOR SIGNALING REG(31:0)
Figure Power Interrupt Collection interrupt tree Interrupt Collection register Interrupt Enable register. Interrupt Collection register provides status source interrupt. Each Interrupt Collection register reduced through AND-OR function with each corresponding Interrupt Enable register generate single RAD750 interrupt. Each bits Interrupt Collection register represents free running status interrupting source. That when source interrupt removed corresponding Interrupt Collection register will clear.
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Figure Power INT_L Interrupt Tree Interrupt Collection register indicates that interrupt present Power inputs, MISC_INTERNAL_INT (15:0). MISC_INTERNAL_INT(15:0) connected internal chip interrupt sources shown following table:
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Table Interrupt Register Definition 13:11 04:00 Source Reserved Memory Memory UART MISC Reserved Description Function Interrupt Function Interrupt 0b`0' Memory High Priority Interrupt Memory Priority Interrupt UART Interrupt Interrupt Miscellaneous Interrupt Clock Test Interrupt
Interrupt Collection register also provides indicate that least Programmable Discretes (PID), configured input interrupt, active enabled. source this interrupt found Input register. Each input interrupts enabled Interrupt Enable register. Interrupt Collection register also provides indicate that least Multiprocessing Signaling interrupts active enabled. source this interrupt found Multiprocessor Signaling register. Each Multiprocessor Signaling interrupts enabled Signaling Enable register.
4.2.6.2 NMI_L
Source: (external source) Destination: Power (then RAD750 error enabled) Description: Non-maskable interrupt CompactPCI Card Power chip receive non-maskable interrupt (NMI) CompactPCI backpanel connector. This interrupt active will generate Machine Check RAD750, Machine Check interrupt enabled Power bridge chip. following section more details.
4.2.6.3 MCP_L
Source: Power Destination: RAD750 Description: Machine Check Interrupt RAD750 Power Bridge chip provides Collection register that indicates status source Machine Check interrupt. Each Collection register reduced through and-or function with each corresponding Enable register generate single RAD750 Machine Check interrupt. Each bits Collection register represents free running status
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interrupting source. That when source interrupt removed corresponding Collection register will clear. Machine Check interrupt sources signals MISC_INTERNAL_MCP(1:0) IO_MISC_NMI. Machine Check Interrupt further enabled MISC_MCP_ENABLE input. This intended connected MPC-106 compliant bridge chip) MPC-106 defined register PICR1[MCP_EN]. This signal only affects assertion Machine Check Interrupt, setting bits within Collection register
User Define (11) (Machine Check
Data Data
60X_Error_Status(3) 60X_Error_Mask(3) (OCB_MCP)
MCP_Collection(2) MCP_EN(2)
Data Addr Misaligned transfer received from MemCtl Data Invalid from MemCtl Retry Error Invalid Transfer Type NMI_L
60X_Error_Status(4) 60X_Error_Mask(4) (60X_MCP) MCP_Collection(1) MCP_EN(1) nand MCP_L
MCP_Collection(0) MCP_EN(0)
Figure Power Generation Tree interface function send MISC_INTERNAL_MCP signal collection register. table below shows main conditions that will generate signal. Please note that internal Power PCI, there error bits. error detected side transfer another error detected Power internal side transfer. Table Error Mechanisms
Error
Data Error signal received Power internal Master Subcore Data Parity data read Subcore Power Subcore Error from internal Master
Detection
Signal active
Isolation
Pass Read with Parity Data
Reporting
"Power internal MCP" Error Status Register "Power internal MCP" Error Status Register
Removal
Write "Power internal MCP" Error Status Register. Write "Power internal MCP" Error Status Register. Write "60x MCP" Error Status Register.
Recovery
External
Check parity across data data error from Power internal Check Parity data from Interface
Regenerate Data
Parity
External
Received Parity Error Data from Interface
Memory: Pass Data with incorrect parity; Power internal bus: activate WR_D_ERR signal; internal 60x: discard data Terminate address transfer asserting P60X_IO_ARTRY_L
"60x MCP" Error Status Register
External
Received Parity Error Address from Interface
Check Parity address from Interface
"60x MCP" Error Status Register store address information
Write "60x MCP" Error Status Register.
External
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Received Illegal Misaligned transfer that crosses 32-bit boundary from Interface
Detection
Check illegal misaligned transfers from Interface Monitor signals
Isolation
Terminate address transfer asserting P60X_IO_ARTRY_L
Reporting
"60x MCP" Error Status Register store address information "60x MCP" Error Status Register
Removal
Write "60x MCP" Error Status Register. Write "60x MCP" Error Status Register.
Recovery
External
Received IO_P60X_APE IO_P60X_DPE active
Parity Error Data from Memory Controller Interface
Operation continues
External
Check Parity data from Memory Controller Interface
Power internal bus: activate RD_D_ERR signal; 60x: send correct parity
"Memory Controller Interface Error" Error Status Register; 60x: Also "60x MCP" Error Status Register "Memory Controller Interface Error" Error Status Register; 60x: Also "60x MCP" Error Status Register "60x MCP" Error Status Register
Write "Memory Controller Interface Error" Error Status Register. Write "60x MCP" Error Status Register. Write "Memory Controller Interface Error" Error Status Register. Write "60x MCP" Error Status Register. Write "60x MCP" Error Status Register.
External
Data Invalid active read data from Memory Controller Interface
Monitor Data Invalid line from Memory Controller Interface
Power internal bus: activate RD_D_ERR signal; 60x: send correct parity
External
Retry Error
Address retried read Power internal does match original address Check invalid Transfer Type
Operation Continues
External
Invalid Transfer Type from interface
Terminate Address transfer asserting P60X_IO_ARTRY_L
"60x MCP" Error Status Register
Write "60x MCP" Error Status Register.
External
4.2.6.4 SMI_L
Source: Card Pull-up Destination: RAD750 Description: System Management Interrupt This signal, which part standard PowerPC Architecture, used RAD750 CompactPCI board design tied inactive card.
4.2.6.5 TEA_L
Source: Card Pull-up Destination: RAD750
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Description: Transfer Error Acknowledge commercial PowerPC system, generally used memory controller signal memory parity uncorrectable error occurred. receipt RAD750 generally causes Machine Check cause fatal Checkstop error). RAD750 CompactPCI board system signal used. Rather internal interrupt gathering mechanisms Power used handle memory errors signal RAD750, desired signals. Therefore, signal tied inactive RAD750 CompactPCI card.
4.2.6.6 RAD750_CKSTP_OUT_L
Source: RAD750 Destination: Power Bridge Description: RAD750 Checkstop (fatal error signal) Checkstop signal from processor signals that RAD750 fatal error longer operating. This signal received Power ASIC mapped Vector Interrupt would generally expected that Power routine coded handle this interrupt level would reset RAD750 perform some form BIST determine solid failure exists, not, could reinitialize RAD750 continued operation. Checkstop signal received Power bridge masked follows. Power statuses state primary input IO_MISC_CKSTP_L Checkstop Vector Interrupt Status register. While Checkstop active corresponding enable Vector Interrupt Enable register active then Power activates MISC_EMC_VECTOR_INT(5). Power latches IO_MISC_CKSTP_L signal."
4.2.6.7 RAD750_CKSTP_IN_L
Source: Power Bridge Destination: RAD750 Description: RAD750 Checkstop (fatal error signal) Power activates primary output MISC_IO_CKSTP_L when Critical Error active Vector Interrupt Status register, corresponding Vector Interrupt Enable register active, checkstop Enable RAD750 Discretes register set. Figure shows actual logic tree used Power this function. Power latches MISC_IO_CKSTP_L signal. Sources critical errors include internal chip errors such errors causing hot-bit state machines states once, internal parity errors, etc. These errors classified critical because they will generally require reset from recover from. Power chip sends Checkstop signal RAD750 which will then stop operation take place high impedance state (safe mode).
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Figure Power Checkstop Generation Tree Vector Interrupt Tree
4.2.6.8 Vector Interrupts
interrupts processor card need handled RAD750. Power supports Vector Interrupts, which handled Power PCI's internal EMC. Figure shows interrupt generation tree these vector interrupts. More details Vector Interrupt function found Section 4.2.4.8.
4.2.6.9 Interrupt Latencies
RAD750 board maximum external interrupt latencies while running from local memory shown Table depending mode speed. Latencies measured from interrupt signal transition first instruction execution interrupt handler. Table RAD750 board Interrupt Latencies Full-on Mode (µsec) Doze Mode (µsec) Mode (µsec) Sleep Mode (µsec) µsec 16.5 8.25 4.125
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External Electrical Interface
following sections provide consolidated list Input Output signals RAD750 board.
CompactPCI Defined Signals
Table shows signals used RAD750 CompactPCI board. Table Heading Notes: Signal Type column: BDTS indicates bi-directional, tri-state input/output (only direction time). BDODIL indicates bi-directional, open drain, inverted logic input/output pin, with external pull-up resistor, allowing multiple devices concurrently drive signal "wired-OR" configuration. Drivers assert (i.e. sink current) indicate logic state release (i.e. tri-state) indicate logic state. indicates tri-state output. indicates open drain output with external pull-up resistor allowing multiple devices share wireOR. BDOD indicates bi-directional, open drain input/output pin. BDSTS indicates bi-directional, sustained tri-state. This active tri-state signal owned driven one, only one, agent time. agent that drives must drive high least clock cycle before letting float. agent cannot start driving sooner than clock cycle after previous owner tri-states external pull-up resistor required sustain inactive state until another agent drives indicates cold-spareable. indicates internal soft pull-up input. identifies which connector (first characters) which (last three characters) signal wired section 3.11 more details connectors. Voltage/Technology column indicates type assumed signals card boundary. Included here external non-VLSI elements terminations. Value column, value shown state signal after issued. second value shown, this when card being used Resource Controller. Reset column, value shown state signal after Reset issued. second value shown, this when card being used Resource Controller. Table X2000 System Flight Computer Interface Signals SIGNAL NAME
PCI_AD_0 BDTS J1D24 3.3V Toler. Stub 3-State 3-State Address/Data
Signal Type
Voltage/ Technology
Value
Reset Value
Comment
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SIGNAL NAME
PCI_AD_1
Signal Type
BDTS
J1A24
Voltage/ Technology
3.3V Toler. Stub
Value
3-State
Reset Value
3-State
Comment
Address/Data
PCI_AD_2
BDTS
J1E23
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_3
BDTS
J1C23
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_4
BDTS
J1B23
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_5
BDTS
J1E22
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_6
BDTS
J1D22
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_7
BDTS
J1A22
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_8
BDTS
J1C21
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_9
BDTS
J1B21
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_10
BDTS
J1E20
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_11
BDTS
J1D20
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_12
BDTS
J1A20
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_13
BDTS
J1E19
3.3V Toler. Stub
3-State
3-State
Address/Data
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SIGNAL NAME
PCI_AD_14
Signal Type
BDTS
J1C19
Voltage/ Technology
3.3V Toler. Stub
Value
3-State
Reset Value
3-State
Comment
Address/Data
PCI_AD_15
BDTS
J1B19
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_16
BDTS
J1C11
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_17
BDTS
J1B11
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_18
BDTS
J1A11
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_19
BDTS
J1E10
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_20
BDTS
J1D10
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_21
BDTS
J1A10
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_22
BDTS
J1E09
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_23
BDTS
J1C09
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_24
BDTS
J1E08
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_25
BDTS
J1D08
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_26
BDTS
J1A08
3.3V Toler. Stub
3-State
3-State
Address/Data
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SIGNAL NAME
PCI_AD_27
Signal Type
BDTS
J1E07
Voltage/ Technology
3.3V Toler. Stub
Value
3-State
Reset Value
3-State
Comment
Address/Data
PCI_AD_28
BDTS
J1C07
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_29
BDTS
J1B07
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_30
BDTS
J1A07
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_AD_31
BDTS
J1E06
3.3V Toler. Stub
3-State
3-State
Address/Data
PCI_C/BE0#
BDTS
J1E21
3.3V Toler. Stub
3-State
3-State
Cmd/Byte Enable
PCI_C/BE1#
BDTS
J1E18
3.3V Toler. Stub
3-State
3-State
Cmd/Byte Enable
PCI_C/BE2#
BDTS
J1E11
3.3V Toler. Stub
3-State
3-State
Cmd/Byte Enable
PCI_C/BE3#
BDTS
J1A09
3.3V Toler. Stub
3-State
3-State
Cmd/Byte Enable
PCI_PAR
BDTS
J1D18
3.3V Toler. Stub
3-State
3-State
Even Parity over C/BE(0:3)#
PCI_FRAME#
BDSTS
J1B15
3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Master Start Stop
PCI_IRDY#
BDSTS
J1C15
3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Initiator Ready
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SIGNAL NAME
PCI_TRDY#
Signal Type
BDSTS
J1E15
Voltage/ Technology
3.3V Toler. Stub 8.2K Pull-up
Value
3-State
Reset Value
3-State
Comment
Target Ready
PCI_STOP#
BDSTS
J1D16
3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Target Stop
PCI_DEVSEL#
BDSTS
J1A16
3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Device select
PCI_IDSEL
Input
J1B09
3.3V Toler. Stub
Chip select device configuration space
PCI_PERR#
BDSTS
J1E17
3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Parity Error
PCI_SERR#
BDOD
J1A18
3.3V Toler. Stub 8.2K Pull-up
Floated
Floated
System Error
PCI_REQ#
BDTS
J1A06
3.3V Toler. Series Term.
3-State
3-State
Request
PCI_GNT#
BDTS
J1E05
3.3V Toler. Series Term. 100K Pull-up
3-State
3-State
Grant
PCI_RST# PCI_RDY_PAR
BDTS BDTS
J1C05 J1B05
3.3V Toler. 3.3V Toler. Stub 8.2K Pull-up
3-State
3-State
Reset Ready Parity
PCI_CLK
BDTS
J1D06
3.3V Toler. Series Term.
Active
Active
Clock
PCI_SDONE PCI_SBO#
J1B17 J1C17
None None
Unused Unused
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SIGNAL NAME
PCI_LOCK#
Signal Type
J1E16
Voltage/ Technology
Stub
Value
Reset Value
Comment
Unused
Central Resource
PCI_SYSEN# Input J2C02 3.3V Toler. 8.2K Pull-up PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# PCI_REQ5# PCI_REQ6# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_GNT4# PCI_GNT5# PCI_GNT6# PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 Input Input Input Input Input Input J2C01 J2E01 J2E02 J2D03 J2D15 J2D17 J2D01 J2D02 J2C03 J2E03 J2E15 J2E17 J2A01 J2A02 J2B02 J2A03 J2A20 3.3V Toler. 3.3V Toler. 3.3V Toler. 3.3V Toler. 3.3V Toler. 3.3V Toler. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3.3V Series Term. 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active 3-State Active Clock Distribution Clock Distribution Clock Distribution Clock Distribution Clock Distribution 3-State 3-State Arbitration Grant 3-State 3-State Arbitration Grant 3-State 3-State Arbitration Grant 3-State 3-State Arbitration Grant 3-State 3-State Arbitration Grant 3-State 3-State Arbitration Grant Arbitration Request Arbitration Request Arbitration Request Arbitration Request Arbitration Request Arbitration Request System Slot Enable
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SIGNAL NAME
PCI_CLK6 PCI_CLK7
Signal Type
J2A21 J2C21
Voltage/ Technology
3.3V Series Term. 3.3V Series Term.
Value
3-State Active 3-State Active
Reset Value
3-State Active 3-State Active
Comment
Clock Distribution Clock Distribution
Miscellaneous Signals
PCI_REQ64# PCI_ACK64# PCI_PRST# PCI_DEG# Pull-up Pull-up Pull-up Input, Input, Input, J1B25 J1E24 J2C17 J2C16 8.2K Pull-up 8.2K Pull-up 8.2K Pull-up 3.3V CMOS Tol. 8.2K Pull-up 3.3V CMOS Tol. 8.2K Pull-up 3.3V CMOS Tol. 8.2K Pull-up High High High High Request, Unused Acknowledge, Unused Push Button Reset Unused Power Degrading
PCI_FAL#
J2C15
Power Failed
PCI_ENUM#
J1C25
Module Added about Dropped
Table Content Notes: Signal will input only when card operating central resource. This indicated input signal PCI_SYSEN# being active. Signal will when card operating central resource. This indicated input signal PCI_SYSEN# being active. RAD750 CompactPCI board contains fully compliant target initiator interface local bus. Additionally, when PCI_SYSEN# active, RAD750 CompactPCI board provides clock, request grant signals required central resource. signals discussed thoroughly chapter Specification, this section mostly serves specify optional features RAD750 CompactPCI board must support, well provide summary ease reference. Note special requirements PCI_RST#, PCI_SERR#, added sideband signal PCI_RDY_PAR. PCI_RDY_PAR added provide additional fault tolerance.
5.1.1 Interface
RAD750 CompactPCI board shall designed allow multiple RAD750 CompactPCI boards same Bus. RAD750 CompactPCI board supports following interface main backpanel connectors J2). RAD750 CompactPCI board designed permit operation from CompactPCI slot without requiring physical reconfiguration RAD750 CompactPCI board. Multiple RAD750 CompactPCI board's placed same backpanel, with PCI_SYSEN# signal from backpanel being used RAD750 CompactPCI board determine Central Resource.
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5.1.1.1 PCI_AD(31:0)
RAD750 CompactPCI board supports 32-bit described Specification. address data multiplexed onto PCI_AD(31:0) signals. transaction consists address phase (the RAD750 CompactPCI board does support Dual-Address Cycles) followed more data phases. RAD750 CompactPCI board supports burst accesses both target initiator bus. When acting central resource (PCI_SYSEN# active), PCI_AD(31:0) signals driven 0x'0000 0000' during reset prevent from floating, provided board test mode, which will override control tri-state driver. PCI_AD(31:0) held tri-state during reset when RAD750 CompactPCI board selected central resource. There stub termination each signal.
5.1.1.2 PCI_C/BE(3:0)#
PCI_C/BE(3:0)# provide multiplexed command byte enables bus. During address phase transaction, command valid. During each data phase transaction, byte enables valid. byte enables free change between data phases, valid clock that starts each data phase stay valid entire data phase (regardless state PCI_IRDY#). PCI_C/BE(3:0)# always driven transaction master. Similar PCI_AD(31:0), when acting central resource, RAD750 CompactPCI board drives PCI_C/BE(3:0)# 0b'0000' during reset provided board test mode, which will override chip driver (OCD) control tri-state driver. PCI_C/BE(3:0)# tri-state during reset when central resource. There stub termination each signal.
5.1.1.3 PCI_PAR
PCI_PAR signal provides even parity over PCI_AD(31:0) PCI_C/BE(3:0)#. (The number `1's PCI_AD(31:0), PCI_C/BE(3:0)#, PCI_PAR equals even number.) Parity calculated same transactions regardless type. PCI_PAR valid address phases clock after address phase completes. data phases, parity valid clock after PCI_IRDY# asserted write, clock after PCI_TRDY# asserted read remains valid until once clock after data phase completes. transaction master drives PCI_PAR writes; target drives PCI_PAR reads. Similar PCI_AD(31:0) PCI_C/BE(3:0)#, RAD750 CompactPCI board, when acting central resource, drives PCI_PAR 0b`0' during reset, provided board test mode, which will override control tri-state driver. When acting central resource, RAD750 CompactPCI board tri-states PCI_PAR during reset. There stub termination this signal.
5.1.1.4 PCI_FRAME#
PCI_FRAME# asserted entity granted mastership claim begin transaction. While PCI_FRAME# asserted, data transfers continue. When PCI_FRAME# deasserted, transaction final data phase completed. There stub termination this signal 8.2K pull-up 3.3V.
5.1.1.5 PCI_IRDY#
Initiator Ready driven initiator (bus master) asserted indicate that master able complete current data phase transaction. During write, PCI_IRDY# indicates that valid data present PCI_AD(31:0). During read, PCI_IRDY# indicates master ready accept data. Data transferred (and data phase completed) whenever PCI_IRDY# PCI_TRDY# both asserted. Wait cycles inserted into data phases until both PCI_IRDY# PCI_TRDY# asserted. There stub termination this signal 8.2K pull-up 3.3V.
Document 234A533
RAD750 CompactPCI Hardware Users Manual
5.1.1.6 PCI_TRDY#
Target Ready driven target asserted indicate that target able complete current data phase transaction with data being transferred. During read, PCI_TRDY# indicates that valid data present PCI_AD(31:0). During write, PCI_TRDY# indicates target ready accept data. Data transferred (and data phase completed) whenever PCI_TRDY# PCI_IRDY# both asserted. Wait cycles inserted into data phases until both PCI_TRDY# PCI_IRDY# asserted. There stub termination this signal 8.2K pull-up 3.3V.
5.1.1.7 PCI_STOP#
PCI_STOP# driven target asserted indicate that target requesting terminate current transaction. RAD750 CompactPCI board supports types target termination. There stub termination this signal 8.2K pull-up 3.3V.
5.1.1.8 PCI_DEVSEL#
target will drive PCI_DEVSEL# active when determines been selected target current transaction. transaction master uses PCI_DEVSEL# input signify that target claimed transaction master started. Once asserted, PCI_DEVSEL# remains active throughout transaction, unless signify target abort. RAD750 CompactPCI board only supports Medium speed PCI_DEVSEL# target, supports valid PCI_DEVSEL# timings master. There stub termination this signal 8.2K pull-up 3.3V.
5.1.1.9 PCI_IDSEL
Initialization Device Select used chip select during configuration read write cycles. target, RAD750 CompactPCI board only responds "multi-function" Type configuration cycles. device that supports multi-function Type configuration cycles will assert PCI_DEVSEL# response configuration read write command only PCI_IDSEL active, PCI_AD(1:0) 0b'00', PCI_AD(10:8) match function that implemented device. RAD750 CompactPCI board only function defined. single-function Type configuration cycle decode does include decode AD(10:8).) There stub termination this signal.
5.1.1.10
PCI_PERR#
Parity Error used reporting data parity errors during transactions except Special Cycle. (Data parity errors during Special Cycle commands address parity errors reported using PCI_SERR# enabled.) Refer Specification details operation PCI_PERR#. There stub termination this signal 8.2K pull-up 3.3V.
5.1.1.11
PCI_SERR#
System Error defined Specification open drain output only signal. However, RAD750 CompactPCI board, when operating central resource will additionally receive PCI_SERR# input, therefore RAD750 CompactPCI board redefines this signal bidirectional open drain (BDOD). Specification (chapter 3.10 Special Design Considerations) states "devices cannot drive receive signals same time". order meet this requirement, RAD750 CompactPCI board wraps PCI_SERR# output internally (i.e., prior cell Power chip). RAD750 CompactPCI board ignores PCI_SERR# receiver input when central resource. There stub termination this signal 8.2K pull-up 3.3V.
Document 234A533
RAD750 CompactPCI Hardware Users Manual
5.1.1.12
PCI_REQ#
RAD750 CompactPCI board asserts PCI_REQ# only when central resource, requires mastership capable sending receiving data soon PCI_FRAME# asserted. PCI_REQ# output only signal that tri-stated during reset. series termination resistor placed RAD750
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