µPD98404 ADVANCED ASONET FRAMER DESCRIPTION µPD98404 NE

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µPD98404 ADVANCED ASONET FRAMER DESCRIPTION µPD98404 NE

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INTEGRATED CIRCUIT
µPD98404
ADVANCED ASONET FRAMER
DESCRIPTION
µPD98404 NEASCOT-P30is Aapplications, which used Aadapter boards connecting workstations Anetwork also used Ahubs Aswitches. This provides sub-layer functions SONET/SDH-base physical layer within Aprotocol defined AForum's UNI3.1 recommendations. This product's main functions include transmission functions such mapping Acells sent from Alayer payload field Mbps SONET STS-3c/SDH STM-1 frame transmission (Physical Media Dependent) sub-layer physical layer. reception functions include separation overhead from Acells data streams received from sub-layer transmission Acells Alayer. addition, this includes clock recovery function that extracts reception sync clock from streams received data clock synthesis function that generates clock transmissions. Detailed function descriptions provided following user's manuals. sure read them before designing. µPD98404 User's Manual: S11821E
FEATURES
On-chip clock recovery/clock synthesis functions Provides sub-layer function Aprotocol's physical layer Supported frame formats include Mbps SONET STS-3c/SDH STM-1 Conforms AForum UTOPIA interface Level V1.0 (af-phy-0039.000 June 1995) Supports three UTOPIA interfaces: Single octet-level handshaking Single cell-level handshaking Multi mode Selectable drop/bypass unassigned cells On-chip internal loopback functions layer loopback Alayer loopback Supports interfaces: serial parallel 155.52 Mbps serial interface 19.44 parallel interface Provides registers writing/reading overhead information (section overhead) byte, (first second) bytes, byte (line overhead) byte, byte (path overhead) byte, byte, byte Provides pseudo error frame transmit function various errors Supports JTAG boundary scan test function (IEEE 1149.1) CMOS technology +3.3 single power supply
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Document S11822EJ4V0DS00 (4th edition) Date Published 2000 CP(K) Printed Japan
mark
shows major revised points.
1997, 1999
µPD98404
Provides abundant (Operation Maintenance) functions Receive side Transmit side Transmission various alarm data Source-triggered automatic loopback transmission Line RDI, Path Line REI, Path Command-specified transmission Line AIS, Path Pseudo error generation frame transmit functions generated frame OOF, generated frame generated frame OCD, generated frame error generated frame error generated frame error generated frame Detection alarm fault signals (Loss Signal) (Out Frame) (Loss Frame) (Loss Pointer) (Out Cell Delineation) (Loss Cell delineation) Line RDI, Path Line AIS, Path Detection display quality loss sources error, error, error, Line REI, Path-REI On-chip error counters byte error counter (16-bit) byte error counter (20-bit) byte error counter (16-bit) Line error counter (20-bit) Path error counter (16-bit) Frequency justification processing counter (12-bit) error drop cell counter (20-bit) FIFO overflow drop cell counter (20-bit) Idle cell counter (20-bit)
ORDERING INFORMATION
Part number µPD98404GJ-KEU Package 144-pin plastic (fine pitch)
Data Sheet S11822EJ4V0DS00
µPD98404
SYSTEM CONFIGURATION EXAMPLE
following example system configuration using µPD98404.
Aadapter card application
Control memory
chip PD98401A NEASCOT-S15
chip PD98404 NEASCOT-P30
Optical fiber transceiver /receiver
19.44 Oscillator bridge
(terminal side) application
Microprocessor
Oscillator
PD98404 NEASCOT-P30
Optical fiber transceiver /receiver
UTOPIA Level2
Switch device PD98412 NEASCOT-X15
µPD98404 NEASCOT-P30
Optical fiber transceiver /receiver
Data Sheet S11822EJ4V0DS00
Serial parallel Frame synchronization (A1, Pointer processor
Cell synchronization verification correction
BLOCK DIAGRAM
UTOPIA interface signal
Cell descrambler
FIFO, cells
interface signal
Alayer interface
Clock recovery clock synthesizer layer interface
Descrambler
Parallel serial
Scrambler
Cell scrambler
generator
FIFO, cells
Data Sheet S11822EJ4V0DS00
generator (transmit side)
Transmission overhead processor (A1,
Reception overhead processor (K2,
Transmission overhead registers (J0, K2,etc.)
Management interface signal
Controller interface
generator (receive side)
Transmission timing generator
controller (performance register, etc.)
Reception overhead registers (J0, etc.)
Interrupt source register Mode register
µPD98404
µPD98404
CONFIGURATION
Test interface interface
TEST0 TEST2
RDIT, RDIC RCIT, RCIC TDOT, TDOC TCOT, TCOC TFKT, TFKC Serial
RDO0 RDO7 RCLK RSOC RENBL_B EMPTY_B/RCLAV RADD0-RADD4 TDI0 TDI7 TCLK TSOC
AIN1 REFCLK PSEL0, PSEL1 RPD0 RPD7 TPD0 TPD7 Parallel
Alayer interface
TENBL_B FULL_B/TCLAV TADD0 TADD4 UMPSEL
PMDALM PHYALM0 PHYALM2 RxFP TxFP TFSS
MSEL MADD0 MADD6 CS_B DS_B/RD_B R/W_B/WR_B ACK_B/RDY_B PHINT_B Management interface
JTAG boundary scan interface
Remark
Active pins indicated with suffix "_B" this document.
Power supply,
GND, GND-TPE, GND-RPE GND-SP, GND-CS, GND-CR
JRST_B
VDD, VDD-TPE, VDD-RPE VDD-SP, VDD-CS, VDD-CR
RESET_B
Data Sheet S11822EJ4V0DS00
µPD98404
CONFIGURATION (TOP VIEW)
144-pin plastic (fine pitch)
JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TxFP TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP
RADD4 RADD3 RADD2 RADD1 RADD0 RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 RCLK RENBL_B RSOC EMPTY_B/RCLAV FULL_B/TCLAV TSOC TENBL_B TCLK TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0
TADD4 TADD3 TADD2 TADD1 TADD0 RESET_B PHINT_B ACK/RDY_B R/W_B/WR_B DS_B/RD_B CS_B UMPSEL MADD6 MADD5 MADD4 MADD3 MADD2 MADD1 MADD0 MSEL PMDALM RxFP
GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-RPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1
Data Sheet S11822EJ4V0DS00
µPD98404
ALLOCATION
Number name JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TxFP TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP Number name GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-RPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1 Number name RxFP PMDALM MSEL MADD0 MADD1 MADD2 MADD3 MADD4 MADD5 MADD6 UMPSEL CS_B DS_B/RD_B R/W_B/WR_B ACK_B/RDY_B PHINT_B RESET_B TADD0 TADD1 TADD2 TADD3 TADD4 Number name TDI0 TDI1 TDI2 TDI3 TDI4 TDI5 TDI6 TDI7 TCLK TENBL_B TSOC FULL_B/TCLAV EMPTY_B/RCLAV RSOC RENBL_B RCLK RDO0 RDO1 RDO2 RDO3 RDO4 RDO5 RDO6 RDO7 RADD0 RADD1 RADD2 RADD3 RADD4
Data Sheet S11822EJ4V0DS00
µPD98404
NAMES
ACK_B AIN1 DS_B EMPTY_B FULL_B GND-RPE GND-CR GND-CS GND-SP GND-TPE JRST_B
Read/write Cycle Receive Acknowledge External Filter Connection Chip Select Data Strobe Output Buffer Empty Buffer Full Ground Ground Receive PECL Buffer Ground Clock Recovery Circuit Ground Clock Synthesis Ground Serial/Parallel Circuit Ground Transmit PECL Buffer JTAG Clock JTAG Data Input JTAG Data Output JTAG Mode Select JTAG Reset
REFCLK RENBL_B RESET_B RPD0-RPD7 RSOC RxFP R/W_B
System Clock Receive Data Enable System Reset Receive Parallel Data Clock Receive Parallel Data Receive Start Address ACell Receive Frame Pulse Read/write Control
TADD0-TADD4 Transmit Device Address TCLAV TCLK TCOC TCOT TDI0-TDI7 TDOC TDOT TENBL_B TEST0-TEST2 TFKC TFKT TFSS Internal Transmit System Clock Transmit Cell Available Transmit Data Transferring Clock Transmit Clock Output Complement Transmit Clock Output True Transmit Data Input from ALayer Transmit Data Output Complement Transmit Data Output True Transmit Data Enable Test Mode Transmit Reference Clock Transmit Reference Clock Complement Transmit Reference Clock True Transmit Frame Signal Transmit Parallel Data Clock Transmit Parallel Data Transmit Start Address ACell Transmit Frame Pulse Utopia Multi-PHY Mode Select Supply Voltage Logic Circuit Voltage Supply Receive PECL Buffer Voltage Supply Clock Recovery Circuit Voltage Supply Clock Synthesis Voltage Supply Serial/Parallel Circuit Voltage Supply Transmit PECL Buffer Write Select
MADD0-MADD6 Management Interface Address MD0-MD7 MSEL PHINT_B PHYALM0PHYALM2 PMDALM Device Alarm Management Interface Data Management Interface Mode Select Physical Interrupt Alarm Detection
TPD0-TPD7 TSOC TxFP UMPSEL VDD-RPE VDD-CR VDD-CS VDD-SP VDD-TPE WR_B
PSEL0, PSEL1 Mode Select RADD0-RADD4 Receive Device Address RCIC RCIT RCLAV RCLK RD_B RDIC RDIT RDO0-RDO7 RDY_B Receive Clock Input Complement Receive Clock Input True Internal Receive System Clock Receive Cell Available Receive Data Transferring Clock Read Select Receive Data Input Complement Receive Data Input True Receive Data Output Ready Signal
Data Sheet S11822EJ4V0DS00
µPD98404
FUNCTIONS
Interface
name RDIT level P-ECL True(+) RDIC P-ECL Complement(-) RCIT P-ECL True(+) RCIC P-ECL Complement(-) TDOT P-ECL True(+) TDOC P-ECL Complement(-) TCOT P-ECL True(+) Serial transmit clock output (155.52 MHz). When PSEL [1:0] clock generated internal synthesizer output transmit clock. When PSEL [1:0] clock supplied TFKT/TFKC output. TCOC P-ECL Complement(-) Depending mode selected, transmit data latched receive clock output. Even such case, this outputs clock internal synthesizer clock input TFKT/TFKC accordance with setting PSEL[1:0] pins. does output receive recovery clock. TFKT P-ECL True(+) TFKC P-ECL Complement(-) RPD0RPD7 61-68 TTL* Parallel receive data input. When PSEL [1:0] these pins input receive data. data sampled sync with rising edge parallel receive clock RPC. TTL* Parallel receive clock input (19.44 MHz). When PSEL [1:0] select parallel mode, this inputs 19.44 receive clock. TPD0TPD7 17-24 TTL* Parallel transmit data output. When PSEL [1:0] select parallel mode, these pins output transmit data sync with rising edge TTL* Parallel transmit clock output. When PSEL [1:0] this outputs clock (19.44 MHz) supplied TFC. Serial transmit clock input (155.52 MHz). When PSEL [1:0] input used transmit clock. Serial transmit data output. data output sync with rising edge serial clock TCOT. Function Serial receive data input. When PSEL [1:0] data sampled clock recovered internal clock recovery PLL. When PSEL [1:0] data sampled clock input RCIT/RCIC. Serial receive clock input (155.52 MHz). When PSEL [1:0] input used receive clock.
(1/2)
Data Sheet S11822EJ4V0DS00
µPD98404
(2/3)
name level TTL* Function Parallel transmit clock input. When PSEL [1:0] select parallel mode, this inputs parallel transmit clock 19.44 MHz. TxCL bits [1:0] MDR1 register serial mode with PSEL[1:0] "00", input 19.44 source clock internal clock synthesizer PLL. REFCLK TTL* Reference clock input. This supplies system clock 19.44 internal clock recovery/synthesizer. Always input this clock. PSEL0, PSEL1 TTL* interface mode select input. These pins select interface mode layer used. PSEL [1:0] :Serial mode. clock generated internal clock recovery/synthesizer used transmission reception. PSEL [1:0] :Serial mode. clock input external RCIT/RCIC TFKT/TFKC used transmission reception. PSEL [1:0] 1x:Parallel mode. clock input used. AIN1 Analog This connects loop filter internal synthesizer PLL. Leave open. PMDALM TTL* layer alarm signal input. signal level this reflected state internal register. transition used interrupt source. device input. PHYALM0PHYALM2 10-12 TTL* layer alarm detection signal output. These pins output signal indicating that internally monitored error state (PMDALM, CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, Path RDI) been detected. pins output error either singly combination. type error indicated selected setting internal AMPR, AMR1, AMR2 registers. details use, refer Alarm Report Pins state signal from peripheral
(PHYALM[2:0], (S11821E).
RxFP TTL*
PMDALM)
µPD98404
User's
Manual
Frame pulse output receive side kHz). This outputs pulse signal one-clock intervals sync with clock frame synchronization state.
Data Sheet S11822EJ4V0DS00
µPD98404
(3/3)
name TxFP level TTL* Function Frame pulse signal output transmit side kHz). This outputs pulse signal one-clock intervals sync with clock. TFSS TTL* Transmit frame output disable signal input. When signal high, transmit frame output stops. When signal low, transmission starts from beginning frame. µPD98404 samples this signal rising edge clock. transmit frame output resumed ninth rising edge clock after rising edge which high level this signal last detected. TTL* Internal system clock output receive side (19.44 MHz). This outputs receive clock divided source receive clock depends selected mode, which either clock generated internal clock recovery clock supplied from RCIT/RCIC pins. Clock output from this stopped while device being reset. TTL* Internal system clock output transmit side (19.44 MHz). This outputs transmit clock divided source transmit clock depends selected mode, which either clock generated internal synthesizer clock supplied from TCIT/TCIC pins. Clock output from this stopped while device being reset.
Alayer interface
name RDO0RDO7 130-137 level TTL* state) Receive data output. Function
(1/2)
These pins form 8-bit data that outputs receive data Alayer device. data output sync with rising edge RCLK clock. These pins operate three states, depending UTOPIA interface mode.
RCLK
TTL*
Receive clock input. This supplies clock receive data transfer.
RSOC
TTL*
state)
Receive cell start position signal output. receive cell. This operates three states, depending UTOPIA interface mode.
This outputs signal indicating position first byte
RENBL_B
TTL*
Receive enable signal input. This inputs signal indicating that Alayer ready receive data.
Data Sheet S11822EJ4V0DS00
µPD98404
(2/2)
name EMPTY_B/ RCLAV level TTL* Function Receive FIFO data transfer disable signal output
receive FIFO cell data transfer enable signal output. state) This functions either EMPTY_B (2-state operation) RCLAV (3-state operation), depending selected mode UTOPIA interface. EMPTY_B indicates that receive FIFO receive data bytes transferred Alayer. RCLAV indicates that receive FIFO data least once cell transferred Alayer. This operates three states, depending UTOPIA interface mode.
RADD0RADD4 TDI0TDI7
138-142
TTL*
address input receive side. multi-PHY mode, these pins input address layer device selected.
111-118
TTL*
Transmit data input. These pins form 8-bit data that inputs transmit data. data input sync with rising edge TCLK clock.
TCLK
TTL*
Transmit clock input. This inputs clock transmit data transfer. Caution µPD98404 also uses this clock system clock management interface block. Therefore, always input clock higher.
TSOC
TTL*
Transmit cell start position input. This inputs signal indicating position first byte transmit cell input µPD98404.
TENBL_B
TTL*
Transmit enable input. This inputs signal indicating that Alayer device outputting valid transmit data TDI0 TDI7.
FULL_B/ TCLAV
TTL*
Transmit FIFO data transfer disable signal output transmit FIFO
cell data transfer enable signal output. state) This functions either FULL_B (2-state operation) TCLAV (3state operation), depending selected UTOPIA interface mode. FULL_B indicates that transmit FIFO free area receive transmit data. TCLAV indicates that transmit FIFO free area least cell storing transmit data. This operates three states, depending UTOPIA interface mode.
TADD0TADD4 UMPSEL
103-107
TTL*
address input transmit side. When used multi-PHY mode, these pins input address selecting layer device.
TTL*
Multi-PHY mode select signal input. When signal high, multi-PHY mode selected. When signal low, single mode selected.
Data Sheet S11822EJ4V0DS00
µPD98404
Management interface
name MSEL level TTL* Function Mode select signal input. level input this determines management interface mode. MSEL MSEL functions RD_B, WR_B, RDY_B selected. functions DS_B, R/W_B, ACK_B selected. MADD0MADD6 78-84 TTL* Address input. These pins form address input address internal register µPD98404. MD0-MD7 87-94 TTL* (3state) CS_B TTL* 8-bit data bus. These pins form data read write data internal register µPD98404. Chip select signal input. When signal low, access internal register enabled. DS_B/ RD_B TTL* Data strobe signal input read signal input. This functions either DS_B RD_B, depending mode selected MSEL pin. MSEL This functions DS_B input data strobe signal. MSEL This functions RD_B select read access. R/W_B/ WR_B TTL* Read/write signal input write signal input. This functions either R/W_B WR_B, depending mode selected MSEL pin. MSEL This functions R/W_B that inputs read/write control signal. High: Read cycle Low: Write cycle MSEL This functions WR_B that selects write access. ACK_B/ RDY_B TTL* (3state) Data acknowledge signal output ready signal output. selected MSEL pin. MSEL functions ACK_B that outputs data strobe signal. MSEL functions RDY_B that selects read access. PHINT_B TTL* Interrupt signal output. This notifies host that internal interrupt source been detected. active low. This
(1/2)
functions either ACK_B RDY_B, depending mode
Data Sheet S11822EJ4V0DS00
µPD98404
(2/2)
name RESET_B level TTL* Function System reset signal input. signal initializes µPD98404. input signal should kept more. Especially, case power above-mentioned pulse width must kept after supply voltage reaches equal more than least. When RESET_B signal input, following clock must input according interface mode. Serial mode TCLK/RCLK clock Parallel mode TCLK/RCLK TFC/RPC clocks
JTAG boundary scan
name level TTL* Boundary scan data input. When being used, this should grounded. TTL* (3state) TTL* Boundary scan clock input. When being used, this should grounded. TTL* Boundary scan mode select signal input. When being used, this should grounded. JRST_B TTL* Boundary scan reset signal input. When being used, this should grounded. Boundary scan data output. When being used, this should left open. Function
Remark
Processing JTAG boundary scan pins used (during normal operation) reason that JRST_B grounded when used (during normal operation) better prevent malfunctioning JTAG logic. JTAG also processed either following ways: Reset JTAG logic without using JRST_B Reset JTAG logic using pins keep reset status (the JRST_B pulled up). (pull input clock cycles more pin. Reset JTAG logic using JRST_B Input pulse same width RESET_B µPD98404 JRST_B pin. both JRST_B pins pulled kept high, JTAG logic released from reset status. Therefore, normal operation affected. input level pins pulling them down
Data Sheet S11822EJ4V0DS00
µPD98404
Internal test pins
name TEST0TEST2 level TTL* Function These pins used test µPD98404. normal operation, these pins should grounded. TEST [2:0] =000 Normal operation TEST [2:0] =Other than Test mode
Power ground
name 108, 119, 102, 109, 110, 124, 143, VDD-TPE Power supply (+3.3 ±5%) ground output PECL I/O. noise this power supply will affect jitter characteristics. GND-TPE means eliminating this noise, such filter, needed. Function Power supply (+3.3 ±5%) ground general logic block.
VDD-RPE
Power supply (+3.3 ±5%) ground input PECL I/O. noise this power supply will affect jitter characteristics. means eliminating this noise, such filter, needed.
GND-RPE
VDD-SP
Power supply (+3.3 ±5%) ground serial /parallel block. noise this power supply will affect jitter characteristics. means eliminating this noise, such filter, needed.
GND-SP
VDD-CS
Power supply (+3.3 ±5%) ground clock synthesizer block. noise this power supply will affect jitter characteristics. means eliminating this noise, such filter, needed.
GND-CS
VDD-CR
Power supply (+3.3 ±5%) ground clock recovery block. noise this power supply will affect jitter characteristics. means eliminating this noise, such filter, needed.
GND-CR
Data Sheet S11822EJ4V0DS00
µPD98404
Recommended connection unused pins
Each input level other than P-ECL Recommended Connection Unused Pins Connect ground (parallel input serial mode) RPD0 through RPD7, RPC, (Multi-PHY pins single mode) TADD0 TADD4, RADD0 through RADD4 (others) TFSS (essential) Each input P-ECL level Output Pull True(+) pins (TFKT, RCIT, RDIT) Connect Complement(-) pins (TFKC, RCIC, RDIC) ground. Leave open. (Parallel input pins serial mode) TPD0 TPD7 (others) TxFP, RxFP, TCL, Output P-ECL level Leave open. TDOT, TDOC, TCOT, TCOC AIN1 Leave Open. Because noise this affects characteristics internal PLL, wire clock line vicinity.
Data Sheet S11822EJ4V0DS00
µPD98404
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings mark indicates portion which have been revised from edition.
Item Power supply voltage Input/output voltage
Symbol VI1/VO1 VI2/VO2
Condition
Ratings -0.5 +4.6
Unit
other than P-ECL, analog level P-ECL, analog level
-0.5 +6.6 +3.0 -0.5 +4.6 +0.5 +150
Operating temperature Storage temperature
Tstg
Caution
even parameters exceeds absolute maximum rating even momentarily, quality product degraded. absolute maximum rating therefore specifies upper lower limit values which product used without physical damage. sure exceed fall below these values when using product.
Capacitance
Parameter Input capacitance Output capacitance Input/output capacitance
Symbol
Condition Frequency: Frequency: Frequency:
MIN.
TYP.
MAX.
Unit
Recommended Operating Conditions
Parameter Power supply voltage Operating temperature range Low-level input voltage
Symbol VIL1 VIL2
Condition
MIN. 0.95
TYP.
MAX. 1.05 1.50 5.25 0.40 1900
Unit
other than P-ECL level P-ECL level other than P-ECL level P-ECL level
2.82 1.49
High-level input voltage
VIH1 VIH2
Differential input voltage
VIDIFF2
Remark
P-ECL level pins RDIT, RDIC, RCIT, RDIC, TDOT, TDOC, TCOT, TCOC, TFKT, TFKC Analog pins AIN1
Data Sheet S11822EJ4V0DS00
µPD98404
Characteristics (VDD ±0.15 +85°C)
Parameter Off-state output current Input leakage current Symbol ILI1 Condition other than P-ECL level ILI2 Low-level output voltage VOL1 P-ECL level +8mA, other than P-ECL level VOL2 P-ECL level High-level output voltage VOH1 other than P-ECL level VOH2 P-ECL level Power supply current During normal operation 1.14 0.92 0.69 2.175 1.975 1.755 MIN. TYP. MAX. Unit
Characteristics (VDD ±0.15 +85°C) Test Condition propagation delay time defined shown below.
0.7VDD Input 0.3VDD 0.5VDD
Output
0.5VDD
Testing Load Circuit
Device Under Test
50pF
Data Sheet S11822EJ4V0DS00
µPD98404
Management Interface Internal register read
Parameter Address setup time DS_B [RD_B]) CS_B setup time DS_B [RD_B]) R/W_B[WR_B] setup time DS_B [RD_B]) Address hold time DS_B [RD_B]) CS_B hold time DS_B [RD_B]) R/W_B [WR_B] hold time DS_B [RD_B]) DS_B [RD_B] ACK_B [RDY_B] output delay time DS_B [RD_B] data output delay time DS_B [RD_B] ACK_B [RDY_B] float delay time DS_B [RD_B] data float delay time data output delay time DS_B[RD_B] pulse width
Note
Symbol tSADDS tSCSDS tSRWDS tHADDS tHCSDS tHRWDS tVAKDS tVDADS tIAKDSR tIDADS tDDAAK tWDS tDSINT
Condition
MIN.
TYP.
MAX.
Unit
tCYTK
Load capacity Load capacity Load capacity Load capacity Load capacity tCYTK
DS_B[RD_B]DS_B[RD_B] recovery time
Note tWDS defines time during which µPD98404 recognize DS_B [RD_B] level, does define pulse width DS_B [RD_B] with which data accurately read. time required µPD98404 make ACK_B [RDY_B] after DS_B [RD_B] gone differs depending register accessed. Make DS_B [RD_B] high after confirming that ACK_B [RDY_B]. time required µPD98404 make ACK_B [RDY_B] after DS_B [RD_B] gone TCLK clock cycle (tCYTK)" best. that register read without using ACK_B [RDY_B], widen pulse width DS_B [RD_B] least TCLK clock cycle". Remark tCYTK cycle TCLK clock.
Data Sheet S11822EJ4V0DS00
µPD98404
When MSEL (Motorola compatible)
MADD0 MADD6 tSADDS CS_B tSCSDS tVDADS DS_B tWDS R/W_B tSRWDS ACK_B tVAKDS tIAKDSR tHRWDS Invalid tDDAAK Data tIDADS tHCSDS tHADDS
(ii) When MSEL (Intel compatible)
MADD0 MADD6 tSADDS CS_B tSCSDS tVDADS RD_B tWDS WR_B tSRWDS RDY_B tVAKDS tIAKDSR tHRWDS Invalid tDDAAK Data tIDADS tHCSDS tHADDS
Data Sheet S11822EJ4V0DS00
µPD98404
Internal register write
Parameter Address setup time DS_B [WR_B]) CS_B setup time DS_B [WR_B]) R/W_B[RD_B] setup time DS_B [WR_B]) Data setup time DS_B [WR_B]) Address hold time DS_B [WR_B]) CS_B hold time DS_B [WR_B]) R/W_B [WR_B] hold time DS_B [WR_B]) Data hold time DS_B [WR_B]) DS_B [WR_B] ACK_B [RDY_B] output delay time DS_B [WR_B] ACK_B [RDY_B] float delay time DS_B [WR_B] pulse width
Note
Symbol tSADDS tSCSDS tSRWDS
Condition
MIN.
TYP.
MAX.
Unit
tCYTK
tSDADS tHADDS tHCSDS tHRWDS
tHDADS tVAKDS Load capacity
tIAKDSW
Load capacity
tWDS tDSINT
tCYTK
DS_B[WR_B]DS_B[WR_B] recovery time
Note tWDS defines time during which µPD98404 recognize DS_B [WR_B] level, does define pulse width DS_B [WR_B] with which data accurately read. time required µPD98404 make ACK_B [RDY_B] after DS_B [WR_B] gone differs depending register accessed. Make DS_B [WR_B] high after confirming that ACK_B [RDY_B] gone low. time required µPD98404 make ACK_B [RDY_B] after DS_B [WR_B] gone TCLK clock cycle (tCYTK)" best. that register write without using ACK_B [RDY_B], widen pulse width DS_B [WR_B] least TCLK clock cycle". Remark tCYTK cycle TCLK clock.
Data Sheet S11822EJ4V0DS00
µPD98404
When MSEL (Motorola compatible)
MADD0 MADD6 tSADDS CS_B tSCSDS tSDADS DS_B tWDS R/W_B tSRWDS ACK_B tVAKDS tIAKDSW tHRWDS tHCSDS Data tHDADS tHADDS
(ii) When MSEL (Intel compatible)
MADD0 MADD6 tSADDS CS_B tSCSDS tSDADS WR_B tWDS RD_B tSRWDS RDY_B tVAKDS tIAKDSW tHRWDS tHCSDS Data tHDADS tHADDS
Data Sheet S11822EJ4V0DS00
µPD98404
Internal register read/write (NEASCOT-S15 connection mode, MSEL "0") Read timing
Parameter Address setup time CS_B) R/W_B setup time CS_B) Address hold time CS_B) R/W_B hold time CS_B) DS_B hold time CS_B) DS_B data output delay time DS_B data float delay time CS_B pulse width DS_B pulse width Symbol tSADCS tSRWCS tHADCSR tHRWCSR tHDSCS tVDADS tIDADS tWCS tWDS Load capacity Load capacity tCYTK tCYTK Condition MIN. tCYTK TYP. MAX. Unit
Remark
tCYTK cycle TCLK clock.
tSADCS tHADCSR tWCS CS_B tHDSCS DS_B tWDS R/W_B tSRWCS tHRWCSR Data tVDADS
MADD0 MADD6
tIDADS
Data Sheet S11822EJ4V0DS00
µPD98404
(ii) Write timing
Parameter Address setup time CS_B) R/W_B setup time CS_B) Data setup time CS_B) Address hold time CS_B) R/W_B hold time CS_B) Data hold time CS_B) CS_B pulse width Symbol tSADCS tSRWCS tSDACS tHADCSW tHRWCSW tHDACS tWCS Condition MIN. tCYTK TYP. MAX. Unit
Remark
tCYTK cycle TCLK clock.
tSADDS tHADCSW tWCS CS_B tSDACS MD0-MD7 DS_B tSRWCS R/W_B tHRWCSW Data tHDACS
MADD0-MADD6
Caution
device reset software setting CMR2 register, read write registers duration least TCLK clock cycle (tCYTK)" from that write cycle. Otherwise, registers read written correctly.
Data Sheet S11822EJ4V0DS00
µPD98404
interface
Parameter TCLK PHYARM2-0 delay time
Symbol tDARRL
Condition Load capacity
MIN.
TYP.
MAX.
Unit
TCLK tDARRL PHYARM2-0
Control signal interface
tDARRL
Parameter TFSS setup time TCL) TFSS hold time TCL) TxFP delay time RxFP delay time
Symbol tSTFTL tHTFTL tDTFTL tDRFRL
Condition
MIN.
TYP.
MAX.
Unit
Load capacity Load capacity
TFSS tSTFTL TxFP tHTFTL tDTFTL tDTFTL
tDRFRL RxFP tDRFRL
Data Sheet S11822EJ4V0DS00
µPD98404
UTOPIA interface (transmit side)
Parameter TCLK cycle time TCLK high level width TCLK level width TCLK TCLAV delay time TCLK TCLAV output delay time TCLK TCLAV data float delay time TDI0-7 setup time TCLK) TDI0-7 hold time TCLK) TSOC setup time TCLK) TSOC hold time TCLK) TADD0-7 setup time TCLK) TADD0-7 hold time TCLK) TENBL_B setup time TCLK) TENBL_B hold time TCLK)
Symbol tCYTK tWTKH tWTKL tDCATK tVCATK tICATK tSDITK tHDITK tSSOTK tHSOTK tSADTK tHADTK tSENTK tHENTK
Condition
MIN. tCYTK tCYTK
TYP.
MAX. tCYTK tCYTK
Unit
Load capacity Load capacity Load capacity
tCYTK tWTKH TCLK tSADTK TADD0-7 TCLAV tDCATK TENBL_B tSSOTK TSOC tSDITK TDI0-7 tHDITK tHSOTK tSENTK tHENTK tDCATK tICATK tVCATK tHADTK tWTKL
Data Sheet S11822EJ4V0DS00
µPD98404
UTOPIA interface (receive side)
Parameter RCLK cycle time RCLK high level width RCLK level width RCLK RCLAV delay time RCLK RCLAV output delay time RCLK RCLAV data float delay time RCLK RDO0-7 delay time RCLK RDO0-7 output delay time RCLK RDO0-7 data float delay time RCLK RSOC delay time RCLK RSOC output delay time RCLK RSOC data float delay time RADD0-7 setup time RCLK) RADD0-7 hold time RCLK) RENBL_B setup time RCLK) RENBL_B hold time RCLK)
Symbol tCYRK tWRKH tWRKL tDCARK tVCARK tICARK tDDORK tVDORK tIDORK tDSORK tVSORK tISORK tSADRK tHADRK tSENRK tHENRK
Condition
MIN. tCYRK tCYRK
TYP.
MAX.
Unit
tCYRK tCYRK
Load capacity Load capacity Load capacity Load capacity Load capacity Load capacity Load capacity Load capacity Load capacity
tCYTK tWTKH TCLK tSADTK TADD0-7 TCLAV tDCATK TENBL_B tSSOTK TSOC tSDITK TDI0-7 tHDITK tHSOTK tSENTK tHENTK tDCATK tICATK tVCATK tHADTK tWTKL
Data Sheet S11822EJ4V0DS00
µPD98404
parallel interface (receive side)
Parameter cycle time high level width level width RPD0 RPD7 setup time RPC) RPD0 RPD7 hold time RPC)
Symbol tCYRP tWRPH tWRPL tSPDRP tHPDRP
Condition
MIN. tCYRP tCYRP
TYP.
MAX.
Unit
tCYRP tCYRP
tCYRP tWRPH tSPDRP RPD0-7 tHPDRP tWRPL
parallel interface (transmit side)
Parameter cycle time high level width level width delay time delay time TPD0-TPD7 delay time Symbol tCYTF tWTFH tWTFL tDPCTFH tDPCTFL tDPDTC Load capacity Load capacity Load capacity Condition MIN. tCYTF tCYTF tCYTF tCYTF TYP. MAX. Unit
tCYTF tWTFH tDPCTFH tDPDTC TPD0-7 tDPCTFL tWTFL
Data Sheet S11822EJ4V0DS00
µPD98404
serial interface (transmit side)
Parameter REFCLK cycle time
Note
Symbol tCYRF tWRFH tWRFL tCYSF
Condition
MIN. -20ppm tCYRF tCYRF -0.005UI
TYP. 51.4403
MAX. +20ppm tCYRF tCYRF
Unit
REFCLK high level width REFCLK level width TFKT(C) cycle time
6.43
+0.005UI
Caution
clock which jitter below 0.01UI, basis signal which least equal more than precision must inputted.
When using clock synthesizer
tCYRF tWRFH REFCLK tWRFL
(ii) When using external serial clock
tCYSF TFKT (TFKC)
Data Sheet S11822EJ4V0DS00
µPD98404
serial interface (receive side)
Parameter RCIT(RCIC) cycle time RDIT(RCIC) setup time RDIT(RCIC) hold time
Symbol tCYSC tSDISC tHDISC
Condition
MIN. -0.005UI
TYP. 6.43
MAX. +0.005UI
Unit
tCYSC RCIT (RCIC) tSDISC RDIT (RDIC) tHDISC
Data Sheet S11822EJ4V0DS00
µPD98404
PACKAGE DRAWINGS
PLASTIC (FINE PITCH) (20x20)
detail lead
NOTE
ITEM MILLIMETERS 22.0±0.3 20.0±0.2 20.0±0.2 22.0±0.3 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 0.125±0.075 MAX.
Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
S144GJ-50-JEU, KEU-1
Data Sheet S11822EJ4V0DS00
µPD98404
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended below, contact sales personnel. Surface Mount Type Soldering Conditions µPD98404GJ-KEU: 144-pin plastic (fine pitch)
Recommended soldering code IR35-203-2
Soldering method Infrared reflow
Soldering conditions Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less Note Exposure limit: days (after that, prebake 125°C hours) temperature: 300°C max., Duration: seconds max. (per device side)
Partial heating
Note After opening pack, store 25°C less less allowable storage period.
Data Sheet S11822EJ4V0DS00
µPD98404
[MEMO]
Data Sheet S11822EJ4V0DS00
µPD98404
[MEMO]
Data Sheet S11822EJ4V0DS00
µPD98404
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S11822EJ4V0DS00
µPD98404
NEASCOT-P30, NEASCOT-S15, NEASCOT-X15 trademarks Corporation.
information this document subject change without notice. Before using this document, please confirm that this latest version. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.

µPD98404 ADVANCED ASONET FRAMER DESCRIPTION µPD98404 NE

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