µPD78001B(A), 78002B(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESC

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µPD78001B(A), 78002B(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESC

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INTEGRATED CIRCUIT
µPD78001B(A), 78002B(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
µPD78001B(A)/78002B(A) products µPD78002 subseries within 78K/0 series. µPD78001B(A)/78002B(A) have various peripheral hardware such timer, serial interface interrupt function. one-time PROM EPROM product, µPD78P014, capable operating same power supply voltage range that mask product other development tools provided. Functions described detail following User's Manual, which should read when carrying design work. µPD78002, 78002Y Series User's Manual: IEU-1334
FEATURES
µPD78001B, comparison with 78002B, higher reliability device, result more comprehensive quality assurance program (Refer Quality Grade Semiconductor Devices (IEI-1209)) Large on-chip
Item Product Name Program Memory (ROM) bytes byte Data Memory (Internal High-Speed RAM) bytes bytes 64-pin plastic shrink (750 mil) 64-pin plastic Package
µPD78001B(A) µPD78002B(A)
External memory expansion space: bytes Instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain Serial interface channel Timer: channels Operating voltage range
APPLICATION
Transmission equipment control device, detector circuit breaker, safety devices, etc.
information this document subject change without notice.
Document IC-3599 (O.D. IC-9078) Date Published February 1995 Printed Japan
1995
µPD78001B(A), 78002B(A)
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink (750 mil) 64-pin plastic 64-pin plastic shrink (750 mil) 64-pin plastic Quality Grade Special Special Special Special
µPD78001BCW µPD78001BGC µPD78002BCW µPD78002BGC
Remark indicates code
Please refer "Quality grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
Difference between µPD78001B(A), 78002B(A) µPD78001B, 78002B.
Product Name Item Quality Grade
µPD78001B(A), 78002B(A)
µPD78001B, 78002B
Special
Standard
µPD78001B(A), 78002B(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products further development 78K/0 Series. designations appearing inside boxes subseries names.
Products Volume Production Products under Development control 100-pin 80-pin 64-pin 64-pin 64-pin 42/44-pin
series products compatible with bus.
PD78078 PD78054 PD78018F PD78014 PD78002 PD78083
PD78078Y PD78054Y µPD78018FY PD78014Y PD78002Y
Timer added PD78054, external interface functions UART added PD78014, enhanced Low-voltage (1.8 operation version PD78014, with enhanced variations 16-bit timer added PD78002 Basic subseries control Internal UART, low-voltage (1.8 operation possible
78K/0 Series FIP® driving 100-pin PD780208 80-pin µPD78044A 64-pin PD78024 driving 100-pin I/O, µPD78044A enhanced, display output total: 6-bit counter added µPD78024, display output total: Basic subseries driving, display output total:
PD78064
IEBus
PD78064Y
Subseries driving, internal UART
80-pin
PD78098
IEBus controller added µPD78054
major functional differences among subseries shown below.
Function Name Control 8-bit 16-bit Timer Watch Watchdog 8-bit MIN. Value 8-bit 8-bit (UART: 1ch) 8-bit 8-bit (UART: 1ch)
Serial Interface
External Expansion
µPD78078 µPD78054 µPD78018F µPD78014 µPD78002 µPD78083
8-bit (UART: 1ch)
driving
µPD780208 µPD78044A µPD78024
driving IEBus
µPD78064 µPD78098
8-bit (UART: 1ch)
µPD78001B(A), 78002B(A)
OVERVIEW FUNCTION
Product Name Item Internal memory Internal highspeed bytes bits registers bits registers banks) On-chip instruction execution time cycle modification function µs/0.8 µs/1.6 µs/3.2 µs/6.4 10.0 operation) 32.768 operation)
µPD78001B(A)
bytes bytes
µPD78002B(A)
bytes bytes
Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction
16-bit operation manipulation (set, reset, test, boolean operation) correction, etc. Total CMOS input CMOS N-channel open-drain withstand voltage)
ports
Serial interface Timer
3-wire/SBI/2-wire mode selectable 8-bit timer/event counter Watch timer Watchdog timer 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 main system clock 10.0 operation), 32.768 subsystem clock 32.768 operation) kHz, kHz, main system clock 10.0 operation) Internal External Internal channels channel channel
Timer output Clock output
Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt Test input
Internal
Internal External +85°C 64-pin plastic shrink (750 mil) 64-pin plastic
Operating voltage range Operating ambient temperature range Package
µPD78001B(A), 78002B(A)
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM
FUNCTIONS
PORT PINS OTHER PINS CIRCUIT RECOMMENDED CONNECTION UNUSED PINS
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS CLOCK GENERATOR TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT SERIAL INTERFACES
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS TEST FUNCTIONS
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTIONS RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVE (REFERENCE VALUES) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78001B(A), 78002B(A)
CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink (750 mil)
P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13
P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P57/A15 P56/A14
Remark
Always connect IC0, (Internally Connected) pins directly. Always connect directly.
µPD78001BCW(A)- µPD78002BCW(A)-
µPD78001B(A), 78002B(A)
64-Pin Plastic
P26/SO0/SB1
P25/SI0/SB0
P27/SCK0
P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 RESET P67/ASTB P66/WAIT
µPD78001BGC(A)- -AB8 µPD78002BGC(A)- -AB8
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P47/AD7
P64/RD
Remark
Always connect IC0, (Internally Connected) pins directly. Always connect directly.
P65/WR
µPD78001B(A), 78002B(A)
INTP0 INTP3 TI1, TO1, SB0, SCK0
Port Port Port Port Port Port Port Interrupt From Peripherals Timer Input Timer Output Serial Serial Input Serial Output Serial Clock
WAIT ASTB XT1, RESET
Programmable Clock Buzzer Clock Address/Data Address Read Strobe Write Strobe Wait Address Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Power Supply Ground Internally Connected
µPD78001B(A), 78002B(A)
BLOCK DIAGRAM
TO1/P31 TI1/P33 TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT0
P01-P03
8-bit TIMER/ EVENT COUNTER
PORT1
P10-P17
WATCHDOG TIMER 78K/0 CORE WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 INTP0/P00 INTP3/P03
PORT2
P20-P27
PORT3
P30-P37
SERIAL INTERFACE
PORT4
P40-P47
INTERRUPT CONTROL
PORT5
P50-P57
BUZ/P36
BUZZER OUTPUT
PORT6
P60-P67
PCL/P35
CLOCK OUTPUT CONTROL
AD0/P40AD7/P47 EXTERNAL ACCESS A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET XT1/P04
IC0IC3
SYSTEM CONTROL
Remark
Internal capacity varies depending product.
µPD78001B(A), 78002B(A)
FUNCTIONS
PORT PINS (1/2)
Input Input/ output Port 5-bit port Function Input only Input/output specified bit-wise. When used input port, pull-up resistor used software. Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. After Reset Input Input DualFunction INTP0 INTP1 INTP2 INTP3 Input Input/ output Input
Name P04*
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.
Input
SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
When using P04/XT1 pins input port, (FRC) processor control register. on-chip feedback register subsystem clock oscillator.)
µPD78001B(A), 78002B(A)
PORT PINS (2/2)
Input/ output Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. N-ch open-drain input/output port. Onchip pull-up resistor specified mask option. driven directly. When used input port, pull-up resistor used software. After Reset Input DualFunction
Name
Input/ output
Input
WAIT ASTB
Caution
When pull-up resistors used (specified mask option), low-level input leak current increases with -200 (MAX.) under either following conditions. When external device expansion function used low-level input pin. During 3-clock period when read instruction executed port (P6) port mode register (PM6).
µPD78001B(A), 78002B(A)
OTHER PINS
Input Function Effective edge (rising edge, falling edge, both rising edge falling edge) specified. External interrupt input. Falling edge detection external interrupt input. Input Output Input /output Input /output Serial interface serial clock input/output. Input Serial interface serial data input. Serial interface serial data output. Serial interface serial data input/output. Input Input Input After Reset Input DualFunction P25/SB0 P26/SB1 P25/SI0 P26/SO0
Name INTP0 INTP1 INTP2 INTP3 SCK0
Input
External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2).
Input
Output
8-bit timer (TM1) output. 8-bit timer (TM2) output.
Input
Output Output Input /output
Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data external memory expansion.
Input Input Input
WAIT ASTB
Output Output
High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
Input Output
Wait insertion external memory access. Strobe output which latches address information output port port access external memory.
Input Input
RESET
Input Input Input
System reset input. Main system clock oscillation crystal connection.
Subsystem clock oscillation crystal connection.
Input
Positive power supply. Ground potential. Internal connection. IC0/IC1/IC3 should connected directly VDD, respecitively.
µPD78001B(A), 78002B(A)
CIRCUIT RECOMMENDED CONNECTION UNUSED PINS input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Fig. 3-1. Table Input/Output Circuit Type Each
Input/Output Circuit Type Input Input/output
Name P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB RESET IC0, IC1,
Recommended Connection when Used Connected Connected through resistor independently.
Input Input/output
Connected Connected through resistor independently.
10-A
13-B
Connected through resistor independently. Connected through resistor independently. Connected through resistor independently. Connected through resistor independently.
Input
Leave open. Connected directly. Connected directly.
µPD78001B(A), 78002B(A)
Fig. Input/Output Circuits
Type 10-A pullup enable data open drain output disable Schmitt-Triggered Input with Hysteresis Characteristic P-ch N-ch P-ch
Type
Type pullup enable data output disable input enable Type pullup enable data output disable
P-ch
Type 13-B Mask Option data output disable N-ch P-ch
P-ch N-ch
Middle-High Voltage Input Buffer
P-ch P-ch N-ch
Type feedback cut-off P-ch
Type pullup enable data output disable
P-ch
P-ch N-ch
µPD78001B(A), 78002B(A)
MEMORY SPACE
memory µPD78001B(A)/78002B(A) shown Fig. 4-1. Fig. Memory
FFFFH Special Function Registers (SFR) Bits FF00H FEFFH FEE0H FEDFH General Registers Bits
Internal High-Speed RAM*
mmmmH mmmmH-1
nnnnH Program Area
Data Memory Space
Prohibited
1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area
FA80H FA7FH Program Memory Space nnnnH+1 nnnnH
External Memory
0080H 007FH CALLT Table Area 0040H 003FH
Internal ROM* 0000H 0000H
Vector Table Area
Remark
Shaded area indicates internal memory.
Intermal internal high-speed capacities vary depending product (see table below).
Internal Product Name Address nnnnH 1FFFH 3FFFH Internal High-Speed Start Address mmmmH FE00H FD80H
µPD78001B(A) µPD78002B(A)
µPD78001B(A), 78002B(A)
PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS port following three types. CMOS input (P00, P04) CMOS input/output (P01 P03, port port P67) N-ch open-drain input/output (15V withstand voltage) (P60 P63) Total
Table Functions Ports
Port Name Port Name P00, Port Port Port Port Dedicated Input port Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified 8-bit units. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. driven directly. N-ch open-drain input/output port. Input/output specified bit-wise. On-chip pull-up resistor specified mask option. driven directly. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Function
Port
Port
Caution
When pull-up resistors used (specified mask option), low-level input leak current increases with -200 (MAX.) under either following conditions. When external device expansion function used low-level input pin. During 3-clock period when read instruction executed port (P6) port mode register (PM6).
µPD78001B(A), 78002B(A)
CLOCK GENERATOR There types clock generator: main system clock subsystem clock. instruction exection time changed. µs/0.8 µs/1.6 µs/3.2 µs/6.4 (mainsystem clock: 10.0 operation) (subsystem clock: 32.768 operation)
Fig. Clock Generator Block Diagram
XT1/P04
Subsystem Clock Osicillator Prescaler
Watch Timer Clock Output Function
Main System Clock Osicillator
Prescaler
Clock Peripheral Hardware
STOP
Selector
Standby Control Circuit
Wait Control Circuit
Clock (fCPU)
INTP0 Sampling Clock
µPD78001B(A), 78002B(A)
TIMER/EVENT COUNTER following four channels incorporated timer/event counter. 8-bit timer/event counter Watch timer Watchdog timer channels channel channel
Table Types Features Timer/Event Counter
8-bit Timer/Event Counter
Watch Timer
Watchdog Timer
Type
Interval timer External event counter
channels channels outputs outputs
channel
channel
Functions
Timer output Sqare wave output Interrupt request
Fig. 8-Bit Timer/Enent Counter Block Diagram
Internal INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match
Output Control Circuit
TO2/P32 INTTM2
fX/2 fX/210 fX/212 TI1/P33 Selector 8-Bit Timer Register (TM1) Selector Clear 8-Bit Timer Register (TM2) Clear fX/2 fX/210 fX/212 TI1/P34 Output Control Circuit Internal Selector Selector
TO1/P31
µPD78001B(A), 78002B(A)
Fig. Watch Timer Block Diagram
fX/2 Selector
Selector Prescaler
5-Bit Counter
Selector INTWT
Selector
INTTM3
Fig. Watchdog Timer Block Diagram
Prescaler
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
µPD78001B(A), 78002B(A)
CLOCK OUTPUT CONTROL CIRCUIT clock with following frequencies output clock output. 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 (Main system clock: 10.0 operation) 32.768 (Subsystem clock: 32.768 operation) Fig. Clock Output Control Block Diagram
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 Selector Synchronization Circuit Output Control Circuit PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT clock with following frequencies output buzzer output. kHz/4.9 kHz/9.8 (Main system clock: 10.0 operation) Fig. Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212 Selector Output Control Circuit BUZ/P36
µPD78001B(A), 78002B(A)
SERIAL INTERFACES There on-chip clocked serial interface. Serial Interface channel following three modes. 3-wire serial mode (Serial Interface) mode 2-wire serial mode MSB/LSB-first switchable MSB-first MSB-first
Fig. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25 Selector SO0/SB1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Release/Command/ Acknowledge Detection Circuit Serial Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fX/22 fX/2 Serial Clock Control Circuit Selector
µPD78001B(A), 78002B(A)
INTERRUPT FUNCTIONS DEST FUNCTIONS
INTERRUPT FUNCTIONS There interrupt functions different kinds shown below. Non-maskable interrupt Maskable interrupt Software interrupt
Table Interrrupt Source List
Interrupt Type Nonmaskable Maskable Default Priority Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with nonmaskable interrupt selected) Watchdog timer overflow (with interval timer selected) input edge detection External 0006H 0008H 000AH 000CH Serial interface channel transfer Reference time interval signal from watch timer 8-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation instruction execution Internal Internal 000EH 0012H Internal/ External Internal Vector Table Adress 0004H Basic Configuration Type
INTWDT
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTTM3
INTTM1
0016H
INTTM2
0018H
Software
003EH
default priority priority applicable when more priority than maskable interrupt generated. highest lowest. Basic configuration types correspond next page.
µPD78001B(A), 78002B(A)
Fig. Interrupt Function Basic Configuration (1/2) Internal Non-Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External Maskable Interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78001B(A), 78002B(A)
Fig. Interrupt Function Basic Configuration (2/2) External Maskable Interrupt (Except INTP0)
Internal
External Interrupt Mode Register (INTM0)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Remarks
Interrupt request flag
Interrupt enable flag In-service priority flag Interrupt mask flag Priority spcification flag
µPD78001B(A), 78002B(A)
TEST FUNCTIONS There test functions shown Table 6-2. Table Test Source List
Test Source Internal/External Name INTWT NTPT4 Watch timer overflow Port falling edge detection Trigger Internal External
Fig. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Remarks
Test input flag
Test mask flag
µPD78001B(A), 78002B(A)
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion function used connect external devices areas other than internal ROM, SFR. Ports used connection with external devices.
STANDBY FUNCTIONS
There following standby functions reduce current dissipation. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operating mode. main system clock oscillation stopped. whole operation main system clock stopped, that system operates with ultra-low power consumption using only subsystem clock. Fig. Standby Functions
STOP mode
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation* HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode* (Clock supply stopped, oscillation)
power consumption reduced stopping main system clock. When operating subsystem clock, stop main system clock. STOP instruction cannot used. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program program.
Caution
RESET FUNCTION There following reset methods.
External reset input RESET pin. Internal reset watchdog timer runaway time detection.
µPD78001B(A), 78002B(A)
INSTRUCTION
8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand #byte Operand ADDC SUBC ADDC SUBC ADDC SUBC saddr ADDC SUBC !addr16 PUSH [DE] [HL] ROR4 ROL4 [HL+byte] [HL+B] [HL+C] DBNZ DBNZ ADDC SUBC ADDC SUBC ADDC SUBC saddr !addr16 [DE] [HL] [HL+byte] [HL+B] [HL+C] ADDC SUBC RORC ROLC $addr16 None
Except
µPD78001B(A), 78002B(A)
16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand #word Operand ADDW SUBW CMPW MOVW MOVW* INCW, DECW PUSH, sfrp saddrp !addr16 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW sfrp saddrp !addr16 None
Only when
Operation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand A.bit Operand A.bit MOV1 BTCLR sfr.bit MOV1 BTCLR saddr.bit MOV1 BTCLR PSW.bit MOV1 BTCLR [HL].bit MOV1 BTCLR MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit $addr16 None
µPD78001B(A), 78002B(A)
Call Instruction/Branch Instruction CALL, CALLF, CALLT, BNC, BNZ, BF,BTCLR, DBNZ
Operand Operand Basic instruction Compound instruction CALL, CALLF CALLT BNC, BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78001B(A), 78002B(A)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Symbol Output voltage Output current high P17, P27, total P03, P47, P57, total Output current Peak value Effective value P47, total Peak value Effective value IOL* P03, P56, P57, total P03, total P17, P27, total Operating ambient temperature Storage temperature Peak value Effective value Peak value Effective value Peak value Effective value P04, P17, P27, toP37 P47, P57, P67, Open-drain -0.3 -0.3 Test Conditions Rating -0.3 -0.3 Unit
Tstg
+150
Effective value should calculated follows: [Effective value] [Peak value] duty
Caution
Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximuam ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
µPD78001B(A), 78002B(A)
Capacitance
Parameter Input capacitance capacitance Unmeasured pins returned Symbol Test Conditions Unmeasured pins returned P03, P17, P27, P37, toP47, P57, MIN. TYP. MAX. Unit
Remark
characteristics dual-function port same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics
Resonator Recommended Circuit Parameter Test Conditions MIN. TYP. MAX. Unit
Ceramic resonator
Oscillator frequency (fX)
Oscillator voltage range
Oscillation stabilization time
After reaches oscillator voltage range MIN.
Crystal resonator
Oscillator frequency (fX) 8.38
Oscillation stabilization time
External clock
input
frequency (fX)
10.0
µPD74HCU04
input high/low level width (tXH tXL) 42.5
Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release.
Cautions
When using main system clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator.
When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78001B(A), 78002B(A)
Subsystem Clock Oscillation Circuit Characteristics
Resonator Recommended Circuit
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal resonator
Oscillator frequency (fXT)
32.768
Oscillation stabilization time
External clock
input
frequency (fXT)
input high/low level width (tXTH tXTL)
Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reaches oscillator voltage MIN.
Cautions
When using subsystem clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator.
subsystem clock oscillation circuit circuit with amplification level, more prone misoperation noise than main system clock. When using subsystem clock, special care needed regarding wiring method.
µPD78001B(A), 78002B(A)
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
Main System Clock Ceramic Resonator
Manufacturer Murata m.f.g. Products CSB1000J Kyocera KBR-4.19MWS 4.19 KBR-4.19MKS KBR-4.19MSA 4.19 PBRC4.19A KBR-10.0M KBR-1000F 1.00 KBR-1000Y 10.0 6.01-10.0 On-chip On-chip 4.19-6.00 On-chip On-chip 2.45-4.18 On-chip On-chip 1.80-2.44 On-chip On-chip Frequency (MHz) 1.00 1.01-1.25 1.26-1.79 Recommended Oscillation Constant (pF) (pF) Oscillation Voltage Range MIN. MAX.
Remark indicates frequency.
Subsystem Clock: Crystal Resonator
Manufacturer Products DT-38 (1TA632E00, Load capacitance 6.3pF) Frequency (MHz) Recommended Circuit Constant (pF) Daishinku corp. 32.768 (pF) Oscillation Voltage Range MIN. MAX.
Caution
Regarding oscillator circuit constant, operation guaranteed, reliability guaranteed. Customers require high reliability should directly consult resonator manufacturer.
µPD78001B(A), 78002B(A)
Characteristics
Parameter Input voltage high VIH2 VIH3 VIH4 VIH5 Symbol Test Conditions P17, P21, P23, P32, P37, P47, P57, P03, P20, P22, P27, P33, P34, RESET XT1/P04, Open-drain VDD-0.5 VDD-0.5 VDD-0.3 Input voltage VIL2 VIL3 VIL1 P17, P21, P23, P32, P47, P57, P03, P20, P22, P27, P33, P34, RESET VIL4 VIL5 XT1/P04, Output voltage high Output voltage VOL1 P03, P17, P27, P37, P47, VOH1 V,IOH -100 P57, VOL2 SB0, SB1, SCK0 open-drain pulled-up VOL3 Input leakage current high ILIH1 P03, P17, P27, P37, P47, P57, P67, RESET ILIH2 ILIH3 Input leakage current high ILIL1 XT1/P04, P03, P17, P27, P37, P47, P57, ILIL2 ILIL3 P67, RESET XT1/P04, Other than above -200
MIN.
TYP.
MAX.
Unit
VIH1
VDD-1.0 VDD-0.5
When memory expansion mode used memory expansion mode register (MM) with on-chip pull-up resistor mask option. When pull-up resistors used (specified mask option), low-level input leakage current increases with -200 (MAX.) under either following conditions. When external device expansion function used level input pin. During 3-clock period when read instruction executed port (P6) port mode registor (PM6). characteristics dual-function port same unless specified otherwise.
Remark
µPD78001B(A), 78002B(A)
Characteristics
Parameter Output leakage current high Output leakage current Mask option pullup resister Software pullup resister
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
ILOH1
VOUT
ILOL
VOUT
P03,
P17, P27, P37, P47, P57,
0.05
22.5 1650
Power supply current
IDD1
8.38 Crystal oscillation operating mode 8.38 Crystal oscillation HALT mode 32.768 Crystal oscillation operating mode 32.768 Crystal oscillation HALT mode STOP mode When feedback resister used STOP mode When feedback resister unused
IDD2
IDD3
IDD4
IDD5
IDD6
Operating high-speed mode (when processor clock control register 00H). Operating low-speed mode (when processor clock control register 04H). Port current excluded.
Remark
characteristics dual-function port same unless specified otherwise.
µPD78001B(A), 78002B(A)
Characteristics Basic Operation
Parameter Cycle time (Min. instruction execution time) input frequency input high/ low-level width Interrupt input high/low-level width RESET level width tRSL tTIH tTIL tINTH tINTL INTP0 INTP1 INTP3 Symbol Operating main system clock Operationg subsystem clock Test Conditions MIN. 0.96 8/fsam* TYP. MAX. Unit
combination with bits (SCS0) (SCS1) sampling clock select register, selection fsam possible between fX/2N+1, fX/64 fx/128 (when
µPD78001B(A), 78002B(A)
main system clock operation)
µPD78P014 (Reference)
main system clock operation)
Cycle Time [µs] Operation Guaranteed Range Cycle Time [µs]
Operation Guaranteed Range
Supply Voltage
Supply Voltage
Remark
indicates TA=-40 indicates TA=-40
Caution
operation guaranteed range µPD78001B(A), 78002B(A) differs from that µPD78P014.
µPD78001B(A), 78002B(A)
Read/Write Operation
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from tRDAST external fetch Address hold time from tRDADH external fetch Write data output time from delay time from write data tWDWR 0.5tCY-170 Address hold time from tWRADH delay time from WAIT delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+100 2.5tCY+80 2.5tCY+80 =4.5 0.5tCY tCY+60 tRDWD 0.5tCY-120 0.5tCY tCY+50 tCY-10 tCY+40 tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR (0.5+2n)tCY (2.5+2n)tCY 0.5tCY-30 1.5tCY (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY Load resistor Test Conditions MIN. 0.5tCY 0.5tCY-30 (2+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit
Remarks
TCY/4 indicates number waits. indicates load capacitance P40/AD0 P47/AD7, P50/A8 P57/A15, P64/RD, P65/WR, P66/WAIT,P67/ASTB pins).
µPD78001B(A), 78002B(A)
Serial Interface 3-wire serial mode (SCK. Internal clock output)
Parameter cycle time tKCY1 3200 high/low-level width tKH1 tKL1 setup time SCK) hold time (from SCK) output delay time from tKSO1 1000 tSIK1 tKSI1 tKCY1/2-50 tKCY1/2-150 Symbol Test Conditions MIN. TYP. MAX. Unit
load capacitance output line.
3-wire serial mode (SCK. External clock input)
Parameter cycle time tKCY2 3200 high/low-level width tKH2 tKL2 setup time SCK) hold time (from SCK) output delay time from tKSO2 rise, fall time When external device expansion function used When external device expansion function used 1000 1000 tSIK2 tKSI2 1600 Symbol Test Conditions MIN. TYP. MAX. Unit
load capacitance output line.
µPD78001B(A), 78002B(A)
mode (SCK. Internal clock output)
Parameter cycle time Symbol tKCY3 Test Conditions MIN. 3200 high/low-level width tKH3 tKL3 SB0, setup time tSIK3 SCK) SB0, hold time tKSI3 from SB0, output delay time tKSO3 (from SCK) SB0, from from SB0, SB0, high-level width SB0, low-level width tKSB tSBK tSBH tSBL tKCY3 tKCY3 tKCY3 tKCY3 1000 tKCY3/2 tKCY3/2-50 tKCY3/2-150 TYP. MAX. Unit
load resistors load capacitance output line.
mode (SCK. External clock input)
Parameter cycle time tKCY4 3200 high/low-level width tKH4 tKL4 SB0, setup time tSIK4 SCK) SB0, hold time tKSI4 (from SCK) SB0, output delay time tKSO4 from SB0, from from SB0, SB0, high-level width SB0, low-level width rise, fall time tKSB tSBK tSBH tSBL When external device expansion function used When external device expansion function used 1000 tKCY4 tKCY4 tKCY4 tKCY4 1000 tKCY4/2 1600 Symbol Test Conditions MIN. TYP. MAX. Unit
load resistors load capacitance output line.
µPD78001B(A), 78002B(A)
2-wire serial mode (SCK. Internal clock output)
Parameter cycle time tKCY5 3800 high-level width low-level width SB0, setup time tSIK5 SCK) SB0, hold time tKSI5 (from SCK) SB0, output delay time tKSO5 from 1000 tKH5 tKL5 tKCY5/2-50 tKCY5/2-50 Symbol Test Conditions MIN. 1600 TYP. MAX. Unit
load resistors load capacitance SCK0, output line.
2-wire serial mode (SCK. External clock input)
Parameter cycle time tKCY6 3800 high-level width low-level width SB0, setup time tSIK6 SCK) SB0, hold time tKSI6 (from SCK) SB0, output delay time tKSO6 from rise, fall time When external device expansion function used When external device expansion function used 1000 1000 tKCY6/2 tKH6 tKL6 Symbol Test Conditions MIN. 1600 TYP. MAX. Unit
load resistors load capacitance SCK0, output line.
µPD78001B(A), 78002B(A)
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
0.4V
Input
1/fXT
tXTL
tXTH 0.4V
Input
Timing
1/fTI
tTIL TI1,
tTIH
µPD78001B(A), 78002B(A)
Read/Write Operation External fetch wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78001B(A), 78002B(A)
External data access wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
tASTWR tWRL1
External data access (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2 tRDWD tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78001B(A), 78002B(A)
Serial Transfer Timing 3-wire serial mode:
tKCY
tKL1,2 tSIK1,2 tKSI1,2
tKH1,2
tKSO1,2
Input Data
Output Data
mode (Bus release signal transfer):
tKCY3,4 tKL3,4 tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4 tKH3,4
SB0, tKSO3,4
mode (Command signal transfer):
tKCY3,4 tKL3,4 tKSB tSBK tSIK3,4 tKSI3,4 tKH3,4
SB0, tKSO3,4
µPD78001B(A), 78002B(A)
2-wire serial mode:
tKCY5,6 tKL5,6 tSIK5,6 tKSO5,6 SB0, tKSI5,6 tKH5,6
µPD78001B(A), 78002B(A)
Data Memory Stop Mode Supply Voltage Data Retention Characteristics
Parameter Data retention VDDDR supply voltage Data retention supply current Release signal time Oscillation stabilization tWAIT wait time Release interrupt VDDDR Subsystem clock stop feed-back resister disconnected Release RESET 218/fx Symbol Test Conditions MIN. TYP. MAX. Unit
IDDDR
tSREL
combination with bits (OSTS0 OSTS2) oscillation stabilization time select register, selection 213/fx 215/fx 218/fx possible.
Data Retention Timing (STOP Mode Release RESET)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Signal)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
µPD78001B(A), 78002B(A)
Interrupt Input Timing
tINTL INTP0-INTP2
tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
µPD78001B(A), 78002B(A)
CHARACTERISTIC CURVE (REFERENCE VALUES)
(Main System Clock 8.38 MHz)
10.0
(TA=25°C) PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05 HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=8.38MHz XT=32.768kHz
0.001
Supply Voltage
µPD78001B(A), 78002B(A)
(Main System Clock 4.19 MHz)
10.0
(TA=25°C)
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05
HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=4.19MHz XT=32.768kHz
0.001
Supply Voltage
µPD78001B(A), 78002B(A)
(VDD
PCC=00H
Supply Current [mA]
PCC=01H
PCC=02H PCC=03H PCC=04H HALT Oscillation)
Clock Oscillator Frequency [MHz]
PCC=00H
Supply Current [mA]
(VDD
PCC=01H PCC=02H PCC=03H PCC=04H HALT Oscillation)
Clock Oscillator Frequency [MHz]
µPD78001B(A), 78002B(A)
(Port P67)
(TA=25 VDD=5 VDD= VDD=4 VDD=3
(P60 P63)
(TA=25
VDD=6
VDD=5
VDD=4
Output Current [mA]
Output Current [mA]
VDD=3
Output Voltage
Output Voltage
(Port
(TA=25
(Port P67)
(TA=25
VDD=6 VDD=5
Output Current High [mA]
VDD=4 VDD=3
VDD=5 VDD=4 VDD=6 VDD=3
Output Current [mA]
Output Voltage
Output Voltage High
µPD78001B(A), 78002B(A)
PACKAGE DRAWINGS DRAWINGS MASS-PRODUCTION PRODUCT PACKAGES (1/2)
64-PIN PLASTIC SHRINK (750 mil)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Caution
Dimensions materials products different from those mass-production products. Refer DRAWINGS PRODUCT PACKAGES (1/2).
µPD78001B(A), 78002B(A)
DRAWINGS MASS-PRODUCTION PRODUCT PACKAGES (2/2)
64-PIN PLASTIC
detail lead
P64GC-80-AB8-3 ITEM MILLIMETERS 17.6 14.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.10 2.55 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Caution
Dimensions materials different from those mass-production products. Refer DRAWINGS PRODUCT PACKAGES (2/2).
5°±5°
µPD78001B(A), 78002B(A)
DRAWINGS PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK (SEAM WELD) (750 mil)
0~15°
P64D-70-750A1 NOTES Each lead centerline located within 0.25 (0.01 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel. ITEM MILLIMETERS 58.16 MAX. 1.521 MAX. 1.778 (T.P.) 0.46 0.05 MIN. 1.02 MIN. 3.14 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.05 0.25 INCHES 2.290 MAX. 0.060 MAX. 0.070 (T.P.) 0.018 0.002 0.031 MIN. 0.138 0.012 0.040 MIN. 0.124 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01
+0.002
µPD78001B(A), 78002B(A)
DRAWINGS PRODUCT PACKAGES (2/2)
CERAMIC (FOR
(Bottom View)
X64B-80A-1 INCHES 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (T.P.) 0.157+0.007 -0.006 0.01 0.119 MAX. 0.022 0.039 0.047
ITEM
MILLIMETERS 22.0 14.0 14.0 22.0 0.32 (T.P.) 0.15 0.25 MAX. 0.55
µPD78001B(A), 78002B(A)
RECOMMENDED SOLDERING CONDITIONS
µPD78001B(A)/78002B(A) should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). soldering methods conditions other than those recommended below, contact sales personnel.
Table 14-1 Surface Mounting Type Soldering Conditions
Soldering Method Infrared reflow
64-Pin Plastic 64-Pin Plastic
Recommended Condition Symbol IR35-00-2
Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Twice max. Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided.
Package peak temperature: 215°C, Duration: sec. max. 200°C above) Number times: Twice max. Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided.
VP15-00-2
part heating temperature: 300°C max., Duration: sec. max. (per device side)
Caution
more than soldering method should avoided (except case part heating).
Table 14-2 Insertion Type Soldering Conditions
Soldering Method Wave soldering (Pin only) part heating
64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil)
Soldering Conditions Solder bath temperature: 260°C max., Duration: sec. max. temperature: 300°C max., Duration: sec. max. (per pin)
Caution
Wave soldering only pins order that solder contact with chip directly.
µPD78001B(A), 78002B(A)
APPENDIX DEVEROPMENT TOOLS
following development tools available system development using µPD78001B(A), 78002B(A). Language Processing Software
RA78K/0*1, CC78K/0*1, DF78002*1, CC78K/0-L
78K/0 series common assembler package 78K/0 series common compiler package
µPD78002 subseries device file
78K/0 series common compiler library source file
PROM Programming Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controller*1, PROM programmer Programmer adapter connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0*1, SM78K/0 DF78002
78K/0 series common in-circuit emulator 78K/0 series common break board
µPD78002/78014 subseries evaluation emulation board
Emulation probe common µPD78244 subseries Socket mounted user system board created 64-pin plastic IE-78000-R screen debugger 78K/0 series common system simulator
µPD78002 subseries device file
Enbedded
MX78K/0*1, 78K/0 series common enbedded
Fuzzy Inference Development Support System
FE9000*1/FE9200*5 FT9080 /FT9085 FI78K0*1, FD78K0*1,
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
PC-9800 series (MS-DOSTM) based. PC/AT(PC DOSTM) based. HP9000 series 300TM, HP9000 series 700(HP-UXTM) based, SPARCstationTM, (Sun OSTM) based, EWS-4800 series (EWS-UX/V) based. PC-9800 series (MS-DOS WindowsTM) based.
µPD78001B(A), 78002B(A)
PC/AT Windows) based. Under development. Remarks development tools manufactured third party, "78K/0 Series Selection Guide" (IF1185). RA78K/0, CC78K/0, SD78K/0, SM78K/0 used combination with DF78002.
µPD78001B(A), 78002B(A)
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual 78K/0 Series User's Manual Instruction Application Note Basic Basic Document (Japanese) IEU-788 IEU-849 IEA-715 IEA-740 Document (Engligh) IEU-1334 IEU-1372 IEA-1288 IEA-1299
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240 SD78K/0 Screen Debugger Beginner's guide Reference Document (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-805 EEU-986 EEU-852 EEU-816 Document (Engligh) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1400 preparation EEU-1414 EEU-1413
Embedded Software Documents (User's Manual)
Document Name Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator Document (Japanese) EEU-892 EEU-862 Document (Engligh) EEU-1438 EEU-1444
Caution
These documents above subject change without notice. Besure latest document designing your system.
µPD78001B(A), 78002B(A)
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade Semiconductor Devices Semiconductor Device Quality Guarantee Guide Document (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document (Engligh) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution
These documents above subject change without notice. Besure latest document designing your system.
µPD78001B(A), 78002B(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must Semiconductor adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78001B(A), 78002B(A)
[MEMO]
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export reexport this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product. registered trademark Corporation. IEBus trademark Corporation. MS-DOS Windows trademarks Microsoft Corporation. PC/AT trademarks Corporation. HP9000 Series 300, HP9000 Series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc.
94.11

µPD78001B(A), 78002B(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESC

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