Operation Inputs Accept Voltages 3-State Inverting Outputs Drive Lines

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Operation Inputs Accept Voltages 3-State Inverting Outputs Drive Lines

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SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
Operation Inputs Accept Voltages 3-State Inverting Outputs Drive Lines Directly Full Parallel Access Loading
SN54AC534 PACKAGE SN74AC534 PACKAGE (TOP VIEW)
description/ordering information
These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. devices particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. positive transition clock (CLK) input, outputs complements logic levels data inputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations flip-flops. data retained data entered while outputs high-impedance state. ORDERING INFORMATION
PDIP SOIC -40°C 85°C 40°C SSOP TSSOP CDIP -55°C 125°C LCCC PACKAGE Tube Tube Tape reel Tape reel Tape reel Tape reel Tube Tube Tube
SN54AC534 PACKAGE (TOP VIEW)
ORDERABLE PART NUMBER SN74AC534N SN74AC534DW SN74AC534DWR SN74AC534NSR SN74AC534DBR SN74AC534PWR SNJ54AC534J SNJ54AC534W SNJ54AC534FK
SNJ54AC534FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
DALLAS, TEXAS 75265
TOP-SIDE MARKING SN74AC534N AC534 AC534 AC534 AC534 SNJ54AC534J SNJ54AC534W
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
description/ordering information (continued)
ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver.
FUNCTION TABLE (each flip-flop) INPUTS OUTPUT
logic diagram (positive logic)
Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through ±200 Package thermal impedance, (see Note package 70°C/W package 58°C/W package 69°C/W package 60°C/W package 83°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
POST OFFICE 655303
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SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AC534 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise fall rate 3.15 3.85 1.35 1.65 SN74AC534 3.15 3.85 1.35 1.65 ns/V UNIT
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, 2.56 3.86 4.86 0.36 0.36 0.36 ±0.5 ±0.1 25°C SN54AC534 SN74AC534 2.46 3.76 4.76 0.44 0.44 0.44 ±2.5 UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C fclock Clock frequency Pulse duration, high Setup time, data before Hold time, data after SN54AC534 SN74AC534 UNIT
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C fclock Clock frequency Pulse duration, high Setup time, data before Hold time, data after SN54AC534 SN74AC534 UNIT
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC534 17.5 16.5 15.5 15.5 16.5 13.5
range,
UNIT
25°C 12.5 12.5 13.5
SN54AC534
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC534 13.5 12.5 12.5 11.5 11.5 12.5
range,
UNIT
25°C 10.5 11.5
SN54AC534
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT Timing Input Input VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input
Input tPLH tPHL Out-of-Phase Output tPHL tPLH
Output Control (low-level enabling) tPZL Output Waveform (see Note tPZH Output Waveform Open (see Note
tPLZ tPHZ
In-Phase Output
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
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MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
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MECHANICAL DATA
MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.020 (0,51) 0.014 (0,35)
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
0.010 (0,25)
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25)
Gage Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) 0.012 (0,30) 0.004 (0,10) PINS 0.004 (0,10)
0.410 (10,41) 0.400 (10,16)
0.462 (11,73) 0.453 (11,51)
0.510 (12,95) 0.500 (12,70)
0.610 (15,49) 0.600 (15,24)
0.710 (18,03) 0.700 (17,78) 4040000/E 08/01
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MS-013
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
POST OFFICE 655303
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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
POST OFFICE 655303
DALLAS, TEXAS 75265
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Operation Inputs Accept Voltages 3-State Inverting Outputs Drive Lines

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