KS57C5616/P5616 single-chip CMOS microcontroller designed high perform
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KS57C5616/P5616
KS57C5616/P5616 single-chip CMOS microcontroller designed high performance application Caller-ID, Telephone using Samsung's newest 4-bit core, SAM47 (Samsung Arrangable Microcontrollers). Featuring DTMF generator, up-to-960-dot direct drive capability, 8-bit timer/counter flexible 8-bit timer/counters, serial interface, KS57C5616/P5616 offer excellent design solution wide variety applications requiring DTMF, support. (including COM/SEG) pins 100-pin package dedicated I/O. Nine vectored interrupts provide fast response internal external events. addition advanced CMOS technology KS57C5616/P5616 ensures power consumption with wide operating voltage range.
KS57C5616 microcontroller also available (One Time Programmable) version, KS57P5616. KS57P5616 microcontroller on-chip 16K-byte one-time-programmable EPROM instead masked ROM. KS57P5616 comparable KS57C5616, both function configuration.
KS57C5616/P5616
FEATURES SUMMARY
Memory 8-bit 5,120 4-bit (excluding RAM) 8-bit Serial Interface 8-bit transmit/receive mode 8-bit receive mode LSB-first MSB-first transmission selectable
Pins Input only: 4pins (Not including COM/SEG) 6pins (Including COM/SEG) I/O: 15pins (Not including COM/SEG) 43pins (Including COM/SEG)
Controller/Driver terminals selectable 8-15: shared with port SEG40-59: shared with port kinds bias resistor value
Memory-Mapped Structure Data memory bank
Sequential Carrier Supports 16-bit serial data transfer arbitrary format
8-bit Basic Timer Four interval timer functions Watchdog timer
Interrupts Four external interrupt vectors Five internal interrupt vectors quasi-interrupts
8-bit Timer/Counter Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Power-Down Modes Idle mode (only clock stops) Stop mode (main system oscillation stops) Subsystem clock stop mode
16-Bit Timer/Counter Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider Configurable 8-bit Timers Serial interface clock generator
Oscillation Sources Crystal Ceramic system clock Oscillation frequency: 0.4-6.0 clock divider circuit
Instruction Execution Times 1.12, 2.23, 17.88 3.58 0.67, 1.33, 10.7 32.768 (subsystem)
Watch Timer Time interval generation: 32.768 frequency outputs (0.5, kHz) 32.768
Operating Temperature
Comparator 4-channel mode: Internal reference (4-bit resolution); 16-step variable reference voltage 3-channel mode: External reference
Operating Voltage Range (except DTMF Comparator) (include DTMF) (include Comparator)
DTMF Generator dual-tone tone dialing
Package Type 100-pin (1420C)
KS57C5616/P5616
BLOCK DIAGRAM
P7.0/SEG55/CIN0 P7.1/SEG54/CIN1 P7.2/SEG53/CIN2 P7.3/SEG52/CIN3 P1.0-P1.3/ INT0-INT4 P2.0/CLO P2.1/VLC1 P2.2 P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 P4.0-P4.3/ COM8-COM11 P5.0-P5.3/ COM12-COM15 P6.0-P6.3 SEG59-SEG56/ KS4-KS7 P7.0/SEG55/CIN0 P7.1/SEG54/CIN1 P7.2/SEG53/CIN2 P7.3/SEG52/CIN3 P8.0/SEG51/LCDCK P8.1/SEG50/LCDSY P8.2/SEG49 P8.3/SEG48 P9.0-P9.3/ SEG47-SEG44 P10.0-P10.3/ SEG43-SEG40
Comparator RESET Input Port XOUT XTIN XTOUT
Basic Timer Watch Timer
Watchdog Timer
Port
Interrupt Control Block
Clock
Instruction Register Driver/ Controller Program Counter
VLC1 COM0-COM7 P4.0-P5.3/ COM8-COM15 SEG0-SEG39 P10.3-P6.0/ SEG40-SEG59
Port Internal Interrupts
Port Port
Instruction Dcoder Port Port Arithmetic Logic Unit
Serial Program Status Word Port Stack Pointer
P0.0/SCK/KO P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 DTMF
DTMF Generator
Port Port 8-Bit Timer/ Counter 16-Bit Timer/Counter (Two 8Bit Timer/Counter) 4-bit 16KB
Port
Figure 1-1. KS57C5616 Block Diagram
KS57C5616/P5616
ASSIGNMENTS
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DTMF P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 XOUT TEST XTIN XTOUT
RESET
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/VLC1 P2.2 P3.0/TCLO0
SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P10.3/SEG40 P10.2/SEG41 P10.1/SEG42 P10.0/SEG43 P9.3/SEG44 P9.2/SEG45 P9.1/SEG46 P9.0/SEG47 P8.3/SEG48 P8.2/SEG49 P8.1/SEG50/LCDSY P8.0/SEG51/LCDCK P7.3/SEG52/CIN3 P7.2/SEG53/CIN2 P7.1/SEG54/CIN1 P7.0/SEG55/CIN0 P6.3/SEG56/K7 P6.2/SEG57/K6 P6.1/SEG58/K5
Figure 1-2. KS57C5616 Assignments (100-QFP Package)
P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 P4.0/COM8 P4.1/COM9 P4.2/COM10 P4.3/COM11 P5.0/COM12 P5.1/COM13 P5.2/COM14 P5.3/COM15 P6.0/SEG59/K4
KS57C5616 (100-QFP-1420C)
KS57C5616/P5616
DESCRIPTIONS
Table 1-1. KS57C5616 Descriptions Name P0.0 P0.1 P0.2 P0.3 Type Description 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. Individual pins software configurable open-drain push-pull output. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins. 4-bit input port. 1-bit 4-bit read test possible. 4-bit pull-up resistors software assignable. Same port except that port 3-bit port. Share
SCK/K0
SO/K1 SI/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
INT0 INT1 INT2 INT4 VLC1 TCLO0 TCLO1 TCL0 TCL1 COM8-COM11 COM12-COM15
Same port
4-bit ports. 4-bit 8-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins. Same
P6.0-P6.3
SEG59- SEG56/K4-K7 SEG55/CIN0- SEG52/CIN3
P7.0-P7.3 P8.0-P8.1 Input ports. 4-bit 8-bit read test possible. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins. These pins used push-pull output. Refer NOTES Table 10-3. Port Mode Group Flags. Same
SEG51/LCDCK SEG50/LCDSY
P8.2-P8.3
SEG49 SEG48 SEG47-SEG44
P9.0-P9.3 P10.0-P10.3
Same Serial interface clock signal. Serial data output.
SEG43-SEG40 P0.0/K0 P0.1/K
KS57C5616/P5616
Table 1-1. KS57C5616 Descriptions (Continued) Name INT0, INT1 INT2 INT4 TCLO0 TCLO1 TCL0 TCL1 CIN0 CIN1 CIN2 CIN3 DTMF LCDCK LCDSY COM0-COM7 COM8-COM11 COM12-COM15 SEG0-SEG39 SEG40-SEG59 K0-K3 K4-K7
RESET
Type Serial data input.
Description 0.5, frequency output buzzer sound. External interrupts. triggering edge INT0 INT1 selectable. Quasi-interrupt with detection rising falling edges. External interrupt with detection rising falling edge. Clock output Timer/counter clock output. Timer/counter clock output. External clock input timer/counter External clock input timer/counter 4-Channel comparator input CIN0-CIN2: comparator input only CIN3: comparator input external reference input DTMF output clock output synchronization clock output. common signal output.
Share P0.2/K2 P0.3/K3 P1.0, P1.1 P1.2 P1.3 P2.0 P3.0 P3.1 P3.2 P3.3 P7.0/SEG55 P7.1/SEG54 P7.2/SEG53 P7.3/SEG52 P8.0/SEG51 P8.1/SEG50 P4.0-P4.3 P5.0-P5.3
segment signal output. External interrupt (triggering edge selectable) Main power supply. Ground. Reset signal. power supply. Crystal, Ceramic oscillator pins system clock. Crystal oscillator pins subsystem clock. Chip test input pin. Hold when device operating.
P10.3-P6.0 P0.0-P0.3 P6.0-P6.3
VLC1 XIN, XOUT XTIN, XTOUT TEST
NOTE: Pull-up resistors ports automatically disabled they configured output mode.
KS57C5616/P5616
Table 1-2. Supplemental KS57C5616 Data Names P0.0-P0.3 P1.0-P1.3 P2.0 P2.1 P2.2 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.2 P7.3 P8.0-P8.1 P8.2-P8.3 P9.0-P9.3 P10.0-P10.3 COM0-COM7 SEG0-SEG39 DTMF
RESET
Share Pins
SCK/K0, SO/K1,
Type
RESET
Value
Circuit Type H-24 H-25 H-26 H-27 H-28 H-24 H-24 H-24
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input High High High impedance
SI/K2, BUZ/K3 INT0, INT1 INT2, INT4 VLC1 TCLO0, TCLO1 TCL0, TCL1 COM8-COM11 COM12-COM15 SEG59/K4- SEG56/K7 SEG55/CIN0- SEG53/CIN2 SEG52/CIN3 SEG51-SEG50 SEG49-SEG48 SEG47-SEG44 SEG43-SEG40
VLC1 XIN, XOUT XTIN, XTOUT TEST
KS57C5616/P5616 (Preliminary Spec)
CIRCUIT DIAGRAMS
Pull-Up Resistor
P-Channel N-Channel
Schmitt Trigger
Figure 1-3. Circuit Type
Figure 1-5. Circuit Type
Pull-Up Resistor Pull-Up Resistor Enable Data
P-CH
Output DIsable Schmitt Trigger
N-CH
Figure 1-4. Circuit Type
Figure 1-6. Circuit Type
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable N-CH
P-CH Data Output DIsable
Figure 1-7. Circuit Type
Pull-up Resistor Pull-up Resistor Enable N-CH
P-CH Data Output DIsable
Schmitt Trigger
Figure 1-8. Circuit Type
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable N-CH
P-CH Data Output DIsable
Digital Input VLCEN
Figure 1-9. Circuit Type
1-10
KS57C5616/P5616
VLC2
VLC3
COM/SEG
VLC4
VLC5
VLC6
Figure 1-10. Circuit Type
KS57C5616/P5616
VLC2
VLC3
SEG/COM Data Output DIsable
VLC4
VLC5
Figure 1-11. Circuit Type H-23
1-12
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Circuit Type H-23 Circuit Type
Figure 1-12. Circuit Type H-24
Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Circuit Type H-23 Circuit Type
Figure 1-13. Circuit Type H-25
1-13
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Analog Input Digital Circuit Type H-23 Circuit Type P-CH
Analog
Figure 1-14. Circuit Type H-26
1-14
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable COM/SEG Data Output DIsable Analog Input Digital Circuit Type H-23 Circuit Type P-CH
External
Analog External
Figure 1-15. Circuit Type H-27
1-15
KS57C5616/P5616
Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON LCDCK/CLDSY LCDCK/LCDSY Enable Circuit Type H-23 Circuit Type
Output DIsable
Figure 1-16. Circuit Type H-28
DTMF Disable
Figure 1-17. Circuit Type
1-16
KS57C5616/P5616
ADDRESS SPACES
ADDRESS SPACES
PROGRAM MEMORY (ROM)
maps KS57C5616 devices mask programmable factory. standard configuration, device's 16,384 8-bit program memory three areas that directly addressable program counter (PC): Table 2-1. Program Memory Address Ranges Area Function Vector address area General-purpose program memory instruction look-up table area General-purpose program memory VECTOR ADDRESSES AREA 16-byte vector address area used store vector addresses executing system resets interrupts. starting addresses interrupt service routines stored this area, along with enable memory bank (EMB) enable register bank (ERB) flag values that needed initialize service routines. 16-byte vector addresses organized follows: PC13 PC12 PC11 PC10 Address Ranges 0000H-000FH 0010H-001FH 0020H-007FH 0080H-3FFFH Area Size Bytes)
vector address area specific programs, instruction VENTn. programming tips next page explain this. INSTRUCTIONS Locations 0020H-007FH used reference area (look-up table) 1-byte instructions. instruction reduces byte size instruction operands. reference 2-byte instruction, 1-byte instructions, 3-byte instructions which stored look-up table. Unused look-up table addresses used general-purpose ROM.
ADDRESS SPACES
KS57C5616/P5616
GENERAL-PURPOSE MEMORY AREAS 16-byte area locations 0010H-001FH 16,256-byte area locations 0080H-3FFFH used general-purpose program memory. Unused locations vector address area instruction look-up table areas used general-purpose program memory. However, care must taken overwrite live data when writing programs that special-purpose areas ROM.
0000H Vector Address Area bytes) 000FH 0010H General Purpose Area bytes) 001FH 0020H Instruction Reference Area bytes) 007FH 0080H 0006H 0008H 000AH General Purpose Area (16,256 bytes) 000CH 000EH 3FFFH 0000H 0002H 0004H
RESET
INTB/INT4 INT0 INT1 INTS INTT0/INTT1B INTT1 (INTT1A) INTK
Figure 2-1. Address Structure
Figure 2-2. Vector Address
KS57C5616/P5616
ADDRESS SPACES
PROGRAMMING Defining Vectored Interrupts
following examples show several ways define vectored interrupt instruction reference areas program memory: When vector interrupts used: VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 0,0,INTS 0,0,INTT0 0,0,INTT1 0,0,INTK Jump RESET address Jump INTB address Jump INT0 address Jump INT1 address Jump INTS address Jump INTT0 address Jump INTT1 address Jump INTK address 0000H
When specific vectored interrupt such INT0, INTT0 used, unused vector interrupt locations must skipped with assembly instruction that jumps will address correct locations: VENT0 VENT1 VENT3 VENT4 VENT6 VENT7 0010H 0,0,INTT1 0,0,INTK Jump INTT1 address Jump INTK address 000CH INTT0 interrupt used 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0,0,INTS Jump RESET address Jump INTB address INT0 interrupt used Jump INT1 address Jump INTS address 0000H
ADDRESS SPACES
KS57C5616/P5616
PROGRAMMING Defining Vectored Interrupts (Continued)
INT0 interrupt used corresponding vector interrupt area fully utilized, written instruction Example malfunction will occur: VENT0 VENT1 VENT3 VENT4 VENT5 VENT6 VENT7 General-purpose area this example, when INTS interrupt generated, corresponding vector area VENT4 INTS, VENT5 INTT0. This causes INTS interrupt jump incorrectly INTT0 address causes malfunction occur. 0010H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTS 0,0,INTT0 0,0,INTT1 0,0,INTK Jump RESET address Jump INTB address Jump INT1 address INT0 Jump INTS address INT1 Jump INTT0 address INTS Jump INTT1 address INTT0 Jump INTK address INTT1 0000H
KS57C5616/P5616
ADDRESS SPACES
INSTRUCTION REFERENCE AREA Using 1-byte instructions, easily reference instructions with larger byte sizes that stored addresses 0020H-007FH program memory. This 96-byte area called instruction reference area, look-up table. Locations look-up table contain one-byte instructions, single two-byte instruction, three-byte instruction such (jump) CALL. starting address instruction referencing must always even number. reference CALL instruction, must written reference area two-byte format: this format TJP; CALL, TCALL. summary, there three ways instruction: using instructions execute instructions larger than byte. summary, there three ways instruction: Using 1-byte instruction execute 2-byte 1-byte instructions, Branching location referencing branch instruction stored look-up table, Calling subroutines location referencing call instruction stored look-up table.
PROGRAMMING Using Look-Up Table
Here example instruction look-up table: JMAIN KEYCK WATCH INCHL BTSF TCALL INCS 0020H MAIN KEYFG CLOCK @HL,A MAIN KEYFG CHECK Call CLOCK (HL)
MAIN
EA,#00H 0080
#00H
KEYCK JMAIN WATCH INCHL
BTSF KEYFG (1-byte instruction) KEYFG jump MAIN (1-byte instruction) KEYFG CALL CLOCK (1-byte instruction) @HL,A INCS EA,#00H (1-byte instruction)
ADDRESS SPACES
KS57C5616/P5616
DATA MEMORY (RAM)
OVERVIEW standard configuration, data memories four areas: 4-bit working register area 4-bit general-purpose area bank which also used stack area pages with 4-bit bank1 pages general purpose area (00H-12H page) page Display data memory (13H page) 4-bit area bank memory-mapped addresses make easier reference, data memory area three memory banks bank bank bank select memory bank instruction (SMB) used select bank want working data memory. Data stored locations 8-bit addressable. Initialization values data memory area defined hardware must therefore initialized program software after power RESET. However, when RESET signal generated power-down mode, data memory contents held. BANK1 PAGE SELECTION REGISTER (PASR) PASR 8-bit register selecting page bank1, mapped address, F8AH-F8BH. should read written 8-bit control instruction only bits should "0". PASR retains existing value long change required, RESET value Therefore, when returns bank1 from other bank (bank0 bank15) without changing contents PASR, previously specified page selected. PASR must changed interrupt service routine because value cannot recovered original value when routine finished.
KS57C5616/P5616
ADDRESS SPACES
000H
Working Registers Bank (EMB=1, SMB=0) 020H GeneralPurpose Stack Registers 0FFH 100H GeneralPurpose Registers Page (00H) 1FFH 100H 100H 100H 100H 100H 100H Page 100H Page 100H (01H) Page 100H (02H) Page 100H (03H) Page 100H (04H) Page (05H) Page (06H) (07H) Page 1FFH Page 1FFH (1BH) Page 1FFH (1CH) Page 1FFH (1DH) 1FFH (1EH) 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 100H
Bank (EMB=1, SMB=1)
F80H Bank15 (EMB=1, SMB=15 EMB=0) FFFH Peripheral Hardware Register
COM0 100H 110H 120H 130H 101H 111H 121H 131H
10EH 11EH 12EH 13EH
Display Data Registers
COM1 COM2 COM3
Page (13H)
COM12 COM13 COM14 COM15
1C0H 1D0H 1E0H 1F0H
1CEH 1DEH 1EEH 1FEH
1CEH 1DEH 1EEH 1FEH
Figure 2-3. Data Memory (RAM)
ADDRESS SPACES
KS57C5616/P5616
Memory Banks Bank (000H-0FFH) lowest nibbles bank (000H-01FH) used working registers; next nibbles (020H-0FFH) used both stack area general-purpose data memory. stack area implementing subroutine calls returns, interrupt processing. Bank data memory pages, first pages generalpurpose data memory comprised 4-bits, 20th page display data memory consists 4-bits. KS57C5616 uses specially page selection register (PASR) selecting these pages. microcontroller uses bank memory-mapped peripheral I/O. Fixed locations each peripheral hardware address mapped into this area.
Bank
(100H-1FFH)
Bank
(F80H-FFFH)
Data Memory Addressing Modes enable memory bank (EMB) flag controls addressing mode data memory banks When flag logic zero, addressable area restricted specific locations, depending whether direct indirect addressing used. With direct addressing, access locations 000H-07FH bank bank With indirect addressing, only bank (000H-0FFH) accessed. When flag logic one, three data memory banks accessed according current value. 8-bit addressing, 4-bit registers addressed register pair. Also, when using 8-bit instructions address locations, remember even-numbered register address instruction operand. Working Registers working register area data memory bank further divided into four register banks (bank Each register bank eight 4-bit registers paired 4-bit registers 8-bit addressable. Register used 4-bit accumulator register pair 8-bit extended accumulator. carry flag also used 1-bit accumulator. Register pairs used address pointers indirect addressing. limit possibility data corruption incorrect register addressing, advisable register bank main program banks interrupt service routines. Data Register Area values segment data stored data memory bank (13H page). Register locations this area that used store data assigned general-purpose use.
KS57C5616/P5616
ADDRESS SPACES
Table 2-2. Data Memory Organization Addressing Addresses 000H-01FH 020H-0FFH 100H-1FFH F80H-FFFH Register Areas Working registers Stack general-purpose registers General-purpose registers (the first19 pages): display data memory (the 20th page) I/O-mapped hardware registers Bank Value Value
PROGRAMMING Clearing Data Memory Banks Clear banks data memory area: RAMCLR BITS INCS PACL0 INCS DECS PACL1 HL,#10H A,#0H @HL,A RMCL0 EA,#13H PASR,EA A,#0H @HL,A PACL0 EA,PASR PACL1 PACL2 PASR,EA PACL0 Clear (010H-0FFH)
RMCL0
Clear page memory bank
PALL2
ADDRESS SPACES
KS57C5616/P5616
WORKING REGISTERS Working registers, mapped address 000H-01FH data memory bank used temporarily store intermediate results during program execution, well pointer values used indirect addressing. Unused registers used general-purpose memory. Working register data manipulated 1-bit units, 4-bit units using paired registers, 8-bit units.
000H 001H 002H 003H 004H 005H Data Memory Bank 006H 007H 008H 00FH 010H 017H 018H 01FH Register Bank Register Bank Register Bank Working Register Bank
Figure 2-4. Working Register
2-10
KS57C5616/P5616
ADDRESS SPACES
Working Register Banks addressing purposes, working register area divided into four register banks bank bank bank bank these banks selected working register bank register bank selection instruction (SRB setting status register bank enable flag (ERB). Generally, working register bank used main program, banks interrupt service routines. Following this convention helps prevent possible data corruption during program execution contention register bank addressing. Table 2-3. Working Register Organization Addressing Setting Settings NOTE: means don't care.
Selected Register Bank Always bank Bank Bank Bank Bank
Paired Working Registers Each register banks subdivided into eight 4-bit registers. These registers, named either manipulated individually using 4-bit instructions, together register pairs 8-bit data manipulation. names 8-bit register pairs each register bank Registers always become lower nibble when registers addressed 8-bit pairs. This makes total eight 4-bit registers four 8-bit double registers each four working register banks.
(MSB)
(LSB)
(MSB)
(LSB)
Figure 2-5. Register Pair Configuration
ADDRESS SPACES
KS57C5616/P5616
Special-Purpose Working Registers Register used 4-bit accumulator double register 8-bit accumulator. carry flag also used 1-bit accumulator. 8-bit double registers used data pointers indirect addressing. When register serves data pointer, instructions LDI, LDD, XCHI, XCHD make very efficient working registers program loop counters letting transfer value register increment decrement using single instruction.
1-Bit Accumulator
4-Bit Accumulator
8-Bit Accumulator
Figure 2-6. 1-Bit, 4-Bit, 8-Bit Accumulator Recommendation Multiple Interrupt Processing more than four interrupts being processed time, avoid possible loss working register data using PUSH instruction save register contents stack before service routines executed same register bank. When routines have executed successfully, restore register contents from stack working memory using instruction.
2-12
KS57C5616/P5616
ADDRESS SPACES
PROGRAMMING Selecting Working Register Area
following examples show correct programming method selecting working register area: When "0": VENT2 INT0 PUSH PUSH PUSH PUSH PUSH INCS IRET 1,0,INT0 EA,#00H 80H,EA HL,#40H WX,EA YZ,EA Jump INT0 address PUSH current SMB, Instruction does execute because PUSH register contents stack PUSH register contents stack PUSH register contents stack PUSH register contents stack
register contents from stack register contents from stack register contents from stack register contents from stack current SMB,
instructions execute alternately with PUSH instructions. instruction used interrupt service routine, PUSH instruction must used store restore current values, shown Example below. When "1": VENT2 INT0 PUSH INCS IRET 1,1,INT0 EA,#00H 80H,EA HL,#40H WX,EA YZ,EA Jump INT0 address Store current SMB, Select register bank because
Restore SMB,
2-13
ADDRESS SPACES
KS57C5616/P5616
STACK OPERATIONS
STACK POINTER (SP) stack pointer (SP) 8-bit register that stores address used access stack, area data memory aside temporary storage data addresses. read written 8-bit control instructions. When addressing must always remain cleared logic zero. F80H F81H
There basic stack operations: writing stack (push), reading from stack (pop). push decrements increments that always points address last data written stack. program counter contents program status word stored stack area prior execution CALL PUSH instruction, during interrupt service routines. Stack operation LIFO (Last In-First Out) type. stack area located general-purpose data memory bank During interrupt subroutine, value saved stack area. When routine completed, stack pointer referenced restore PSW, next instruction executed. address stack registers bank (addresses 000H-0FFH) regardless current value enable memory bank (EMB) flag select memory bank (SMB) flag. Although general-purpose register areas used stack operations, careful avoid data loss simultaneous same register(s). Since reset value stack pointer defined firmware, recommend that initialize stack pointer program code location 00H. This sets first register stack area 0FFH. NOTE subroutine call occupies nibbles stack; interrupt requires six. When subroutine nesting interrupt routines used continuously, stack area should accordance with maximum number subroutine levels. this, estimate number nibbles that will used subroutines interrupts stack area correspondingly.
PROGRAMMING Initializing Stack Pointer
initialize stack pointer (SP): When "1": When "0": EA,#00H SP,EA Memory addressing area (00H-7FH, F80H-FFFH) EA,#00H SP,EA Select memory bank always cleared Stack area initial address (0FFH) (SP)
2-14
KS57C5616/P5616
ADDRESS SPACES
PUSH OPERATIONS Three kinds push operations reference stack pointer (SP) write data from source register stack: PUSH instructions, CALL instructions, interrupts. each case, decremented number determined type push operation then points next available stack location. PUSH Instructions PUSH instruction references write 4-bit data nibbles stack. 4-bit stack addresses referenced stack pointer: upper register value another lower register. After PUSH executed, decremented points next available stack location. CALL Instructions When subroutine call issued, CALL instruction references write PC's contents 4-bit stack locations. Current values enable memory bank (EMB) flag enable register bank (ERB) flag also pushed stack. Since 4-bit stack locations used CALL, nest subroutine calls number levels permitted stack. Interrupt Routines interrupt routine references push contents program status word (PSW) stack. 4-bit stack locations used store this data. After interrupt executed, decremented points next available stack location. During interrupt sequence, subroutines nested number levels which permitted stack area.
PUSH (After PUSH,
CALL, LCALL (After CALL LCALL, PC11 PC14 PC12
Interrupt (When acknowledged, PC11 PC14 PC12
Lower Register Upper Register
Figure 2-7. Push-Type Stack Operations
2-15
ADDRESS SPACES
KS57C5616/P5616
OPERATIONS each push operation there corresponding operation write data from stack back source register registers: PUSH instruction instruction; CALL, instruction SRET; interrupts, instruction IRET. When operation occurs, incremented number determined type operation points next free stack location. Instructions instruction references write data stored 4-bit stack locations back register pairs register. value lower 4-bit register popped first, followed value upper 4-bit register. After executed, incremented points next free stack location. SRET Instructions subroutine call signaled return instruction, SRET. SRET uses reference 4-bit stack locations used CALL write this data back EMB, ERB. After SRET executed, incremented points next free stack location. IRET Instructions interrupt sequence signaled instruction IRET. IRET references locate 4-bit stack addresses used interrupt write this data back PSW. After IRET executed, incremented points next free stack location.
SRET PC11 PC14 PC12
IRET
Lower Register Upper Register
PC11 PC14 PC12
Figure 2-8. Pop-Type Stack Operations
2-16
KS57C5616/P5616
ADDRESS SPACES
SEQUENTIAL CARRIER (BSC)
sequential carrier (BSC) 16-bit general register that manipulated using 8-bit control instructions. RESET clears values logic zero. Using BSC, specify sequential addresses locations using 1-bit indirect addressing (memb.@L). (Bit addressing independent current value.) this way, programs process 16-bit data moving location sequentially then incrementing decrementing value register. data also manipulated using direct addressing. 8-bit manipulations, 4-bit register names BSC0 BSC2 must specified upper lower bits manipulated separately. values register BSC0.@L, address location assignment FC0H.0. register content BSC0.@L, address location assignment FC3H.3. Table 2-4. Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H BSC0.3 BSC1.3 BSC2.3 BSC3.3 BSC0.2 BSC1.2 BSC2.2 BSC3.2 BSC0.1 BSC1.1 BSC2.1 BSC3.1 BSC0.0 BSC1.0 BSC2.0 BSC3.0
PROGRAMMING Using Register Output 16-Bit Data
sequential carrier (BSC) register output 16-bit data (5937H) P3.0 pin: BITS INCS EA,#37H BSC0,EA EA,#59H BSC2,EA L,#0H C,BSC0.@L P3.0,C
BSC0 BSC1 BSC2 BSC3 P3.0
2-17
ADDRESS SPACES
KS57C5616/P5616
PROGRAM COUNTER (PC)
14-bit program counter (PC) stores addresses instruction fetches during program execution. Whenever reset operation interrupt occurs, bits PC13 through vector address. Usually, incremented number bytes instruction being fetched. exception 1-byte instruction which used reference instructions stored ROM.
PROGRAM STATUS WORD (PSW)
program status word (PSW) 8-bit word that defines system status program execution status which permits interrupted process resume operation after interrupt request been serviced. values mapped follows: (MSB) FB0H FB1H (LSB)
manipulated 1-bit 4-bit read/write 8-bit read instructions, depending specific bits being addressed. addressed during program execution regardless current value enable memory bank (EMB) flag. Part saved stack prior execution subroutine call hardware interrupt. After interrupt been processed, values popped from stack back address. When RESET generated, values according RESET vector address, carry flag left undefined current value retained). bits IS0, IS1, SC0, SC1, cleared logical zero. Table 2-5. Program Status Word Descriptions Identifier IS1, SC2, SC1, Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Addressing Read/Write
2-18
KS57C5616/P5616
ADDRESS SPACES
INTERRUPT STATUS FLAGS (IS0, IS1) bits contain current interrupt execution status values. manipulate flags directly using 1-bit control instructions. manipulating interrupt status flags conjunction with interrupt priority register (IPR), process multiple interrupts anticipating next interrupt execution sequence. interrupt priority control circuit determines settings order control multiple interrupt processing. When both interrupt status flags "0", interrupts allowed. priority with which interrupts processed then determined IPR. When interrupt occurs, pushed stack part automatically incremented next higher priority level. Then, when interrupt service routine ends with IRET instruction, values restored PSW. Table shows effects flag settings. Table 2-6. Interrupt Status Flag Settings Value Value Status Currently Executing Process Effect Settings Interrupt Request Control interrupt requests serviced. Only high-priority interrupt(s) determined interrupt priority register (IPR) serviced. more interrupt requests serviced. applicable; these settings undefined.
Since interrupt status flags addressed write instructions, programs exert direct control over interrupt processing status. Before interrupt status flags addressed, however, must first execute instruction inhibit additional interrupt routines. When manipulation been completed, execute instruction re-enable interrupt processing.
PROGRAMMING Setting Flags Interrupt Processing
following instruction sequence shows flags control interrupt processing: INTB BITR BITS Disable interrupt Allow interrupts according priority level Enable interrupt
2-19
ADDRESS SPACES
KS57C5616/P5616
FLAG (EMB) flag used allocate specific address locations modifying upper bits 12-bit data memory addresses. this way, controls addressing mode data memory banks When flag "0", data memory address space restricted 0F80H-0FFFH data memory bank addresses 000H-07FH bank regardless register contents. When flag "1", addressing area data memory expanded data memory space accessed using appropriate PASR value.
PROGRAMMING Using Flag Select Memory Banks
flag settings memory bank selection: When PASR "0": A,#9H 90H,A 34H,A 90H,A 34H,A 20H,A 90H,A Non-essential instruction since (F90H) bank selected (034H) bank selected Non-essential instruction since (F90H) bank selected (034H) bank selected Non-essential instruction, since (020H) bank selected (F90H) bank selected
When PASR "0": A,#9H 90H,A 34H,A 90H,A 34H,A 20H,A 90H,A Select memory bank (190H) page bank selected (134H) page bank selected Select memory bank (090H) bank selected (034H) bank selected Select memory bank Program error, assembler does detect (F90H) bank selected
2-20
KS57C5616/P5616
ADDRESS SPACES
FLAG (ERB) 1-bit register bank enable flag (ERB) determines range addressable working register area. When flag "1", working register area from register banks selected according register bank selection register (SRB). When flag "0", register bank selected working register area, regardless current value register bank selection register (SRB). When internal RESET generated, program memory address 0000H written flag. This automatically initializes flag. When vectored interrupt generated, respective address table program memory written flag, setting correct flag status before interrupt service routine executed. During interrupt routine, value automatically pushed stack area along with other bits. Afterwards, popped back FB0H.0 location. initial flag settings each vectored interrupt defined using VENTn instructions.
PROGRAMMING Using Flag Select Register Banks
flag settings register bank selection: When "0": When "1": EA,#34H HL,EA YZ,EA WX,EA Register bank selected Bank #34H Bank Bank Register bank selected Bank BANK2 Register bank selected Bank Bank EA,#34H HL,EA YZ,EA WX,EA Register bank selected (since "0", configured bank Bank #34H Bank Register bank selected Bank Register bank selected Bank
ADDRESS SPACES
KS57C5616/P5616
SKIP CONDITION FLAGS (SC2, SC1, SC0) skip condition flags SC2, SC1, indicate current program skip conditions reset automatically during program execution. Skip condition flags only addressed 8-bit read instructions. Direct manipulation SC2, SC1, bits allowed. CARRY FLAG carry flag used save result overflow borrow when executing arithmetic instructions involving carry (ADC, SBC). carry flag also used 1-bit accumulator performing Boolean operations involving bit-addressed data memory. overflow borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), carry flag "1". Otherwise, value "0". When RESET occurs, current value carry flag retained during power-down mode, when normal operating mode resumes, value undefined. carry flag directly manipulated predefined 1-bit read/write instructions, independent other bits PSW. Only instructions, instructions listed Table 2-7, affect carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation BTST transfer Boolean manipulation (operand)
(1),C
Instructions
Carry Flag Manipulation carry flag "1". Clear carry flag (reset carry flag). Invert carry flag value (complement carry flag). Test carry skip "1". Load carry flag value specified bit. Load contents specified carry flag. specified with contents carry flag save result carry flag. specified with contents carry flag save result carry flag. specified with contents carry flag save result carry flag. Save carry flag stack with other bits. Restore carry flag from stack with other bits.
C,(operand)
BAND C,(operand)
C,(operand) BXOR C,(operand) Interrupt routine Return from interrupt INTn IRET
NOTES: operand three addressing formats: mema.a, memb.@L, DA.b. "INTn" refers specific interrupt being executed instruction.
2-22
KS57C5616/P5616
ADDRESS SPACES
PROGRAMMING Using Carry Flag 1-Bit Accumulator
carry flag logic one: #0C3H #0AAH #0C3H #0AAH #1H,
EA,#0C3H HL,#0AAH EA,HL
Logical-AND address with P3.3 output result P5.0: BAND H,#3H C,@H 0FH.3 C,P3.3 P5.0,C upper four bits address register value P3.3 Output result from carry flag P5.0
2-23
ADDRESS SPACES
KS57C5616/P5616
NOTES
2-24
KS57C5616/P5616
ADDRESSING MODES
ADDRESSING MODES
enable memory bank flag, EMB, controls addressing modes data memory. When flag logic one, address entire area; when flag cleared logic zero, addressable area restricted specific locations. flag works connection with select memory bank instruction, SMBn. will recall that SMBn instruction used select bank setting always contained upper four bits 12-bit address. this reason, both addressing modes (EMB "1") apply specifically memory bank indicated instruction, restrictions addressable area within banks Direct indirect 1-bit, 4-bit, 8-bit addressing methods used. Several locations addressable times, regardless current flag setting. Here guidelines keep mind regarding data memory addressing: When address peripheral hardware locations bank mnemonic memory-mapped hardware component used operand place actual address location. Always even-numbered address operand 8-bit direct indirect addressing. With direct addressing, address instruction operand; with indirect addressing, instruction specifies register which contains operand's address.
ADDRESSING MODES
KS57C5616/P5616
Areas 000H 01FH 020H 07FH 080H
Addressing Mode
DA.b
@H+DA.b
mema.b
memb.@L
Working Registers
Bank (General Registers Stack)
0FFH 100H
Bank (General Registers Display Registers)
1FFH F80H FB0H FBFH FC0H
Bank (Peripheral Hardware Registers)
FF0H FFFH NOTES: means don't care. Blank columns indicate areas that addressable, given addressing method, enable memory bank (EMB) flag setting shown column headers. Bank consists gerneral registers (0H-12H pages), Display registers (13H page)
Figure 3-1. Address Structure
KS57C5616/P5616
ADDRESSING MODES
INITIALIZATION VALUES flag bits automatically values RESET vector address interrupt vector address. When RESET generated internally, program memory address 0000H written flag, initializing automatically. When vectored interrupt generated, respective vector address table written EMB. This automatically sets flag status interrupt service routine. When interrupt serviced, value automatically saved stack then restored when interrupt routine completed. beginning program, initial flag values each vectored interrupt must using VENT instruction. reset manipulation instructions (BITS, BITR) despite current setting.
PROGRAMMING Initializing Flags
following assembly instructions show initialize flag settings: VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 BITR 0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INT1 0,1,INTS 0,1,INTT0 0,1,INTT1 0,1,INTK address assignment branch RESET branch INTB branch INT0 branch INT1 branch INTS branch INTT0 branch INTT1 branch INTK
RESET
ADDRESSING MODES
KS57C5616/P5616
ENABLE MEMORY BANK SETTINGS When enable memory bank flag logic one, address data memory bank specified select memory bank (SMB) value using 8-bit instructions. both direct indirect addressing modes. addressable areas when follows: When enable memory bank flag logic zero, addressable area defined independently value, restricted specific locations depending whether direct indirect address mode used. "0", addressable area restricted locations 000H-07FH bank locations F80H-FFFH bank direct addressing. indirect addressing, only locations 000H-0FFH bank addressable, regardless value. address peripheral hardware register (bank using indirect addressing, flag must first value "15". When RESET occurs, flag value contained address 0000H. EMB-Independent Addressing time, several areas data memory addressed independent current status flag. These exceptions described Table 3-1. 000H-0FFH 100H-1FFH F80H-FFFH
Table 3-1. Addressing Affected Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using register pairs; 8-bit indirect addressing using 1-bit direct addressing 1-bit indirect addressing using register Affected Hardware applicable PUSH PSW, SCMOD, IEx, IRQx, BSC, BITS BITR Program Examples A,@WX
FB0H-FBFH FF0H-FFFH FC0H-FFFH
BTST FC3H.@L BAND C,P3.@L
KS57C5616/P5616
ADDRESSING MODES
SELECT BANK REGISTER (SB) select bank register (SB) used assign memory bank register bank. 8-bit register consists 4-bit select register bank register (SRB) 4-bit select memory bank register (SMB), shown Figure 3-2. During interrupts subroutine calls, register contents saved stack 8-bit units PUSH instruction. later restore value using instruction.
(F83H) Register
(F82H)
Figure 3-2. Values Register SELECT REGISTER BANK (SRB) INSTRUCTION select register bank (SRB) value specifies which register bank used working register bank. value "SRB instruction, where four register banks selected combination flag status value that using "SRB instruction. current value retained until another register requested program software. PUSH instructions used save restore contents during interrupts subroutine calls. RESET clears 4-bit value logic zero. SELECT MEMORY BANK (SMB) INSTRUCTION select three available data memory banks, must execute instruction specifying number memory bank want 15). example, instruction "SMB selects bank "SMB selects bank (And remember enable selected memory bank making appropriate flag setting. upper four bits 12-bit data memory address stored register. value specified software RESET does occur) current value retained. RESET clears 4-bit value logic zero. PUSH instructions save restore contents register from stack area during interrupts subroutine calls. BANK1 PAGE SELECTION REGISTER (PASR) PASR 8-bit register selecting page bank1, mapped address, F8AH-F8BH. should read written 8-bit control instruction only bits should "0". PASR retains existing value long change required, RESET value Therefore, when returns bank1 from other bank (bank0 bank15) without changing contents PASR, previously specified page selected. PASR must changed interrupt service routine because value cannot recovered original value when routine finished.
ADDRESSING MODES
KS57C5616/P5616
DIRECT INDIRECT ADDRESSING
1-bit, 4-bit, 8-bit data stored data memory locations addressed directly using specific register address instruction operand. Indirect addressing specifies memory location that contains required direct address. KS57 instruction supports 1-bit, 4-bit, 8-bit indirect addressing. 8-bit indirect addressing, even-numbered address must always used instruction operand. 1-BIT ADDRESSING Table 3-2. 1-Bit Direct Indirect Addressing Operand Notation DA.b Addressing Mode Description Direct: indicated address (DA), memory bank selection, specified number (b). Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 1-bit addressable peripherals (SMB IS0, IS1, EMB, ERB, IEx, IRQx, Pn.m BSCn.x Pn.m
mema.b Direct: indicated addressable area (mema) number (b). Indirect: lower bits register indicated upper bits area (memb) upper bits register Indirect: indicated lower four bits address (DA), memory bank selection, register identifier.
000H-FFFH FB0H-FBFH FF0H-FFFH
Bank
memb.@L
FC0H-FFFH
Bank
DA.b
000H-0FFH
Bank
000H-FFFH
1-bit addressable peripherals (SMB
NOTE: means don't care.
KS57C5616/P5616
ADDRESSING MODES
PROGRAMMING 1-Bit Addressing Modes
1-Bit Direct Addressing "0": AFLAG BFLAG CFLAG BITS BITS BTST BITS BITS "1": AFLAG BFLAG CFLAG BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 AFLAG BFLAG CFLAG BFLAG P3.0 34H.3 85H.3 0BAH.0 AFLAG BFLAG CFLAG BFLAG P3.0
34H.3 F85H.3 FBAH.0 skip Else FBAH.0 F85H.3 (BMOD.3) FF3H.0 (P3.0)
34H.3 85H.3 0BAH.0 skip Else 0BAH.0 085H.3 FF3H.0 (P3.0)
ADDRESSING MODES
KS57C5616/P5616
PROGRAMMING 1-Bit Addressing Modes (Continued)
1-Bit Indirect Addressing "0": AFLAG BFLAG CFLAG BTSTZ BITS "1": AFLAG BFLAG CFLAG BTSTZ BITS 34H.3 85H.3 0BAH.0 H,#0BH @H+CFLAG CFLAG 34H.3 85H.3 0BAH.0 H,#0BH @H+CFLAG CFLAG
#0BH 0BAH.0 0BAH.0 skip Else 0BAH.0 FBAH.0
#0BH 0BAH.0 0BAH.0 skip Else 0BAH.0 0BAH.0
KS57C5616/P5616
ADDRESSING MODES
4-BIT ADDRESSING Table 3-3. 4-Bit Direct Indirect Addressing Operand Notation Addressing Mode Description Direct: 4-bit address indicated address (DA) memory bank selection Indirect: 4-bit address indicated memory bank selection register Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 4-bit addressable peripherals (SMB
000H-FFFH 000H-0FFH
Bank
000H-FFFH
1,15
Indirect: 4-bit address indicated register Indirect: 4-bit address indicated register
000H-0FFH 000H-0FFH
Bank Bank
4-bit addressable peripherals (SMB
NOTE: means don't care.
PROGRAMMING 4-Bit Addressing Modes
4-Bit Direct Addressing "0": ADATA BDATA "1": ADATA BDATA A,P3 ADATA,A BDATA,A A,P3 ADATA,A BDATA,A
Non-essential instruction, since (P3) Non-essential instruction, since (046H) (F8EH (LCON))
(P3) (046H) (08EH)
ADDRESSING MODES
KS57C5616/P5616
PROGRAMMING 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing (Example "0", compare bank locations 040H-046H with bank locations 060H-066H: ADATA BDATA COMP CPSE SRET DECS HL,#BDATA WX,#ADATA A,@WL A,@HL COMP
Non-essential instruction, since bank (040H-046H) bank (060H-066H) skip
"1", compare bank locations 040H-046H bank locations 160H-166H: ADATA BDATA COMP CPSE SRET DECS HL,#BDATA WX,#ADATA A,@WL A,@HL COMP
bank (040H-046H) bank (160H-166H) skip
3-10
KS57C5616/P5616
ADDRESSING MODES
PROGRAMMING 4-Bit Addressing Modes (Concluded)
4-Bit Indirect Addressing (Example "0", exchange bank locations 040H-046H with bank locations 060H-066H: ADATA BDATA TRANS XCHD HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
Non-essential instruction, since bank (040H-046H) Bank (060H-066H)
"1", exchange bank locations 040H-046H bank locations 160H-166H: ADATA BDATA TRANS XCHD HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
bank (040H-046H) Bank (160H-166H)
ADDRESSING MODES
KS57C5616/P5616
8-BIT ADDRESSING Table 3-4. 8-Bit Direct Indirect Addressing Instruction Notation Addressing Mode Description Direct: 8-bit address indicated address even number) memory bank selection Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 8-bit addressable peripherals (SMB
Indirect: 8-bit address indicated memory bank selection register (the 4-bit register value must even number)
000H-FFFH 000H-0FFH
1,15 Bank
000H-FFFH
1,15
8-bit addressable peripherals (SMB
PROGRAMMING 8-Bit Addressing Modes
8-Bit Direct Addressing "0": ADATA BDATA "1": ADATA BDATA EA,P4 ADATA,EA BDATA,EA EA,P4 ADATA,EA BDATA,EA
Non-essential instruction, since (P5), (P4) (046H) (047H) (F8EH) (F8FH)
(P5), (P4) (046H) (047H) (08EH) (08FH)
3-12
KS57C5616/P5616
ADDRESSING MODES
PROGRAMMING 8-Bit Addressing Modes (Continued)
8-Bit Indirect Addressing "0": ADATA "1": ADATA HL,#ADATA EA,@HL HL,#ADATA EA,@HL Non-essential instruction, since (046H), (047H)
(146H), (147H)
3-13
ADDRESSING MODES
KS57C5616/P5616
NOTES
3-14
KS57C5616/P5616
MEMORY
MEMORY
support program control peripheral hardware, addresses peripherals memory-mapped bank RAM. Memory mapping lets mnemonic operand instruction place specific memory location. Access bank controlled select memory bank (SMB) instruction enable memory bank flag (EMB) setting. flag "0", bank addressed using direct addressing, regardless current value. 1-bit direct indirect addressing used specific locations bank regardless current value. HARDWARE REGISTERS Table contains detailed information about mapping peripheral hardware bank (register locations F80H-FFFH). quick-reference source when writing application programs. gives following information: Register address Register name (mnemonic program addressing) values (both addressable non-manipulable) Read-only, write-only, read write addressability 1-bit, 4-bit, 8-bit data manipulation characteristics
MEMORY
KS57C5616/P5616
Table 4-1. Memory Bank Memory Bank Address F80H F81H Locations F84H-F82H mapped F85H F86H F87H F88H F89H F8AH F8BH F8CH F8DH F8EH F8FH F90H F91H F92H F94H F95H F96H F97H F98H F99H F9AH WDFLAG TMOD1A TMOD1B TCNT1A TCNT1B WDTCF WDMOD Watchdog timer mode Register TREF0 Timer/Counter Reference Register TCNT0 TMOD0 LCON LMOD PASR WMOD TOE1 TOE0 TOL2 BMOD BCNT Register Addressing Mode 1-Bit 4-Bit 8-Bit
Location F93H mapped Timer/Counter Counter Register
Locations F9FH-F9BH mapped FA0H FA1H FA2H FA3H FA4H FA5H FA6H FA7H Timer/Counter Counter Register
Timer/Counter Counter Register
KS57C5616/P5616
MEMORY
Table 4-1. Memory Bank (Continued) Memory Bank Address FA8H FA9H FAAH FABH FACH FADH FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H FB8H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H FCEH FD0H BSC0 BSC1 BSC2 BSC3 Locations FCDH-FC4H mapped P7MOD CLMOD Location FCFH mapped Location FD1H mapped PCON IMOD0 IMOD1 IMODK SCMOD DTMR
Addressing Mode 1-Bit 4-Bit 8-Bit
Register TREF1A TREF1B
Timer/Counter Reference Register Timer/Counter Reference Register IRQ4 IRQK IRQT2 IRQ1 IET1 IET0 IRQB IRQW IRQT1 IRQT0 IRQS IRQ0 IRQ2
Locations FAFH-FAEH mapped
IET2
Power Control Register
Location FB9H mapped
MEMORY
KS57C5616/P5616
Table 4-1. Memory Bank (Continued) Memory Bank Address FD2H FD3H FD4H FD6H FD7H FD8H FD9H FDAH FDCH FDDH FDEH FE0H FE1H FE4H FE5H FE6H FE7H FE8H FE9H FEAH FEBH FECH FEDH FEEH FEFH FF0H FF1H FF2H FF3H PMG5 PMG4 PMG3 PMG2 PMG1 PM0.3 PM3.3 PM10.3 PM4.3 PM5.3 PM6.3 PM7.3 PM8.3 PM9.3 PM0.2 PM2.2 PM3.2 PM10.2 PM4.2 PM5.2 PM6.2 PM7.2 PM8.2 PM9.2 PM0.1 PM2.1 PM3.1 PM10.1 PM4.1 PM5.1 PM6.1 PM7.1 PM8.1 PM9.1 PM0.0 PM2.0 PM3.0 PM10.0 PM4.0 PM5.0 PM6.0 PM7.0 PM8.0 PM9.0 SBUF PUMOD2 SMOD PNE2 VLC1R IMOD2 PUMOD1 CMPREG Location FD5H mapped PNE1 PUR3 PUR7 PUR2 PUR6 PUR10 PUR1 PUR5 PUR9 VLC1F PUR0 PUR4 PUR8 Register CMOD Addressing Mode 1-Bit 4-Bit 8-Bit
Location FDBH mapped
Location FDFH mapped
Locations FE3H-FE2H mapped
KS57C5616/P5616
MEMORY
Table 4-1. Memory Bank (Concluded) Memory Bank Address FF4H FF5H FF6H FF7H FF8H FF9H FFAH Register .3/.7 .3/.7 .3/.7 .2/.6 .2/.6 .2/.6 .1/.5 .1/.5 .1/.5 .0/.4 .0/.4 .0/.4
Addressing Mode 1-Bit 4-Bit 8-Bit
Locations FFFH-FFBH mapped
NOTES: WMOD register read-only. TOL2 flag read-only. F9AH.0,F9AH.1, F9AH.2 fixed "0". carry flag read written specific manipulation instructions only. P8.0-P8.1 used push-pull output.
REGISTER DESCRIPTIONS this section, register descriptions presented consistent format familiarize with memory-mapped locations bank RAM. Figure describes features register description format. Register descriptions arranged alphabetical order. Programmers this section quick-reference source when writing application programs. Counter registers, buffer registers, reference registers, well stack pointer port latches, included these descriptions. More detailed information about these registers used included Part this manual, "Hardware Descriptions", context corresponding peripheral hardware module descriptions.
MEMORY
KS57C5616/P5616
Register used addressing Register Register name
Name individual related bits Associated hardware module Register location bank
CLMOD Clock Output Mode Control Register
Identifier
RESET Value
FD0H
Read/Write Addressing CLMOD1.3
Enable/Disable Clock Output Control Disable clock output (CLO1, CLO2) Enable clock output (CLO1, CLO2)
CLMOD1.2
Always logic
CLMOD1.1
Clock Source Frequency Selection Control Bits Select clock souce Select main system clock fx/8 (524 4.19 MHz) Select main system clock fx/16 (262 4.19 MHz) Select main system clock fx/64 (65.5 4.19 MHz)
Read-only Write-only Read/write Type addressing that must used address (1-bit, 4-bit, 8-bit)
value immediately following RESET
number order
Description effect specific settings
identifier used addressing
Figure 4-1. Register Description Format
KS57C5616/P5616
MEMORY
BMOD Basic Timer Mode Register
Identifier
RESET Value
F85H
Read/Write Addressing BMOD.3
Basic Timer Restart Restart basic timer, then clear IRQB flag, BCNT BMOD.3 logic zero
BMOD.2-.0
Input Clock Frequency Signal Stabilization Interval Control Bits Input clock frequency: Interrupt interval time: Input clock frequency: Interrupt interval time: Input clock frequency: Interrupt interval time: Input clock frequency: Interrupt interval time: fxx/212 (1.02 kHz) 220/fxx (250 fxx/29 (8.18 kHz) 217/fxx (31.3 fxx/27 (32.7 kHz) 215/fxx (7.82 fxx/25 (131 kHz) 213/fxx (1.95
NOTES: Interrupt interval time time required IRQB periodically. When RESET occurs, oscillation stabilization time 31.3 (217/fxx) 4.19 MHz. "fxx" system clock rate given clock frequency 4.19 MHz.
MEMORY
KS57C5616/P5616
CLMOD Clock Output Mode Register
Identifier
RESET Value
FD0H
Read/Write Addressing CLMOD.3
Enable/Disable Clock Output Control Disable clock output Enable clock output
CLMOD.2
Always logic zero
CLMOD.1-.0
Clock Source Frequency Selection Control Bits Select clock source fxx/4, fxx/8, fxx/64 (1.05 MHz, kHz, 65.5 kHz) Select system clock fxx/8 (524 kHz) Select system clock fxx/16 (262 kHz) Select system clock fxx/64 (65.5 kHz)
NOTE: "fxx" system clock, given clock frequency 4.19 MHz.
KS57C5616/P5616
MEMORY
CMOD Comparator Mode Register
Identifier
RESET Value
COMPARATOR
FD3H,FD2H
Read/Write Addressing
Comparator Enable/Disable Comparator operation disable Comparator operation enable
Conversion Timer Control 27/fx, 244.4 4.19 24/fx, 30.5 4.19
External/Internal Reference Selection Internal reference, CIN0-3; analog input External reference CIN3, CIN0-2; analog input
Always logic zero
.3-.0
Reference Voltage Selection Bits Selected VREF (N+0.5)
MEMORY
KS57C5616/P5616
DTMR DTMF Mode Register
Identifier
RESET
DTMF
FADH,FACH
Value
Read/Write Addressing DTMR.7-.4
DTMR Values Keyboard Inputs Function
Function Function Function
DTMR.3
Always logic zero
DTMR.2-.
Tone Selection Bits Dual-tone enable Dual-tone enable (alternate setting) Single-column tone enable Single-low tone enable
DTMR.0
DTMF Operation Enable/Disable Disable DTMF operation Enable DTMF operation
4-10
KS57C5616/P5616
MEMORY
IE0, IRQ0, INT0, Interrupt Enable/Request Flags
Identifier
RESET Value
FBEH
IRQ1
IRQ0
Read/Write Addressing
INT1 Interrupt Enable Flag Disable interrupt requests INT1 Enable interrupt requests INT1
INT1 Interrupt Request Flag Generate INT1 interrupt (This cleared hardware when rising falling edge detected INT1 pin.)
INT0 Interrupt Enable Flag Disable interrupt requests INT0 Enable interrupt requests INT0
IRQ0
INT0 Interrupt Request Flag Generate INT0 interrupt (This cleared automatically hardware when rising falling edge detected INT0 pin.)
MEMORY
KS57C5616/P5616
IE2, IRQ2 INT2 Interrupt Enable/Request Flags
Identifier
RESET Value
FBFH
Bits
IRQ2
Read/Write Addressing .3-.2
Always logic zero
INT2 Interrupt Enable Flag Disable INT2 interrupt requests INT2 Enable INT2 interrupt requests INT2
IRQ2
INT2 Interrupt Request Flag Generate INT2 quasi-interrupt (This cleared automatically hardware when rising falling edge detected INT2. Since INT2 quasi-interrupt, IRQ2 flag must cleared software.)
4-12
KS57C5616/P5616
MEMORY
IE4, IRQ4 INT4 Interrupt Enable/Request Flags IEB, IRQB INTB Interrupt Enable/Request Flags
Identifier
RESET Value
FB8H FB8H
IRQ4
IRQB
Read/Write Addressing
INT4 Interrupt Enable Flag Disable interrupt requests INT4 Enable interrupt requests INT4
IRQ4
INT4 Interrupt Request Flag Generate INT4 interrupt (This cleared automatically hardware when rising falling signal edge detected INT4 pin.)
INTB Interrupt Enable Flag Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag Generate INTB interrupt (This cleared automatically hardware when reference interval signal received from basic timer.)
4-13
MEMORY
KS57C5616/P5616
IES, IRQS INTS Interrupt Enable/Request Flags
Identifier
RESET Value
FBDH
Bits
IRQS
Read/Write Addressing .3-.2
Always logic zero
INTS Interrupt Enable Flag Disable INTS interrupt requests Enable INTS interrupt requests
IRQS
INTS Interrupt Request Flag Generate INTS interrupt (This cleared automatically hardware when serial data transfer completion signal received from serial interface.)
4-14
KS57C5616/P5616
MEMORY
IET0, IRQT0 INTT0 Interrupt Enable/Request Flags IET2, IRQT2 INTT1B Interrupt Enable/Request Flags
Identifier
RESET Value
FBCH FBCH
IET2
IRQT2
IET0
IRQT0
Read/Write Addressing IET2
INTT1B Interrupt Enable Flag Disable INTT1B interrupt requests Enable INTT1B interrupt requests
IRQT2
INTT1B Interrupt Request Flag Generate INTT1B interrupt (This cleared automatically hardware when contents TCNT1B TREF1B registers match.)
IET0
INTT0 Interrupt Enable Flag Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag Generate INTT0 interrupt (This cleared automatically hardware when contents TCNT0 TREF0 registers match.)
4-15
MEMORY
KS57C5616/P5616
IET1, IRQT1 INTT1A Interrupt Enable/Request Flags IEK, IRQK INTK Interrupt Enable/Request Flags
Identifier
RESET Value
FBBH FBBH
IRQK
IET1
IRQT1
Read/Write Addressing
INTK Interrupt Enable Flag Disable interrupt requests K0-K7 pins Enable interrupt requests K0-K7 pins
IRQK
INTK Interrupt Request Flag Generate INTK interrupt (This cleared automatically hardware when rising falling edge detected K0-K7 pins.)
INTT1/INTT1A Interrupt Enable Flag Disable INTT1/INTT1A interrupt requests Enable INTT1/INTT1A interrupt requests
IRQT
INTT1/INTT1A Interrupt Request Flag Generate INTT1/INTT1A interrupt (This cleared automatically hardware when contents TCNT1/TCNT1A TREF1/TREF1A registers match.)
4-16
KS57C5616/P5616
MEMORY
IEW, IRQW INTW Interrupt Enable/Request Flags
Identifier
RESET Value
FBAH
Bits
IRQW
Read/Write Addressing .3-.2
Always logic zero
INTW Interrupt Enable Flag Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag Generate INTW interrupt (This when timer interval 3.91 ms.)
NOTE: Since INTW quasi-interrupt, IRQW flag must cleared software.
4-17
MEMORY
KS57C5616/P5616
IMOD0 External Interrupt (INT0) Mode Register
Identifier
RESET Value
FB4H
Bits
Read/Write Addressing IMOD0.3-.2
Always logic zero
IMOD0.1-.0
External Interrupt Mode Control Bits Interrupt requests triggered rising signal edge Interrupt requests triggered falling signal edge Interrupt requests triggered both rising falling signal edges Interrupt request flag (IRQx) cannot logic
4-18
KS57C5616/P5616
MEMORY
IMOD1 External Interrupt (INT1) Mode Register
Identifier
RESET Value
FB5H
Bits
Read/Write Addressing IMOD1.3-.
Always logic zero
IMOD1.0
External Interrupt Edge Detection Control Rising edge detection Falling edge detection
4-19
MEMORY
KS57C5616/P5616
IMOD2 External Interrupt (INT2) Mode Register
Identifier
RESET Value
FDAH
Bits
Read/Write Addressing IMOD2.3-.
Always logic zero
IMOD2.0
External Interrupt Edge Detection Selection Interrupt request INT2 trigged rising edge Interrupt request INT2 trigged falling edge
4-20
KS57C5616/P5616
MEMORY
IMODK External Interrupt Mode Register
Identifier
RESET Value
FB6H
Read/Write Addressing IMODK.3
Always logic zero
IMODK.2
External Interrupt Edge Detection Selection Falling edge detection Rising edge detection
IMODK.1-.0
External Interrupt Mode Control Bits Disable interrupt Enable edge detection K0-K3 pins Enable edge detection K4-K7 pins Enable edge detection K0-K7 pins
NOTES: generate interrupt, selected pins must configured input mode. interrupt pins selected IMODK register configured output mode, only falling edge detected. generate interrupt, first, configure pull-up resistors external pull-down resistors. then, select edge detection pins setting IMODK register.
MEMORY
KS57C5616/P5616
Interrupt Priority Register
Identifier
RESET Value
FB2H
Read/Write Addressing
Interrupt Master Enable Disable interrupt processing Enable processing interrupt service requests
IPR.2-.0
Interrupt Priority Assignment Bits Process interrupt requests priority Process INTB INT4 interrupts only Process INT0 interrupts only Process INT1 interrupts only Process INTS interrupts only Process INTT0 INTT1B interrupts only Process INTT1 (INTT1A) interrupts only Process INTK interrupts only
4-22
KS57C5616/P5616
MEMORY
LCON Output Control Register
Identifier
RESET Value
F8FH,F8EH
Read/Write Addressing LCON.7
Control Always logic zero LCDCK LCDSY Disable/Enable Disable LCDCK LCDSY signal output Enable LCDCK LCDSY signal output Watch Timer (fw) Clock Selection fLCD 4,096 when fx/128 (32.768 4.19 MHz) fLCD 8,192 when fx/64 (65.563 4.19 MHz)
LCON.6
LCON.5
LCON.4
LCON.3-.2
Clock Frequency Selection Bits when duty: (256 Hz); when 1/12 duty: (512 Hz); when 1/16 duty: (512 when duty: (512 Hz); when 1/12 duty: (1024 Hz); when 1/16 duty: (1024 when duty: (1024 Hz); when 1/12 duty: (2048 Hz); when 1/16 duty: (2048 when duty: (2048 Hz); when 1/12 duty: (4096 Hz); when 1/16 duty: (4096
LCON.
Dividing Resistors Control Normal dividing resistors Diminish dividing resistor strengthen drive
LCON.0
Control
4-23
MEMORY
KS57C5616/P5616
LMOD Mode Register
Identifier
RESET Value
F8DH,F8CH
Read/Write Addressing LMOD.7-.5
Output Segment Configuration Bits Segments 40-43, 44-47, 48-51, 52-55, 56-59 Segments 40-43, 44-47, 48-51, 52-55; normal port Segments 40-43, 44-47, 48-51; normal port port Segments 40-43 44-47; normal port Segments 40-43; Normal ports Normal ports Segments 40-43, 44-47, 48-51, 56-59; normal port
NOTE: Segment pins that used normal should configured output mode function.
LMOD.4
Bias Selection Bias Bias
LMOD.3-.2
Duty Selection Bits When duty (COM0-COM7 select) When 1/12 duty (COM0-COM11 select) When 1/16 duty (COM0-COM15 select)
NOTE: When 1/16 duty selected, ports should configured output mode; when duty selected, ports used normal ports.
LMOD.1-.0
Display Mode Selection Bits dots dots Normal display
4-24
KS57C5616/P5616
MEMORY
P7MOD Port Mode Register
Identifier
RESET Value
FCEH
Read/Write Addressing P7MOD.3
P7.3 Analog/Digital Selection Configure P7.3 digital input Configure P7.3 analog input
P7MOD.2
P7.2 Analog/Digital Selection Configure P7.2 digital input Configure P7.2 analog input
P7MOD.
P7.1 Analog/Digital Selection Configure P7.1 digital input Configure P7.1 analog input
P7MOD.0
P7.0 Analog/Digital Selection Configure P7.0 digital input Configure P7.0 analog input
4-25
MEMORY
KS57C5616/P5616
PASR Page Selection Register
Identifier
RESET Value
F8BH, F8AH
Bits
Read/Write Addressing .7-.5
Always logic zero
.4-.0
Page Selection Register Bank1
page Bank1 page Bank
page display register Bank
NOTE: 00H-13H pages used KS57C5616.
4-26
KS57C5616/P5616
MEMORY
PCON Power Control Register
Identifier
RESET Value
FB3H
Read/Write Addressing PCON.3-.2
Operating Mode Control Bits Enable normal operating mode Initiate idle power-down mode Initiate stop power-down mode
PCON.1-.0
Clock Frequency Selection Bits SCMOD.0 "0", fx/64; SCMOD.0 "1", fxt/4 SCMOD.0 "0", fx/8; SCMOD.0 "1", fxt/4 SCMOD.0 "0", fx/4; SCMOD.0 "1", fxt/4
NOTE: "fx" main system clock; "fxt" subsystem clock.
4-27
MEMORY
KS57C5616/P5616
PMG1 Port Mode Flags (Group Ports
Identifier
RESET Value
PM0.3 PM0.2
FE7H, FE6H
PM0.0
PM2.2
PM2.1
PM2.0
PM0.1
Read/Write Addressing
Always logic zero
PM2.2
P2.2 Mode Selection Flag P2.2 input mode P2.2 output mode
PM2.
P2.1 Mode Selection Flag P2.1 input mode P2.1 output mode
PM2.0
P2.0 Mode Selection Flag P2.0 input mode P2.0 output mode
PM0.3
P0.3 Mode Selection Flag P0.3 input mode P0.3 output mode
PM0.2
P0.2 Mode Selection Flag P0.2 input mode P0.2 output mode
PM0.
P0.1 Mode Selection Flag P0.1 input mode P0.1 output mode
PM0.0
P0.0 Mode Selection Flag P0.0 input mode P0.0 output mode
4-28
KS57C5616/P5616
MEMORY
PMG2 Port Mode Flags (Group Ports
Identifier
RESET Value
PM3.3 PM3.2
FE9H, FE8H
PM3.0
PM10.3
PM10.2
PM10.1
PM10.0
PM3.1
Read/Write Addressing PM10.3
P10.3 Mode Selection Flag P10.3 input mode P10.3 output mode
PM10.2
P10.2 Mode Selection Flag P10.2 input mode P10.2 output mode
PM10.
P10.1 Mode Selection Flag P10.1 input mode P10.1 output mode
PM10.0
P10.0 Mode Selection Flag P10.0 input mode P10.0 output mode
PM3.3
P3.3 Mode Selection Flag P3.3 input mode P3.3 output mode
PM3.2
P3.2 Mode Selection Flag P3.2 input mode P3.2 output mode
PM3.
P3.1 Mode Selection Flag P3.1 input mode P3.1 output mode
PM3.0
P3.0 Mode Selection Flag P3.0 input mode P3.0 output mode
4-29
MEMORY
KS57C5616/P5616
PMG3 Port Mode Flags (Group Ports
Identifier
RESET Value
PM4.3 PM4.2
FEBH, FEAH
PM4.0
PM5.3
PM5.2
PM5.1
PM5.0
PM4.1
Read/Write Addressing PM5.3
P5.3 Mode Selection Flag P5.3 input mode P5.3 output mode
PM5.2
P5.2 Mode Selection Flag P5.2 input mode P5.2 output mode
PM5.
P5.1 Mode Selection Flag P5.1 input mode P5.1 output mode
PM5.0
P5.0 Mode Selection Flag P5.0 input mode P5.0 output mode
PM4.3
P4.3 Mode Selection Flag P4.3 input mode P4.3 output mode
PM4.2
P4.2 Mode Selection Flag P4.2 input mode P4.2 output mode
PM4.
P4.1 Mode Selection Flag P4.1 input mode P4.1 output mode
PM4.0
P4.0 Mode Selection Flag P4.0 input mode P4.0 output mode
4-30
KS57C5616/P5616
MEMORY
PMG4 Port Mode Flags (Group Ports
Identifier
RESET Value
PM6.3 PM6.2
FEDH, FECH
PM6.0
PM7.3
PM7.2
PM7.1
PM6.0
PM6.1
Read/Write Addressing PM7.3
P7.3 Mode Selection Flag P7.3 input mode P7.3 output mode
PM7.2
P7.2 Mode Selection Flag P7.2 input mode P7.2 output mode
PM7.
P7.1 Mode Selection Flag P7.1 input mode P7.1 output mode
PM7.0
P7.0 Mode Selection Flag P7.0 input mode P7.0 output mode
PM6.3
P6.3 Mode Selection Flag P6.3 input mode P6.3 output mode
PM6.2
P6.2 Mode Selection Flag P6.2 input mode P6.2 output mode
PM6.
P6.1 Mode Selection Flag P6.1 input mode P6.1 output mode
PM6.0
P6.0 Mode Selection Flag P6.0 input mode P6.0 output mode
MEMORY
KS57C5616/P5616
PMG5 Port Mode Flags (Group Ports
Identifier
RESET Value
PM8.3 PM8.2
FEFH, FEEH
PM8.0
PM9.3
PM9.2
PM9.1
PM9.0
PM8.1
Read/Write Addressing PM9.3
P9.3 Mode Selection Flag P9.3 input mode P9.3 output mode
PM9.2
P9.2 Mode Selection Flag P9.2 input mode P9.2 output mode
PM9.
P9.1 Mode Selection Flag P9.1 input mode P9.1 output mode
PM9.0
P9.0 Mode Selection Flag P9.0 input mode P9.0 output mode
PM8.3
P8.3 Mode Selection Flag P8.3 input mode P8.3 output mode
PM8.2
P8.2 Mode Selection Flag P8.2 input mode P8.2 output mode
PM8.
P8.1 Mode Selection Flag P8.1 input mode available
PM8.0
P8.0 Mode Selection Flag P8.0 input mode available
4-32
KS57C5616/P5616
MEMORY
PNE1 N-Channel Open-Drain Mode Register Identifier
RESET Value
FD7H, FD6H
Read/Write Addressing
Always logic
P2.2 N-Channel Open-Drain Configurable Configure P2.2 push-pull Configure P2.2 n-channel open-drain
P2.1 N-Channel Open-Drain Configurable Configure P2.1 push-pull Configure P2.1 n-channel open-drain
P2.0 N-Channel Open-Drain Configurable Configure P2.0 push-pull Configure P2.0 n-channel open-drain
P0.3 N-Channel Open-Drain Configurable Configure P0.3 push-pull Configure P0.3 n-channel open-drain
P0.2 N-Channel Open-Drain Configurable Configure P0.2 push-pull Configure P0.2 n-channel open-drain
P0.1 N-Channel Open-Drain Configurable Configure P0.1 push-pull Configure P0.1 n-channel open-drain
P0.0 N-Channel Open-Drain Configurable Configure P0.0 push-pull Configure P0.0 n-channel open-drain
4-33
MEMORY
KS57C5616/P5616
PNE2 N-Channel Open-Drain Mode Register
Identifier
RESET Value
FD8H
Read/Write Addressing
P3.3 N-Channel Open-Drain Configurable Configure P3.3 push-pull Configure P3.3 n-channel open-drain
P3.2 N-Channel Open-Drain Configurable Configure P3.2 push-pull Configure P3.2 n-channel open-drain
P3.1 N-Channel Open-Drain Configurable Configure P3.1 push-pull Configure P3.1 n-channel open-drain
P3.0 N-Channel Open-Drain Configurable Configure P3.0 push-pull Configure P3.0 n-channel open-drain
4-34
KS57C5616/P5616
MEMORY
Program Status Word
Identifier
RESET Value
1/4/8 1/4/8
FB1H, FB0H
1/4/8
1/4/8
Read/Write Addressing
Carry Flag overflow borrow condition exists overflow borrow condition does exist
SC2-SC0
Skip Condition Flags skip condition exists; direct manipulation these bits allowed skip condition exists; direct manipulation these bits allowed
IS1,
Interrupt Status Flags Service interrupt requests Service only high-priority interrupt(s) determined interrupt priority register (IPR) service more interrupt requests Undefined
Enable Data Memory Bank Flag Restrict program access data memory bank (F80H-FFFH) locations 000H-07FH bank only Enable full access data memory banks 0-14,
Enable Register Bank Flag Select register bank working register area Select register banks working register area accordance with select register bank (SRB) instruction operand
NOTES: value carry flag after RESET occurs during normal operation undefined. RESET occurs during power-down mode (IDLE STOP), current value carry flag retained. carry flag only addressed specific 1-bit manipulation instructions. Section detailed information.
4-35
MEMORY
KS57C5616/P5616
PUMOD1 Pull-up Resistor Mode Register Identifier
RESET Value
PUR3 PUR2
FDDH, FDCH
PUR1 PUR0
PUR7
PUR6
PUR5
PUR4
Read/Write Addressing PUR7
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR6
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR5
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR4
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR3
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR2
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR0
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
4-36
KS57C5616/P5616
MEMORY
PUMOD2 Pull-up Resistor Mode Register
Identifier
RESET Value
FDEH
PUR10
PUR9
PUR8
Read/Write Addressing
Always cleared logic zero
PUR10
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR9
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR8
Connect/Disconnect Port Pull-up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
4-37
MEMORY
KS57C5616/P5616
SCMOD System Clock Mode Control Register
Identifier
RESET Value
FB7H
Read/Write Addressing SCMOD.3
Enable main system clock Disable main system clock
SCMOD.2
Enable system clock Disable system clock
SCMOD.
Always logic zero
SCMOD.0
Select main system clock Select system clock
NOTES: SCMOD bits cannot modified simultaneously 4-bit instruction; they only modified separate 1-bit instructions. Sub-oscillation goes into stop mode only SCMOD.2. PCON which revokes stop mode cannot stop sub-oscillation. stop sub-oscillation released only reset regardless value SCMOD.2. SCMOD.2 follows (ex; after data bank used, minutes have passed): Main operation sub-operation sub-idle (LCD after minutes later without external input) sub-operation main operation SCMOD.2 main stop mode (LCD off).
4-38
KS57C5616/P5616
MEMORY
SMOD Serial Mode Register
Identifier
RESET Value
FE1H, FE0H
Read/Write Addressing SMOD.7-.5
Serial Clock Selection SBUF Status Control Bits external clock pin; Enable SBUF when operation halted when goes high TOL0 clock from timer/counter Enable SBUF when operation halted when goes high selected clock (fxx/4, "fxx" system clock) then, enable SBUF read/write operation. means don't care. 4.09 clock (fxx/210) clock (fxx/24); Note: cannot select fxx/24 clock frequency have selected clock fxx/64
NOTE: frequency ratings assume system clock 4.19 MHz.
SMOD.4
SMOD.3
Always logic zero
Initiate Serial Operation Clear IRQS flag 3-bit clock counter logic zero; then initiate serial transmission. When transmission starts, this cleared hardware logic zero Enable/Disable Data Shifter Clock Counter Disable data shifter clock counter; contents IRQS flag retained when serial transmission completed Enable data shifter clock counter; IRQS flag logic when serial transmission completed Serial Transmission Mode Selection Receive-only mode Transmit-and-receive mode
SMOD.2
SMOD.
SMOD.0
LSB/MSB Transmission Mode Selection Transmit most significant (MSB) first Transmit least significant (LSB) first
4-39
MEMORY
KS57C5616/P5616
TMOD0 Timer/Counter Mode Register
Identifier
RESET Value
T/C0
F91H, F90H
Read/Write Addressing TMOD0.7
Always logic zero
TMOD0.6-.4
Timer/Counter Input Clock Selection Bits External clock input TCL0 rising edge External clock input TCL0 falling edge Internal system clock (fxx) 4.19 MHz/210 (4.09 kHz) Select clock: fxx/26 (65.5 4.19 MHz) Select clock: fxx/24 (262 4.19 MHz) Select clock: (4.19 MHz)
TMOD0.3
Clear Counter Resume Counting Control Clear TCNT0, IRQT0, TOL0 resume counting immediately (This cleared automatically when counting starts.)
TMOD0.2
Enable/Disable Timer/Counter Disable timer/counter retain TCNT0 contents Enable timer/counter
TMOD0.
Always logic zero
TMOD0.0
Always logic zero
4-40
KS57C5616/P5616
MEMORY
TMOD1A Timer/Counter 1/1A Mode Register
Identifier
RESET Value
FA1H, FA0H
Read/Write Addressing TMOD1.7
16-bit Timer/Counter, 8-bit Timer/Counter 1A/1B Configuration Control 8-bit timer/counter 1A/1B mode (Timer/counter 16-bit timer/counter mode (Timer/counter
TMOD1.6-.4
Timer/Counter 1/1A Input Clock Selection External clock input (TCL1) rising edge External clock input (TCL1) falling edge fxx/210 4.09 fxx/26 65.5 fxx/24 4.19
TMOD1.3
Clear Counter Resume Counting Control Clear TCNT1A, IRQT1, TOL1 resume counting immediately when 8-bit timer 1A/1B mode configured (TMOD1.7 Clear TCNT1, IRQT1, TOL1 resume counting immediately when 16-bit timer mode configured (TMOD1.7
TMOD1.2
Enable/Disable 16-bit Timer/Counter 1/1A Disable timer/counter 1/1A; retain TCNT1A contents (TMOD1.7 TCNT1 (TMOD1.7 Enable timer/counter 1/1A
TMOD1.
Always logic zero
TMOD1.0
Always logic zero
MEMORY
KS57C5616/P5616
TMOD1B Timer/Counter Mode Register
Identifier
RESET Value
FA3H, FA2H
Read/Write Addressing TMOD1.7
Always logic zero
TMOD1.6-.4
Timer/Counter Input Clock Selection available available fxx/210 4.09 fxx/26 65.5 fxx/24 4.19
TMOD1.3
Clear Counter Resume Counting Control Clear TCNT1B, IRQT2, resume counting immediately (This cleared automatically when counting starts.)
TMOD1.2
Enable/Disable Timer/Counter Disable timer/counter retain TCNT1B contents Enable timer/counter
TMOD1.
Always logic zero
TMOD1.0
Always logic zero
4-42
KS57C5616/P5616
MEMORY
TOE0, TOE1, TOL2 Timer Output Enable Flags
Identifier
RESET Value
F92H
TOE1
TOE0
TOL2
Read/Write Addressing
Timer/Counter 1/1A Output Enable Flag Disable timer/counter output TCLO1 Enable timer/counter output TCLO1
TOE0
Timer/Counter Output Enable Flag Disable timer/counter output TCLO0 Enable timer/counter output TCLO0
Always logic zero
TOL2
Timer/Counter Output Latch Read Timer/Counter output clock low, 1-bit read-only addressable Timer/Counter output clock high, 1-bit read-only addressable
4-43
MEMORY
KS57C5616/P5616
VLC1R VLC1 Register
Identifier
RESET Value
FD9H
VLC1F
Bits
Read/Write Addressing VLC1R.3-.
Always logic zero
VLC1F.0
P2.1 Digital Input Analog Input Selection Configure P2.1 digital input Configure P2.1 analog input bias
4-44
KS57C5616/P5616
MEMORY
WDFLAG Watch-Dog Timer's Counter Clear Flag
Identifier
RESET Value
F9AH
WDTCF
Read/Write Addressing WDTCF
Watch-dog Timer's Counter Clear Clear WDT's counter zero restart WDT's counter
WDFLAG.2-.0
Bits Always logic zero
4-45
MEMORY
KS57C5616/P5616
WDMOD Watch-Dog Timer Mode Control Register
Identifier
RESET Value
F99H,F98H
Read/Write Addressing WMOD.7-.0
Watch-Dog Timer Enable/Disable Control Disable watch-dog timer function Enable watch-dog timer function Others
4-46
KS57C5616/P5616
MEMORY
WMOD Watch Timer Mode Register
Identifier
RESET Value
(note)
F89H,F88H
Read/Write Addressing WMOD.7
Enable/Disable Buzzer Output Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output Always logic zero
WMOD.6
WMOD.5-.4
Output Buzzer Frequency Selection Bits buzzer (BUZ) signal output buzzer (BUZ) signal output buzzer (BUZ) signal output buzzer (BUZ) signal output XTIN Input Level Control Input level XTIN low; 1-bit read-only addressable tests Input level XTIN high; 1-bit read-only addressable tests
WMOD.3
WMOD.2
Enable/Disable Watch Timer Disable watch timer clear frequency dividing circuits Enable watch timer Watch Timer Speed Control Normal speed; IRQW seconds High-speed operation; IRQW 3.91 Watch Timer Clock Selection Select main system clock (fx)/128 watch timer clock Select subsystem clock watch timer clock
WMOD.
WMOD.0
NOTES: RESET sets WMOD.3 current input level subsystem clock, XTIN. input level high, WMOD.3 logic one; low, WMOD.3 cleared zero along with other bits WMOD register. Main system clock frequency (fx) assumed 4.19 MHz; subsystem clock (fx) assumed 32.768
4-47
MEMORY
KS57C5616/P5616
NOTES
4-48
KS57C5616/P5616
SAM47 INSTRUCTION
SAM47 INSTRUCTION
SAM47 instruction includes 1-bit, 4-bit, 8-bit instructions data manipulation, logical arithmetic operations, program control, control. instructions peripheral hardware devices flexible easy use. Symbolic hardware names substituted instruction operand place actual address. Other important features SAM47 instruction include: 1-byte referencing long instructions (REF instruction) Redundant instruction reduction (string effect) Skip feature instructions Instruction operands conform operand format defined each instruction. Several instructions have multiple operand formats. Predefined values labels used instruction operands when addressing immediate data. Many symbols specific registers flags also substituted labels operations such mema, memb, Using instruction labels greatly simplify program writing debugging tasks. INSTRUCTION FEATURES this section, following SAM47 instruction features described detail: Instruction reference area Reducing instruction redundancy Flexible manipulation instruction skip condition
SAM47 INSTRUCTION
KS57C5616/P5616
INSTRUCTION REFERENCE AREA Using 1-byte (REFerence) instruction, reference instructions stored addresses 0020H-007FH program memory (the instruction look-up table). location referenced contain either 1-byte instructions single 2-byte instruction. starting address instruction being referenced must always even number. 3-byte instructions such CALL also referenced using REF. reference these 3-byte instructions, 2-byte pseudo commands TCALL must written reference area instead normal CALL instruction. incremented when instruction executed. After executes, program's instruction execution sequence resumes address immediately following instruction. using instructions execute instructions larger than byte, well branches subroutines, reduce total number program steps. summarize, instruction used three ways: Using 1-byte instruction execute 2-byte 1-byte instructions; Branching location referencing branch address that stored look-up table; Calling subroutines location referencing call address that stored look-up table. necessary, instruction circumvented means skip operation prior execution sequence. addition, instruction immediately following also skipped using appropriate reference instruction instructions. Two-byte instructions which referenced using instruction limited instructions with execution time machine cycles. exception this rule A,DA.) addition, when reference 1-byte instructions stored reference area, specific combinations must used first second 1-byte instruction. These combinations described Table 5-1. Table 5-1. Valid 1-Byte Instruction Combinations Look-Ups First 1-Byte Instruction Instruction Operand A,@HL @HL,A A,@HL Second 1-Byte Instruction Instruction INCS DECS INCS DECS INCS INCS DECS INCS DECS INCS INCS DECS INCS DECS Operand
A,@WX A,@WX
A,@WL A,@WL
NOTE: value first one-byte instruction "0", instruction cannot referenced instruction.
KS57C5616/P5616
SAM47 INSTRUCTION
REDUCING INSTRUCTION REDUNDANCY When redundant instructions such A,#im EA,#imm used consecutively program sequence, only first instruction executed. redundant instructions which follow ignored, that they handled like instruction. When HL,#imm instructions used consecutively, redundant instructions also ignored. following example, only #im" instruction will executed. 8-bit load instruction which follows interpreted redundant ignored: A,#im EA,#imm Load 4-bit immediate data (#im) accumulator Load 8-bit immediate data (#imm) extended accumulator
this example, statements A,#2H" A,#3H" ignored: BITR A,#1H A,#2H A,#3H 23H,A Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H
consecutive #imm instructions (load 8-bit immediate data 8-bit memory pointer pair, detected, only first executed which immediately follow ignored. example, HL,#10H HL,#20H A,#3H EA,#35H @HL,A Ignore, redundant instruction Ignore, redundant instruction (10H)
instruction reference with instruction redundancy effect, following conditions apply: instruction preceding redundancy effect, this effect cancelled referenced instruction skipped. instruction following redundancy effect, instruction following skipped.
PROGRAMMING Example Instruction Redundancy Effect
0020H EA,#30H 0080H Stored instruction reference area
EA,#40H
Redundancy effect encountered skip #30H)
EA,#50H
#30H Skip
SAM47 INSTRUCTION
KS57C5616/P5616
FLEXIBLE MANIPULATION addition normal manipulation instructions like clear, SAM47 instruction also perform tests, transfers, Boolean operations. Bits also addressed manipulated special addressing modes. Three types addressing supported: mema.b memb.@L @H+DA.b parameters these addressing modes described more detail Table 5-2. Table 5-2. Addressing Modes Parameters Addressing Mode mema.b memb.@L @H+DA.b Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx Ports 0-13 Ports 0-13, bit-manipulable peripheral hardware FB0H-FBFH FF0H-FFFH FC0H-FFFH bits memory bank specified that bit-manipulable Address Range
Instructions Which Have Skip Conditions following instructions have skip function when overflow borrow occurs: XCHI XCHD INCS DECS
there overflow borrow from result increment decrement, skip signal generated skip executed. However, carry flag value unaffected. instructions BTST, BTSF, CPSE also generate skip signal execute skip when they meet skip condition, carry flag value also unaffected. Instructions Which Affect Carry Flag only instructions which generate skip signal, which affect carry flag follows: BAND BXOR C,(operand) C,(operand) C,(operand) C,(operand)
KS57C5616/P5616
SAM47 INSTRUCTION
INSTRUCTION SKIP CONDITIONS instructions "ADC A,@HL" "SBC A,@HL" generate skip signal, clear carry flag, when they executed combination with instruction "ADS A,#im". "ADS A,#im" instruction immediately follows "ADC A,@HL" "SBC A,@HL" instruction program sequence, instruction does skip instruction following ADS, even skip function. however, "ADC A,@HL" "SBC A,@HL" instruction immediately followed "ADS A,#im" instruction, SBC) skips overflow there borrow) instruction immediately following ADS, program execution continues. Table contains additional information examples "ADC A,@HL" "SBC A,@HL" skip feature. Table 5-3. Skip Conditions Instructions Sample Instruction Sequences A,@HL A,#im A,@HL A,#im result instruction Overflow overflow Borrow borrow Then, execution sequence Reason cannot skip instruction even skip function. cannot skip instruction even skip function.
SAM47 INSTRUCTION
KS57C5616/P5616
SYMBOLS CONVENTIONS Table 5-4. Data Type Symbols Symbol Data Type Immediate data Address data data Register data Flag data Indirect addressing data memc immediate data Table 5-6. Instruction Operand Notation Symbol Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank Select memory bank Carry flag Program status word Port "m"-th port Interrupt priority register Enable memory bank flag Enable register bank flag Pn.m ADRn mema memb memc [(RR)] Definition Direct address Indirect address prefix Source operand Destination operand Contents register location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 0000H-3FFFH immediate address address FB0H-FBFH, FF0H-FFFH FC0H-FFFH Code direct addressing: 0020H-007FH Select bank register bits) Logical exclusive-OR Logical Logical Contents addressed
KS57C5616/P5616
SAM47 INSTRUCTION
OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register Table 5-8. Opcode Definitions (Indirect) Register
Immediate data indirect addressing
Immediate data register
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
CALCULATING ADDITIONAL MACHINE CYCLES SKIPS machine cycle defined cycle selected clock. Three different clock rates selected using PCON register. this document, letter used tables when describing number additional machine cycles required instruction execute, given that instruction skip function ("S" skip). addition number machine cycles that will required perform skip usually depends size instruction being skipped whether 1-byte, 2-byte, 3-byte instruction. skip also executed instructions. values additional machine cycles three cases which skip conditions occur follows: Case skip Case Skip 1-byte 2-byte instruction Case Skip 3-byte instruction cycles cycle cycles
NOTE: instructions skipped machine cycle.
KS57C5616/P5616
SAM47 INSTRUCTION
HIGH-LEVEL SUMMARY This section contains high-level summary SAM47 instruction table format. tables designed familiarize with range instructions that available each instruction category. These tables useful quick-reference resource when writing application programs. reading this user's manual first time, however, want scan this detailed information briefly, then return later following information provided each instruction: Instruction name Operand(s) Brief operation description Number bytes instruction operand(s) Number machine cycles required execute instruction tables this section arranged according following instruction categories: control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions manipulation instructions
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-9. Control Instructions High-Level Summary Name IDLE STOP VENTn memc (0,1) (0,1) Operand Operation Description carry flag logic Reset carry flag logic zero Complement carry flag Enable interrupts Disable interrupts Engage idle mode Engage stop mode operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) enable register bank flag (ERB) program counter vector address, then branch corresponding location Bytes Cycles
Table 5-10. Program Control Instructions High-Level Summary Name CPSE Operand R,#im @HL,#im A,@HL EA,@HL EA,RR ADR14 ADR12 CALL CALLS IRET SRET ADR14 ADR11 Operation Description Compare skip register equals Compare skip indirect data memory equals Compare skip equals Compare skip equals indirect data memory Compare skip equals indirect data memory Compare skip equals Jump direct address (14-bits) Jump direct page (12-bits) Jump immediate address Branch relative register Branch relative Call direct page (14-bits) Call direct page (11-bits) Return from subroutine Return from interrupt Return from subroutine skip Bytes Cycles
5-10
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-11. Data Transfer Instructions High-Level Summary Name Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA PUSH A,@HL A,@HL EA,@WX EA,@EA Operation Description Exchange direct data memory contents Exchange register (Ra) contents Exchange indirect data memory Exchange direct data memory contents Exchange register pair (RRb) contents Exchange indirect data memory contents Exchange indirect data memory contents; increment contents register skip carry Exchange indirect data memory contents; decrement contents register skip carry Load 4-bit immediate data Load indirect data memory contents Load direct data memory contents Load register contents Load 4-bit immediate data register Load 8-bit immediate data register Load contents direct data memory Load contents register Load indirect data memory contents Load direct data memory contents Load register contents Load contents indirect data memory Load contents direct data memory Load contents register Load contents indirect data memory Load indirect data memory increment register contents skip carry Load indirect data memory contents decrement register contents skip carry Load code byte from Load code byte from Rotate right through carry Push register pair onto stack Push values onto stack register pair from stack values from stack Bytes Cycles
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-12. Logic Instructions High-Level Summary Name Operand A,#im A,@HL EA,RR RRb,EA EA,RR RRb,EA A,#im A,@HL EA,RR RRb,EA Operation Description Logical-AND immediate data Logical-AND indirect data memory Logical-AND register pair (RR) Logical-AND register pair (RRb) Logical-OR immediate data Logical-OR indirect data memory contents Logical-OR double register Logical-OR double register Exclusive-OR immediate data Exclusive-OR indirect data memory Exclusive-OR register pair (RR) Exclusive-OR register pair (RRb) Complement accumulator Bytes Cycles
Table 5-13. Arithmetic Instructions High-Level Summary Name Operand A,@HL EA,RR RRb,EA EA,#imm A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA DECS INCS Operation Description indirect data memory with carry register pair (RR) with carry register pair (RRb) with carry 4-bit immediate data skip carry 8-bit immediate data skip carry indirect data memory skip carry register pair (RR) contents skip carry register pair (RRb) skip carry Subtract indirect data memory from with carry Subtract register pair (RR) from with carry Subtract from register pair (RRb) with carry Subtract indirect data memory from skip borrow Subtract register pair (RR) from skip borrow Subtract from register pair (RRb); skip borrow Decrement register (R); skip borrow Decrement register pair (RR); skip borrow Increment register (R); skip carry Increment direct data memory; skip carry Increment indirect data memory; skip carry Increment register pair (RRb); skip carry Bytes Cycles
5-12
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-14. Manipulation Instructions High-Level Summary Name BTST DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory carry Load specified indirect memory carry Load carry specified memory Load carry specified indirect memory Exclusive-OR carry with specified memory Logical-OR carry with specified memory Logical-AND carry flag with specified memory Clear specified memory logic zero specified memory Test specified bit; skip clear memory Test specified memory skip equals Operand Operation Description Test specified skip carry flag Test specified skip memory Bytes Cycles
5-13
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
BINARY CODE SUMMARY This section contains binary code values operation notation each instruction SAM47 instruction easy-to-read, tabular format. intended used quick-reference source programmers experienced with SAM47 instruction set. same binary values notation also included detailed descriptions individual instructions later Chapter reading this user's manual first time, please just scan this very detailed information briefly. Most general information will need write application programs found high-level summary tables previous section. following information provided each instruction: Instruction name Operand(s) Binary values Operation notation tables this section arranged according following instruction categories: control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions manipulation instructions
5-14
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-15. Control Instructions Binary Code Summary Name IDLE STOP VENTn memc (0,1) (0,1) Operand
Binary Code
Operation Notation PCON.2 PCON.3 operation PC13-0 memc7-4, memc3-0 EMB, PC13, PC12 PC11-8 PC7-0
5-15
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-16. Program Control Instructions Binary Code Summary Name CPSE Operand R,#im @HL,#im A,@HL EA,@HL EA,RR ADR14
Binary Code
Operation Notation Skip Skip (HL) Skip Skip (HL) Skip (HL), (HL+1) Skip PC13-0 ADR14
ADR12
PC13-0 PC13-12 ADR11-0 PC13-0 (PC-15 PC+16)
PC13-0 PC13-8 (WX) PC13-0 PC13-8 (EA) [(SP-1) (SP-2)] EMB, [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 [(SP-1) (SP-2)] EMB, [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC10-8
CALL
ADR14
CALLS
ADR1
First Byte
Condition
PC+2 PC+16 PC-1 PC-15
5-16
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-16. Program Control Instructions Binary Code Summary (Continued) Name Operand
Binary Code
Operation Notation PC13-8 (SP) PC7-0 EMB,ERB PC13-8 (SP) PC7-0 PC13-8 (SP) PC7-0 EMB,ERB
IRET
SRET
Table 5-17. Data Transfer Instructions Binary Code Summary Name Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra
Binary Code
Operation Notation (RRa) DA,E (HL), (HL), then L+1; skip (HL), then L-1; skip (RRa)
5-17
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-17. Data Transfer Instructions Binary Code Summary (Continued) Name Operand Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA PUSH A,@HL A,@HL EA,@WX EA,@EA
Binary Code
Operation Notation (HL), (HL) (HL) (HL), then L+1; skip (HL), then L-1; skip [PC13-8 (WX)] [PC13-8 (EA)] A.0, A.n-1 ((SP-1)) ((SP-2)) (RR), (SP) (SP)-2 ((SP-1)) (SMB), ((SP-2)) (SRB), (SP) (SP)-2
5-18
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-17. Data Transfer Instructions Binary Code Summary (Concluded) Name Operand
Binary Code
Operation Notation (SP), (SRB) (SP),
Table 5-18. Logic Instructions Binary Code Summary Name Operand A,#im A,@HL EA,RR RRb,EA EA,RR RRb,EA A,#im A,@HL EA,RR RRb,EA
Binary Code
Operation Notation (HL) (HL) (HL) (RR)
5-19
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-19. Arithmetic Instructions Binary Code Summary Name Operand A,@HL EA,RR RRb,EA EA,#imm A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA DECS INCS
Binary Code
Operation Notation (HL) skip carry imm; skip carry (HL); skip carry skip carry skip carry (HL) C,RRb (HL); skip borrow skip borrow skip borrow R-1; skip borrow RR-1; skip borrow skip carry skip carry (HL) (HL) skip carry skip carry
5-20
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-20. Manipulation Instructions Binary Code Summary Name BTST DA.b mema.b memb.@L Operand
Binary Code
Operation Notation Skip Skip DA.b Skip mema.b Skip [memb.7-2 L.3-2]. [L.1-0] Skip DA.3-0].b Skip DA.b Skip mema.b Skip [memb.7-2 L.3-2]. [L.1-0] Skip DA.3-0].b Skip mema.b clear Skip [memb.7-2 L.3-2]. [L.1-0] clear Skip DA.3-0].b clear DA.b mema.b [memb.7-2 L.3-2].b [L.1-0] DA.3-0].b
@H+DA.b BTSF DA.b mema.b memb.@L
DA.b BTSTZ mema.b memb.@L
@H+DA.b BITS DA.b mema.b memb.@L @H+DA.b
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Table 5-20. Manipulation Instructions Binary Code Summary (Continued) Name BITR Operand DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L
Binary Code
Operation Notation DA.b mema.b [memb.7-2 L3-2].[L.1-0] DA.3-0].b mema.b [memb.7-2 L.3-2]. [L.1-0] DA.3-0].b mema.b [memb.7-2 L.3-2]. [L.1-0] DA.3-0].b mema.b [memb.7-2 L.3-2]. [L.1-0] DA.3-0].b
C,@H+DA.b C,mema.b C,memb.@L
C,@H+DA.b BXOR C,mema.b C,memb.@L
C,@H+DA.b
Second Byte
Addresses
mema.b
FB0H-FBFH FF0H-FFFH
5-22
KS57C5616/P5616
SAM47 INSTRUCTION
Table 5-20. Manipulation Instructions Binary Code Summary (Concluded) Name Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b
Binary Code
Operation Notation mema.b memb.7-2 [L.3-2]. [L.1-0] [DA.3-0].b mema.b memb.7-2 [L.3-2] [L.1-0] DA.3-0].b
Second Byte
Addresses
mema.b
FB0H-FBFH FF0H-FFFH
5-23
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
INSTRUCTION DESCRIPTIONS This section contains detailed information programming examples each instruction SAM47 instruction set. Information arranged consistent format improve readability quick-reference resource application programmers. reading this user's manual first time, please just scan this very detailed information briefly order acquaint yourself with basic features instruction set. information elements instruction description format follows: Instruction name (mnemonic) Full instruction name Source/destination format instruction operand Operation overview (from "High-Level Summary" table) Textual description instruction's effect Binary code overview (from "Binary Code Summary" table) Programming example(s) show instruction used
5-24
KS57C5616/P5616
SAM47 INSTRUCTION
with Carry
Operation: dst,src Operand A,@HL EA,RR RRb,EA Description: Operation Summary indirect data memory with carry register pair (RR) with carry register pair (RRb) with carry Bytes Cycles
source operand, along with setting carry flag, added destination operand stored destination. contents source unaffected. there overflow from most significant result, carry flag set; otherwise, carry flag cleared. "ADC A,@HL" followed "ADS A,#im" instruction program, skips instruction overflow occurs. there overflow, instruction executed normally. (This condition valid only "ADC A,@HL" instructions. overflow occurs following "ADS A,#im" instruction, next instruction will skipped.) Operand A,@HL EA,RR RRb,EA Binary Code Operation Notation (HL)
Examples:
extended accumulator contains value 0C3H, register pair value 0AAH, carry flag "1": 0C3H 0AAH 6EH, Jump XXX; skip after
EA,HL
extended accumulator contains value 0C3H, register pair value 0AAH, carry flag cleared "0": 0C3H 0AAH 6DH, Jump XXX; skip after
EA,HL
5-25
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
with Carry
Examples: (Continued) A,@HL followed A,#im, skips carry instruction immediately after ADS. instruction immediately after does skip even overflow occurs. This function useful decimal adjustment operations. decimal addition (the contents address specified register 9H): A,#8H A,#6H A,@HL A,#0AH C(0), Skip this instruction because after result
decimal addition (the contents address specified register 4H): A,#3H A,#6H A,@HL A,#0AH C(0) skip. (The skip function "ADS A,#im" inhibited after "ADC A,@HL" instruction even overflow occurs.)
5-26
KS57C5616/P5616
SAM47 INSTRUCTION
Skip Overflow
Operation: dst,src Operand EA,#imm A,@HL EA,RR RRb,EA Operation Summary 4-bit immediate data skip overflow 8-bit immediate data skip overflow indirect data memory skip overflow register pair (RR) contents skip overflow register pair (RRb) skip overflow Bytes Cycles
Description:
source operand added destination operand stored destination. contents source unaffected. there overflow from most significant result, skip signal generated skip executed, carry flag value unaffected. "ADS A,#im" follows "ADC A,@HL" instruction program, skips instruction overflow occurs. there overflow, instruction executed normally. This skip condition valid only "ADC A,@HL" instructions, however. overflow occurs following instruction, next instruction skipped. Operand EA,#imm A,@HL EA,RR RRb,EA Binary Code skip overflow (HL); skip overflow skip overflow Operation Notation skip overflow imm; skip overflow
Examples:
extended accumulator contains value 0C3H, register pair value 0AAH, carry flag "0": EA,HL 0C3H 0AAH skips overflow, carry flag value affected. This instruction skipped since overflow. Jump YYY.
5-27
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
Skip Overflow
Examples: (Continued) extended accumulator contains value 0C3H, register pair value 12H, carry flag "0": EA,HL 0C3H 0D5H Jump XXX; skip after ADS.
"ADC A,@HL" followed "ADS A,#im", skips overflow instruction immediately after ADS. "ADS A,#im" instruction immediately after "ADC A,@HL" does skip even overflow occurs. This function useful decimal adjustment operations. decimal addition (the contents address specified register 9H): C(0) Skip this instruction because after result.
A,#8H A,#6H A,@HL A,#0AH
decimal addition (the contents address specified register 4H): C(0) 0DH, skip. (The skip function "ADS A,#im" inhibited after "ADC A,@HL" instruction even overflow occurs.)
A,#3H A,#6H A,@HL A,#0AH
5-28
KS57C5616/P5616
SAM47 INSTRUCTION
Logical
Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Description: Operation Summary Logical-AND immediate data Logical-AND indirect data memory Logical-AND register pair (RR) Logical-AND register pair (RRb) Bytes Cycles
source operand logically ANDed with destination operand. result stored destination. logical operation results whenever corresponding bits operands both "1"; otherwise stored corresponding destination bit. contents source unaffected. Operand A,#im A,@HL EA,RR RRb,EA Binary Code (HL) Operation Notation
Example:
extended accumulator contains value 0C3H (11000011B) register pair value (01010101B), instruction EA,HL
leaves value (01000001B) extended accumulator
5-29
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
BAND Logical
BAND Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Description: Operation Summary Logical-AND carry flag with memory Bytes Cycles
specified source logically ANDed with carry flag value. Boolean value source logic zero, carry flag cleared "0"; otherwise, current carry flag setting left unaltered. value source operand affected. Operand C,mema.b C,memb.@L C,@H+DA.b Binary Code DA.3-0].b Operation Notation mema.b [memb.7-2 L.3-2]. [L.1-0]
Second Byte
Addresses FB0H-FBFH FF0H-FFFH
mema.b
Examples:
following instructions carry flag P1.0 (port 1.0) equal (and assuming carry flag already "1"): BAND C,P1.0 P1.0 "1", P1.0 "0",
5-30
KS57C5616/P5616
SAM47 INSTRUCTION
BAND Logical
BAND Examples: (Continued) Assume address FF1H value register (1001B). address (memb.7-2) 111100B; (L.3-2) 10B. resulting address 11110010B FF2H, specifying value BAND instruction, (L.1-0) which specifies Therefore, P1.@L P2.1: BAND L,#9H C,P1.@L P1.@L specified P2.1
Register contains value FLAG 20H.3. address 0010B FLAG(3-0) 0000B. resulting address 00100000B 20H. value BAND instruction Therefore, @H+FLAG 20H.3: FLAG BAND 20H.3 H,#2H C,@H+FLAG
FLAG (20H.3)
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
BITR Reset
BITR Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Clear specified memory logic zero Bytes Cycles
Description:
BITR instruction clears logic zero (resets) specified within destination operand. other bits destination affected. Operand DA.b mema.b memb.@L @H+DA.b Binary Code DA.3-0].b mema.b [memb.7-2 L3-2].[L.1-0] Operation Notation DA.b
Second Byte
Addresses FB0H-FBFH FF0H-FFFH
mema.b
Examples:
location 30H.2 current value logic one. following instruction clears third location (bit logic zero: BITR 30H.2 30H.2
BITR same manipulate port address bit: BITR P2.0 P2.0
5-32
KS57C5616/P5616
SAM47 INSTRUCTION
BITR Reset
BITR Examples: (Continued) Assuming that P2.2, P2.3, P3.0-P3.3 cleared "0": BITR INCS L,#0AH P0.@L First, P0.@0AH P2.2 (111100B) 10B.10B 0F2H.2
bank location 0A0H.0 cleared (and regardless whether value logic zero), BITR following effect: FLAG BITR BITR 0A0H.0
H,#0AH @H+FLAG; Bank 0H).0 0A0H.0
NOTE: Since BITR instruction used output functions, names used examples above change different devices SAM47 product family.
5-33
SAM47 INSTRUCTION
KS57C5616/P5616 (Preliminary Spec)
BITS
BITS Operation: dst.b Operand DA.b mema.b memb.@L
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