µPD78P054, 78P058 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPT

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µPD78P054, 78P058 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPT

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INTEGRATED CIRCUIT
µPD78P054, 78P058
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P054 78P058 members µPD78054 Subseries 78K/0 Series products, which on-chip mask µPD78054 78058 replaced with one-time PROM EPROM. Because these devices programmed users, they ideally suited applications involving evaluation systems development stages, small-scale production many different products, rapid development time-to-market product. Caution reliability µPD78P054KK-T 78P058KK-T guaranteed when used massproduction applications. Please these devices only experimentally evaluation during trial manufacture. Detailed function descriptions provided following user's manuals. sure read them before designing.
µPD78054, 78054Y Subseries User's Manual: U11747E
78K/0 Series User's Manual Instructions: U12326E
FEATURES
compatible with mask versions (except pin) Internal high-capacity PROM
Parameter Part Number Program Memory (PROM) KbytesNote Internal Data Memory High-Speed 1024 bytesNote Buffer bytes Expansion None 1024 bytesNote
µPD78P054 µPD78P058
KbytesNote
µPD78P05xKK-T:
Reprogrammable (ideal system evaluation)
µPD78P05xGC, 78P05xGK: Programmable once only (ideal small-scale production) Operable same supply voltage range mask versions (VDD Corresponding QTOPmicrocontrollers Notes internal PROM internal high-speed capacity changed using internal memory size switching register (IMS). internal expansion capacity changed using internal expansion size switching register (IXS). Remarks QTOP microcontroller general name microcontrollers with one-time PROM that totally supported writing service (from writing marking, screening, testing). differences between PROM versions mask versions, refer DIFFERENCES BETWEEN µPD78P054, 78P058 MASK VERSIONS. this document, "PROM" used sections common one-time PROM EPROM versions.
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. Document U10417EJ3V0DS00 (3rd edition) Date Published August 1999 CP(K) Printed Japan
mark
shows major revised points.
1994, 1999
µPD78P054, 78P058
ORDERING INFORMATION
Part Number Package 80-pin plastic resin thickness 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN 80-pin plastic resin thickness 80-pin ceramic WQFN Internal One-time PROM One-time PROM EPROM One-time PROM EPROM Quality Grade Standard Standard applicable Standard applicable
µPD78P054GC-8BT µPD78P054GK-BE9 µPD78P054KK-T µPD78P058GC-8BT µPD78P058KK-T
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
78K/0 SERIES LINEUP
products 78K/0 Series listed below. names enclosed boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F µPD78054 µPD780065 PD780078 PD780034A PD780024A µPD78014H
µPD78018F PD78083
Inverter control
EMI-noise reduced version PD78078
µPD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y PD780078Y PD780034AY
PD780024AY PD78018FY
µPD78054 with timer added enhanced external interface
ROM-less version µPD78078 µPD78078Y with enhanced serial limited functions
PD78054 with enhanced serial
EMI-noise reduced version PD78054
µPD78018F with added UART converter enhanced µPD780024 with increased capacity
timer added µPD780034A serial enhanced
PD780024 with enhanced converter µPD78018F with enhanced serial EMI-noise reduced version µPD78018F
Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin
µPD780988
FIPdrive
On-chip inverter control circuit UART. EMI-noise reduced.
100-pin 78K/0 Series 100-pin 80-pin 80-pin 80-pin
PD780208 PD780228 PD780232 µPD78044H µPD78044F
drive
µPD78044F with enhanced C/D. Display output total: µPD78044H with enhanced C/D. Display output total:
panel control. On-chip C/D. Display output total:
µPD78044F with added N-ch open drain I/O. Display output total:
Basic subseries driving FIP. Display output total:
100-pin 100-pin 100-pin
PD780308 µPD78064B µPD78064
PD780308Y PD78064Y
µPD78064 with enhanced SIO, increased ROM, capacity.
EMI-noise reduced version PD78064 Basic subseries driving LCDs, on-chip UART
Call supported 80-pin
PD780841
interface supported
On-chip Call function, simple DTMF. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780948 PD78098B PD780701Y PD780833Y
Meter control
On-chip D-CAN controller PD78054 with IEBuscontroller added. EMI-noise reduced. On-chip D-CAN/IEBus controller On-chip controller compliant with J1850 (Class
100-pin 80-pin 80-pin
µPD780958 µPD780955 µPD780973
industrial meter control Ultra low-power consumption. On-chip UART. On-chip automobile meter controller/driver
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
major functional differences among subseries listed below.
Function Subseries Name Control Capacity Timer 8-Bit 10-Bit 8-Bit 8-bit 16-bit Watch MIN. External Value Expansion
Serial Interface
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780065 µPD780078 µPD780024A µPD78014H µPD78018F µPD78083 µPD780988 µPD780208 µPD780228 µPD780232 µPD78044H µPD78044F µPD780308 µPD78064B µPD78064
(UART:
(time division UART: (UART:
(UART: (UART: (UART:
µPD780034A
(UART: (UART: (time division UART: (UART:
Inverter control drive
Note
drive
Call µPD780841 supported µPD780948 interface supported µPD78098B Meter control
(UART: (UART:
µPD780958 µPD780955 µPD780973
(UART: (UART: (UART:
Note 16-bit timer: channels 10-bit timer: channel
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
OVERVIEW FUNCTIONS
Part Number Item Internal memory PROM High-speed Buffer Expansion Memory space General registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction KbytesNote 1024 bytesNote bytes None Kbytes bits registers bits registers banks) Minimum instruction execution time variable. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 5.0-MHz operation) 32.768-kHz operation) 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc. 1024 bytesNote KbytesNote
µPD78P054
µPD78P058
ports
Total: CMOS input: CMOS input/output: N-ch open-drain input/output: 8-bit resolution 8-bit resolution 3-wire serial I/O, SBI, 2-wire serial mode selectable: 3-wire serial mode (with on-chip max. 32-byte automatic transmit/receive function): 3-wire serial UART mode selectable: 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: (14-bit output capable: 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, 5.0-MHz operation with main system clock) 32.768 32.768-kHz operation with subsystem clock) kHz, kHz, 5.0-MHz operation with main system clock) Maskable Non-maskable Software Internal: external: Internal: Internal: external: +85°C 80-pin plastic resin thickness 80-pin plastic TQFP (fine pitch) µPD78P054 only 80-pin ceramic WQFN
converter converter Serial interface
Timer
Timer outputs Clock output
Buzzer output Vectored interrupt sources Test inputs Supply voltage Operating ambient temperature Package
Notes internal PROM/internal high-speed capacity changed using internal memory size switching register (IMS). internal expansion capacity changed using internal expansion size switching register (IXS).
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CONFIGURATIONS (Top View)
Normal operating mode 80-pin plastic resin thickness
µPD78P054GC-8BT, 78P058GC-8BT
80-pin plastic TQFP (fine pitch)
µPD78P054GK-BE9
80-pin ceramic WQFN
µPD78P054KK-T, 78P058KK-T
P01/INTP1/TI01 P00/INTP0/TI00
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P57/A15
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
Data Sheet U10417EJ3V0DS00
P64/RD
µPD78P054, 78P058
A15: AD7: ANI0 ANI7: ANO0, ANO1: ASCK: ASTB: AVDD: AVREF0, AVREF1: AVSS: BUSY: BUZ: P07: P17: P27: P37: P67: P72: P120 P127: P130, P131: PCL: Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Port Port Port Port Port Port Port Port Port Port Programmable Clock RESET: RTP0 RTP7: RxD: SB0, SB1: SCK0 SCK2: SI2: SO2: STB: TI00, TI01: TI1, TI2: TO2: TxD: VDD: VPP: VSS: WAIT: XT1, XT2: Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
INTP0 INTP6: External Interrupt Input
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM programming mode 80-pin plastic resin thickness
µPD78P054GC-8BT, 78P058GC-8BT
80-pin plastic TQFP (fine pitch)
µPD78P054GK-BE9
80-pin ceramic WQFN
µPD78P054KK-T, 78P058KK-T
Open Open
RESET
Cautions (L): VSS: Open: A16: PGM:
Individually connect pull-down resistor. Connect GND. connection RESET: VDD: VPP: VSS: Reset Power Supply Programming Power Supply Ground
RESET: level.
Address Chip Enable Data Output Enable Program
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33
16-Bit TIMER/ EVENT COUNTER
PORT
8-Bit TIMER/ EVENT COUNTER
PORT
TO2/P32 TI2/P34
8-Bit TIMER/ EVENT COUNTER
PORT
WATCHDOG TIMER
PORT
WATCH TIMER
PORT
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SERIAL INTERFACE SERIAL INTERFACE
78K/0 CORE
PROM
PORT
PORT
PORT
SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 ANI7/P17 AVDD AVSS AVREF0 ANO0/P130 ANO1/P131 AVSS AVREF1
SERIAL INTERFACE
PORT
P120 P127
PORT
P130, P131
CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127 AD0/P40 AD7/P47 A8/P50 A15/P57
CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET XT1/P07
INTP0/P00 INTP6/P06
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL
PCL/P35
CLOCK OUTPUT CONTROL
Remark internal PROM internal capacities differ depending product.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CONTENTS DIFFERENCES BETWEEN µPD78P054, 78P058 MASK VERSIONS FUNCTIONS
Pins Normal Operating Mode Pins PROM Programming Mode Input/Output Circuits Recommended Connection Unused Pins
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) (µPD78P058 ONLY) PROM PROGRAMMING
Operating Modes PROM Write Procedure PROM Read Procedure
ERASURE METHOD (µPD78P054KK-T, 78P058KK-T ONLY) ERASURE WINDOW OPAQUE FILM (µPD78P054KK-T, 78P058KK-T ONLY) SCREENING ONE-TIME PROM VERSIONS.30 ELECTRICAL SPECIFICATIONS CHARACTERISTICS CURVES (FOR REFERENCE ONLY) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
DIFFERENCES BETWEEN µPD78P054, 78P058 MASK VERSIONS
µPD78P054 78P058 single-chip microcontrollers with on-chip one-time writable PROM with onchip EPROM which program write, erasure, rewrite capability. possible make functions, except PROM specification mask option pins, same those mask versions setting internal memory size switching register (IMS) internal expansion size switching register (IXS). Differences between PROM versions (µPD78P054 78P058) mask versions (µPD78052, 78053, 78054, 78055, 78056, 78058) shown Table 1-1. Table 1-1. Differences between µPD78P054, 78P058 Mask Versions
Item Internal structure Internal capacity
µPD78P054, 78P058 One-time PROM/EPROM µPD78P054: Kbytes µPD78P058: Kbytes
Mask Versions Mask
µPD78052: µPD78053: µPD78054: µPD78055: µPD78056: µPD78058:
Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Internal high-speed capacity Internal expansion capacity Change internal internal high-speed capacity internal memory size switching register (IMS) Change internal expansion capacity internal expansion size switching register (IXS) Pull-up resistor on-chip mask option pins Electrical specifications, recommended soldering conditions
1024 bytes
µPD78052: bytes Other than µPD78052: 1024 bytes µPD78058: 1024 bytes Other than µPD78058: None
Cannot changed
µPD78P054: None µPD78P058: 1024 bytes
changedNote
changedNote
Cannot changed
None Provided None Refer data sheet each product.
Provided None Provided
Notes internal PROM capacity internal high-speed capacity become follows RESET input. Internal PROM capacity: Kbytes (µPD78P054), Kbytes (µPD78P058) Internal high-speed capacity: 1024 bytes internal expansion capacity becomes 1024 bytes RESET input (µPD78P058 only). Caution PROM version mask version differ noise tolerance noise emission. When replacing PROM version with mask version when switching from experimental production mass production, make thorough evaluation with (commercial sample) version (not (engineering sample) version) mask version. Remarks µPD78P054 PROM version µPD78052, 78053, 78054. µPD78P058 PROM version µPD78055, 78056, 78058. internal expansion size switching register (IXS) included only µPD78058 78P058.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
FUNCTIONS
Pins Normal Operating Mode
Port pins (1/2)
Name P07Note Input Input/output Input only Port 8-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.Note Port 8-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Input Input Input/Output Input Input/output Port 8-bit input/output port Function Input only Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 ANI0 ANI7
Input/output
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/output
Port 8-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Input
Notes When using P07/XT1 input port, (FRC) processor clock control register (PCC) sure feedback resistor subsystem clock oscillation circuit). When using P10/ANI0 P17/ANI7 pins converter analog input pins, port input mode. this time, pull-up resistors automatically disconnected.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Port pins (2/2)
Name Input/Output Input/output Function Port 8-bit input/output port Input/output specified 8-bit units. When used input port, on-chip pull-up resistor specified means software. test input flag (KRIF) falling edge detection. Port 8-bit input/output port LEDs driven directly. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 8-bit input/output port Input/output specified 1-bit units. N-ch open-drain input/output port. LEDs driven directly. After Reset Input Alternate Function
Input/output
Input
P120 P127
Input/output
Input
When used input port, on-chip pull-up resistor specified means software. Input/output Port 3-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Input/output Port 8-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 2-bit input/output port Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Input
WAIT ASTB
Input
SI2/RXD SO2/TXD SCK2/ASCK
Input
RTP0 RTP7
P130, P131
Input/output
Input
ANO0, ANO1
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Non-port pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01 RTP0 RTP7 Output Output Output Input/output Output Output Output Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Serial data input asynchronous serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) 16-bit timer (TM0) output (also used 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port which outputs data synchronization with trigger Lower address/data expanding memory externally Higher address expanding memory externally Strobe signal output reading from external memory Strobe signal output writing external memory Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input/output Serial interface serial clock input/output Input Input/output Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input Input/Output Input Function External interrupt request input which valid edge (rising edge, falling edge, both rising falling edges) specified. After Reset Input Alternate Function P00/TI00 P01/TI01 P25/SB0 P70/RXD P26/SB1 P71/TXD P25/SI0 P26/SO0 P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P127
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Non-port pins (2/2)
Name WAIT ASTB ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET Input/Output Input Output Input Output Input Input Input Input Input Positive power supply High-voltage applied during program write/verify. Connect directly normal operating mode. Ground potential Connecting crystal resonator subsystem clock oscillation Function Wait insertion when accessing external memory Strobe output that externally latches address information output ports access external memory Analog input converter Analog output converter Reference voltage input converter Reference voltage input converter Analog power supply converter. Connect VDD. Ground potential converter converter. Connect VSS. System reset input Connecting crystal resonator main system clock oscillation After Reset Input Input Input Input Input Alternate Function P130, P131
Pins PROM Programming Mode
Input/Output Input Function PROM programming mode setting When +12.5 applied low-level signal applied RESET pin, this chip PROM programming mode. PROM programming mode setting high-voltage applied during program write/verification Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programming mode Positive power supply Ground potential
Name RESET
Input Input Input/output Input Input Input
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Input/Output Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins shown Table 2-1. input/output circuit configuration each type, Figure 2-1.
Table 2-1. Input/Output Circuits (1/2)
Input/Output Circuit Type
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1
Input
Recommended Connection Unused Pins Connect VSS. Independently connect resistor.
10-A
Input
Connect VSS. Independently connect resistor.
13-D
Independently connect resistor. Independently connect resistor. Independently connect resistor. Independently connect resistor.
12-A Independently connect resistor.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Table 2-1. Input/Output Circuit Type (2/2)
Input/Output Circuit Type
Name RESET AVREF0 AVREF1 AVDD AVSS
Input
Recommended Connection Unused Pins Leave open. Connect VSS. Connect VDD.
Connect VSS. Connect directly VSS.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 2-1. Input/Output Circuits (1/2)
Type
Type
Pullup enable
P-ch
Data
P-ch IN/OUT
Output disable
N-ch
Schmitt-triggered input with hysteresis characteristic
Type
Type 10-A
Pullup enable Data
P-ch
Pullup enable Data P-ch
P-ch
P-ch IN/OUT Open drain Output disable
IN/OUT N-ch
Output disable
N-ch
Input enable
Type
Type
Pullup enable P-ch P-ch IN/OUT Output disable N-ch P-ch N-ch VREF (Threshold voltage) Input enable
Pullup enable Data P-ch
P-ch
Data
IN/OUT Output disable N-ch
Comparator
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 2-1. Input/Output Circuits (2/2)
Type 12-A
Type
Feedback cut-off P-ch
Pullup enable Data P-ch
P-ch
IN/OUT Output disable Input enable N-ch
Analog output voltage
P-ch N-ch
Type 13-D
IN/OUT Data Output disable N-ch
P-ch
Middle-voltage input buffer
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
register that software used specify part internal memory that used. setting IMS, internal memory (ROM, RAM) µPD78P054, 78P058 mapped identically that mask version. with 8-bit memory manipulation instruction. RESET input sets (µPD78P054)/CFH (µPD78P058). Figure 3-1. Format Internal Memory Size Switching Register (µPD78P054)
Symbol Address FFF0H After reset
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Selection internal capacity Kbytes Kbytes Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection internal high-speed capacity bytes 1024 bytes Setting prohibited
Other than above
Table shows setting values which make memory same that various mask versions. Table 3-1. Internal Memory Size Switching Register Setting Values (µPD78P054)
Target Mask Version Setting Value
µPD78052 µPD78053 µPD78054
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 3-2. Format Internal Memory Size Switching Register (µPD78P058)
Symbol Address FFF0H After reset
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Selection internal capacity Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Note Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection internal high-speed capacity bytes 1024 bytes Setting prohibited
Other than above
Note
internal capacity Kbytes less when external device expansion function used.
Table shows setting values which make memory same that various mask versions. Table 3-2. Internal Memory Size Switching Register Setting Values (µPD78P058)
Target Mask Version Setting Value
µPD78052 µPD78053 µPD78054 µPD78055 µPD78056 µPD78058
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) (µPD78P058 ONLY)
register that software used internal expansion capacity. setting IXS, possible same memory that mask version having different internal expansion capacity. with 8-bit memory manipulation instruction. RESET input sets 0AH. Figure 4-1. Format Internal Expansion Size Switching Register
Symbol
Address FFF4H
After reset
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Selection internal expansion capacity byte 1024 bytes Setting prohibited
Other than above
Table shows setting values which make memory same that various mask versions. Table 4-1. Internal Expansion Size Switching Register Setting Values
Target Mask Version Setting Value
µPD78052 µPD78053 µPD78054 µPD78055 µPD78056 µPD78058
Remark Even µPD78P058 program that includes "MOV IXS, #0CH" implemented µPD78052, 78053, 78054, 78055, 78056, operation will affected.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM PROGRAMMING
µPD78P054 78P058 have Kbytes Kbytes respectively on-chip PROM program memory. programming, PROM programming mode with RESET pins. connector unused pins, refer CONFIGURATIONS (Top View) PROM programming mode. Caution program µPD78P054 should written address range 0000H 7FFFH (the last address, 7FFFH, should specified). program µPD78P058 should written address range 0000H EFFFH (the last address, EFFFH, should specified). Writing cannot performed with PROM programmer that cannot specify write addresses. Operating Modes
When +12.5 applied level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM. Table 5-1. Operating Modes PROM Programming
Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance
RESET
Remark
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, data read from device controlling pin, multiple µPD78P054s 78P058s connected data bus. Standby mode Standby mode set. this mode, data output becomes high-impedance irrespective status. Page data latch mode Page data latch mode when page write mode entered. this mode, 1-page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying 0.1-ms program pulse (active low) with Program verification then performed when set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when 0.1-ms program pulse (active low) applied with Program verification then performed when set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, after writing, check write operation performed correctly. Program inhibit mode Program inhibit mode used when pin, pin, pins multiple µPD78P054s 78P058s connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Write Procedure Figure 5-1. Page Program Mode Flowchart
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 0.1-ms program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes pass writing
Fail
Defective product
Remark Start address Program last address
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 5-2. Page Program Mode Timing
Page data latch
Page program
Program verify
Hi-Z Data input Data output
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 5-3. Byte Program Mode Flowchart
Start Address 12.5
X=X+1 0.1-ms program pulse Address Address Fail Verify Pass Address Pass Fail
Verify bytes pass writing
Defective product
Remark Start address Program last address
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure 5-4. Byte Program Mode Timing
Program
Program verify
Hi-Z Data input Data output
Cautions should applied before removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Read Procedure
contents PROM read external data using read procedure shown below. RESET level, supply pin, connect other unused pins shown CONFIGURATIONS (Top View) PROM programming mode. Supply pins. Input address data read pins. Read mode Output data pins. timing above steps shown Figure 5-5. Figure 5-5. PROM Read Timing
Address input
(Input)
(Input)
Hi-Z
Data output
Hi-Z
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
ERASURE METHOD (µPD78P054KK-T, 78P058KK-T ONLY)
µPD78P054KK-T 78P058KK-T capable erasing (FFH) contents data written program memory rewriting. When erasing data, irradiate light having wavelength less than about window package. Normally, ultraviolet rays 254-nm wavelength should used. volume irradiation required completely erase data follows: intensity erasing time: more Erasing time: minutes more (When lamp mW/cm2 used. However, longer time needed because deterioration performance lamp, contamination erasing window, etc.) When erasing data, lamp within from erasing window. Further, filter provided lamp, remove filter during erasure process.
ERASURE WINDOW OPAQUE FILM (µPD78P054KK-T, 78P058KK-T ONLY)
protect from unintentional erasure other than EPROM erasure lamp light, protect internal circuits other than EPROM from malfunction light coming through window, mask window with attached opaque film when EPROM erasure being performed.
SCREENING ONE-TIME PROM VERSIONS
one-time PROM versions (µPD78P054GC-8BT, 78P054GK-BE9, 78P058GC-8BT) cannot tested completely before being shipped, because their structure. recommended perform screening verify PROM after writing necessary data following high-temperature storage under conditions below.
Storage Temperature 125°C Storage Time hours
present, charged one-time PROM writing, marking, screening, verifying service QTOP microcontrollers. details, contact your sales representative.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, XT2, RESET Output voltage Analog input voltage Output current, high Total P06, P37, P56, P57, P67, P120 P127 Total P17, P27, P47, P55, P72, P130, P131 Output current, IOLNote peak value r.m.s. value Total peak value r.m.s. value Total P56, P57, peak value r.m.s. value Total P17, P27, P47, P72, P130, P131 Total P06, P37, P67, P120 P127 Operating ambient temperature Storage temperature peak value r.m.s. value peak value r.m.s value Analog input pins N-ch open-drain PROM programming mode -0.3 -0.3 +13.5 -0.3 AVSS AVREF0 Conditions Ratings -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Tstg
+150
Note r.m.s. values should calculated follows: [r.m.s. value] [peak value] Duty Caution Product quality suffer absolute maximum rating exceeded momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note Conditions Oscillation voltage range MIN. TYP. MAX. Unit
Oscillation stabilization timeNote
After reached MIN. oscillation voltage range
Crystal resonator
Oscillation frequency (fX)Note
Oscillation stabilization timeNote
External clock
input frequency (fX)Note input high-/low-level width (tXH/t
PD74HCU04
Notes Indicates only oscillator characteristics. Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note Conditions MIN. TYP. MAX. Unit 32.768
Oscillation stabilization timeNote
External clock
input frequency (fXT)Note input high-/lowlevel width (tXTH/tXTL)
PD74HCU04
Notes Indicates only oscillator characteristics. Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillation voltage range MIN. Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. subsystem clock oscillator designed low-amplitude circuit reducing current consumption, more prone malfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Recommended Oscillator Constant µPD78P054 Main system clock: Ceramic resonator +85°C)
Manufacturer Product Name Frequency (MHz) Corp. CCR4.0MC3 CCR5.0MC3 Recommended Circuit Constant (pF) On-chip On-chip (pF) On-chip On-chip Oscillation Voltage Range MIN. MAX.
Subsystem clock: Crystal resonator +85°C)
Manufacturer Product Name Frequency (kHz) Daishinku Corp. DT-38 (1TA252E00, load capacitance 12.5 32.768 Recommended Circuit Constant (pF) (pF) Oscillation Voltage Range MIN. MAX.
Caution
oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
µPD78P058 Main system clock: Ceramic resonator +80°C)
Manufacturer Product Name Frequency (MHz) Kyocera Corp. KBR-4.19MKS 4.19 Recommended Circuit Constant (pF) On-chip (pF) On-chip Oscillation Voltage Range MIN. MAX.
Main system clock: Ceramic resonator +85°C)
Manufacturer Product Name Frequency (MHz) Murata Mfg. Co., Ltd. CST5.00MGW CSA5.00MG Recommended Circuit Constant (pF) On-chip (pF) On-chip Oscillation Voltage Range MIN. MAX.
Caution
oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Capacitance 25°C,
Parameter Input capacitance Input/output capacitance Symbol Conditions MHz, Unmeasured pins returned Unmeasured pins returned P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 VIH2 P06, P20, P22, P27, P33, P34, P70, P72, RESET VIH3 (N-ch open-drain) VIH4 MIN. 0.7VDD TYP. MAX. Unit
0.8VDD
0.8VDD 0.85VDD 0.7VDD 0.8VDD
0.3VDD
VIH5
XT1/P07,
VNote
0.8VDD 0.9VDD 0.9VDD
Input voltage,
VIL1
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131
0.2VDD
VIL2
P06, P20, P22, P27, P33, P34, P70, P72, RESET
0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.2VDD 0.1VDD 0.1VDD
VIL3
VIL4
VIL5
XT1/P07,
VNote
Output voltage, high
VOH1
-100
Output voltage,
VOL1
P57,
P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 N-ch open-drain, with pull-up resistor
0.2VDD
VOL3
Note When XT1/P07 used P07, inverse phase should input using inverter. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, high Output leakage current, Software pull-up resistorNote ILOH1 ILOL1
-3Note
Notes P63, low-level input leakage current -200 (MAX.) flows only clocks (without wait) after read instruction been executed port (P6) port mode register (PM6). times other than this 1.5-clock interval (MAX.) current flows. software pull-up resistor only used range Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics +85°C,
Parameter Supply currentNote Symbol IDD1 Conditions 5.0-MHz crystal oscillation operating mode (fXX MHz)Note ±10%Note ±10%Note 5.0-MHz crystal oscillation operating mode (fXX IDD2 MHz)Note ±10%Note ±10%Note MIN. TYP. 0.65 0.05 0.05 MAX. 27.0 1.95 12.5 Unit
±10%Note ±10% ±10% ±10%
5.0-MHz crystal oscillation HALT mode (fXX MHz)Note
5.0-MHz crystal oscillation HALT mode (fXX MHz)Note IDD3 32.768-kHz crystal oscillation operating modeNote IDD4 32.768-kHz crystal oscillation HALT modeNote
±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10%
IDD5
STOP mode Feedback resistor used
±10% ±10% ±10% ±10% ±10% ±10%
IDD6
STOP mode Feedback resistor used
Notes High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H) Operation with main system clock fX/2 (when oscillation mode selection register (OSMS) 00H) Operation with main system clock (when OSMS 01H) Refers current flowing through AVDD pins. current flowing converter, converter, on-chip pull-up resistors included. When main system clock operation stopped.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics Basic operation +85°C,
Parameter Cycle time (minimum instruction execution time) Symbol Conditions Operating with main system clock (fXX MHz)Note MIN. 40Note tTIH, tTIL tTIH, tTIL tINTH, tINTL INTP0 INTP1 INTP6, 8/fsamNote RESET low-level width tRSL 8/fsamNote TYP. MAX. Unit
Operating with main system clock (fXX MHz)Note
Operating with subsystem clock TI01, TI1, input frequency TI00 input high-/lowlevel width TI01, TI1, TI2, input high-/low-level width Interrupt request input high-/low-level width
Notes Operation with main system clock fX/2 (when oscillation mode selection register (OSMS) 00H) Operation with main system clock (when OSMS 01H) Value when external clock used. When crystal resonator used, (MIN.). Selection fsam fXX/2N, fXX/32, fXX/64, fXX/128 possible using bits (SCS0 SCS1) sampling clock selection register (SCS) (when
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
fX/2 main system clock operation) main system clock operation)
Cycle time [µs]
Guaranteed operation range
Cycle time [µs]
Guaranteed operation range
Supply voltage
Supply voltage
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Read/write operations When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 0.85tCY 0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY 1.15tCY 1.15tCY 2n)tCY (2.85 2n)tCY 0.85tCY 2tCY 2tCY 2n)tCY Conditions MIN. 0.85tCY 0.85tCY (2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY MAX. Unit
ASTB delay time from external fetch tRDAST Address hold time from external fetch tRDADH Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Except when PCC2 PCC0 000B +85°C, (1/2)
Parameter ASTB high-level width Symbol tASTH Conditions MIN. Address setup time tADS Address hold time tADH 0.4tCY 0.37tCY Data input time from address tADD1 2n)tCY 2n)tCY tADD2 2n)tCY 2n)tCY Data input time from tRDD1 (1.4 2n)tCY (1.37 2n)tCY tRDD2 (2.4 2n)tCY (2.37 2n)tCY Read data hold time low-level width tRDH tRDL1 (1.4 2n)tCY (1.37 2n)tCY tRDL2 (2.4 2n)tCY (2.37 2n)tCY WAIT input time from tRDWT1 tRDWT2 2tCY 2tCY WAIT input time from tWRWT 2tCY 2tCY WAIT low-level width Write data setup time tWTL tWDS 2n)tCY (2.4 2n)tCY (2.37 2n)tCY Write data hold time low-level width tWDH tWRL1 (2.4 2n)tCY (2.37 2n)tCY 2n)tCY MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Except when PCC2 PCC0 000B +85°C, (2/2)
Parameter delay time from ASTB Symbol Conditions MIN. 0.4tCY 0.37tCY delay time from ASTB tASTWR 1.4tCY 1.37tCY ASTB delay time from external fetch tRDAST Address hold time from external fetch tRDADH Write data output time from tRDWD 0.4tCY 0.37tCY Write data output time from tWRWD Address hold time from tWRADH delay time from WAIT tWTRD 0.6tCY 0.63tCY delay time from WAIT tWTWR 0.6tCY 0.63tCY 2.6tCY 2.63tCY 2.6tCY 2.63tCY MAX. Unit tASTRD
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Serial interface +85°C, Serial interface channel 3-wire serial mode (SCK0 Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions MIN. 1600 3200 SCK0 high-/low-level width tKH1, tKL1 setup time SCK0) tSIK1 tKCY1/2 tKCY1/2 hold time (from SCK0) output delay time from SCK0 tKSI1 tKSO1 100pFNote TYP. MAX. Unit
Note load capacitance output line. (ii) 3-wire serial mode (SCK0 External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions MIN. 1600 3200 SCK0 high-/low-level width tKH2, tKL2 1600 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time tSIK2 tKSI2 tKSO2 tR2, pFNote TYP. MAX. Unit
When using external device expansion function When using external device expansion function
1000
Note load capacitance output line.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
(iii) mode (SCK0 Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Conditions MIN. 3200 SCK0 high-/low-level width tKH3, tKL3 SB0, setup time SCK0) tSIK3 tKCY3/2 tKCY3/2 SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 pFNote tKCY3/2 tKCY3 tKCY3 tKCY3 tKCY3 1000 TYP. MAX. Unit
Note load resistance load capacitance SCK0, output lines. (iv) mode (SCK0 External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions MIN. 3200 SCK0 high-/low-level width tKH4, tKL4 SB0, setup time SCK0) tSIK4 1600 SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time tKSB tSBK tSBH tSBL tR4, When using external device expansion function When using external device expansion function 1000 tKSI4 tKSO4 pFNote tKCY4/2 tKCY4 tKCY4 tKCY4 tKCY4 1000 TYP. MAX. Unit
Note load resistance load capacitance output lines.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
2-wire serial mode (SCK0 Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 SCK0 high-level width tKH5 pFNote Conditions MIN. 1600 3200 tKCY5/2 tKCY5/2 SCK0 low-level width tKL5 tKCY5/2 tKCY5/2 SB0, setup time SCK0) tSIK5 SB0, hold time (from SCK0) SB0, output delay time from SCK0 tKSI5 tKSO5 TYP. MAX. Unit
Note load resistance load capacitance SCK0, output lines. (vi) 2-wire serial mode (SCK0 External clock input)
Parameter SCK0 cycle time Symbol tKCY6 Conditions MIN. 1600 3200 SCK0 high-level width tKH6 1300 SCK0 low-level width tKL6 1600 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time tR6, tSIK6 tKSI6 tKSO6 pFNote tKCY6/2 TYP. MAX. Unit
When using external device expansion function When using external device expansion function
1000
Note load resistance load capacitance output lines.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Serial interface channel 3-wire serial mode (SCK1 Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH7, tKL7 tSIK7 tKCY7/2 tKCY7/2 hold time (from SCK1) output delay time from SCK1 tKSI7 tKSO7 pFNote TYP. MAX. Unit
setup time SCK1)
Note load capacitance output line. (ii) 3-wire serial mode (SCK1 External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH8, tKL8 1600 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK8 tKSI8 tKSO8 tR8, pFNote 1000 TYP. MAX. Unit
When using external device expansion function When using external device expansion function
Note load capacitance output line.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
(iii) Automatic transmit/receive function 3-wire serial mode (SCK1 Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH9, tKL9 setup time SCK1) tSIK9 tKCY9/2 tKCY9/2 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tKSI9 tKSO9 tSBD tSBW pFNote tKCY9/2 tKCY9 tKCY9 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYS tKCY9/2 tKCY9 tKCY9 TYP. MAX. Unit
tBYH
2tKCY9
SCK1 from busy inactive
tSPS
Note
load capacitance output line. (iv) Automatic transmit/receive function 3-wire serial mode (SCK1 External clock input)
Parameter Symbol tKCY10 Conditions MIN. 1600 3200 TYP. MAX. Unit
SCK1 cycle time
SCK1 high-/low-level width
tKH10, tKL10
1600
setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time
tSIK10 tKSI10 tKSO10 tR10, tF10 pFNote
When using external device expansion function When using external device expansion function
1000
Note load capacitance output line.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Serial interface channel 3-wire serial mode (SCK2 Internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Conditions MIN. 1600 3200 SCK2 high-/low-level width tKH11, tKL11 setup time SCK2) tSIK11 tKCY11/2 tKCY11/2 hold time (from SCK2) output delay time from SCK2 tKSI11 tKSO11 pFNote TYP. MAX. Unit
Note load capacitance output line. (ii) 3-wire serial mode (SCK2 External clock input)
Parameter SCK2 cycle time Symbol tKCY12 Conditions MIN. 1600 3200 SCK2 high-/low-level width tKH12, tKL12 1600 setup time SCK2) hold time (from SCK2) output delay time from SCK2 SCK2 rise, fall time tSIK12 tKS1I2 tKSO12 tR12, tF12 pFNote TYP. MAX. Unit
When using external device expansion function When using external device expansion function
1000
Note load capacitance output line.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 78125 39063 19531 Unit
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY13 Conditions MIN. 1600 3200 ASCK high-/low-level width tKH13, tKL13 1600 Transfer rate 39063 19531 9766 ASCK rise, fall time tR13, tF13 when using external device expansion function 1000 TYP. MAX. Unit
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Timing Test Points (Excluding inputs)
Test Points
Clock Timing
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
Timing
1/fTI tTIL tTIH
TI00, TI01, TI1,
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Read/Write Operations External fetch wait):
Lower 8-bit address tADS tASTH ASTB tADH
Higher 8-bit address tADD1 Hi-Z Operation code tRDD1 tRDADH tRDAST
tASTRD tRDL1 tRDH
External fetch (wait insertion):
Lower 8-bit address ASTH ASTB
Higher 8-bit address
ADD1 Hi-Z RDD1 Operation code tRDADH tRDAST
ASTRD RDL1
WAIT RDWT1 tWTRD
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
External data access wait):
Lower 8-bit address tADS tASTH ASTB tADH tADD2 Hi-Z tRDD2
Higher 8-bit address
Read data
Hi-Z
Write data
Hi-Z
tRDH
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL1 tWDS tWDH WRADH
External data access (wait insertion):
Lower 8-bit address tADD2 tADS tASTH ASTB tASTRD tRDL2 tRDWD tWRWD tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL1 tWRADH tWDS tWDH tADH tRDD2 tRDH Hi-Z Read data Hi-Z Write data Higher 8-bit address Hi-Z
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Serial Transfer Timing 3-wire serial mode:
tKCYm
tKLm SCK0 SCK2 tSIKm tKSIm
tKHm
tKSOm
Input data
Output data
Remark
mode (bus release signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
mode (command signal transfer):
tKL3, SCK0 tKSB tSBK
tKCY3, tKH3,
tSIK3,
tKSI3,
SB0, tKSO3,
2-wire serial mode:
tKCY5, tKL5, SCK0 tSIK5, tKSO5, SB0, tKSI5, tKH5,
Automatic transmit/receive function 3-wire serial mode:
SIK9, KSO9,
KSI9, KH9,
SCK1 KL9, KCY9,
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Automatic transmit/receive function 3-wire serial mode (busy processing):
SCK1
9Note
10Note
10+n Note
BUSY (Active high)
Note signal actually driven here; shown such indicate timing.
UART mode (external clock input):
tKCY13 tKL13
tKH13
ASCK
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall errorNote AVREF0 AVDD Symbol Conditions MIN. TYP. MAX. 19.1 12/fXX AVSS AVREF0 AVDD Unit
µPD78P054 µPD78P058
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS
tCONV tSAMP VIAN AVREF0 RAIREF0
Note Excludes quantization error (±1/2LSB). Shown percentage full scale value. Remark fXX: Main system clock frequency fX/2) Main system clock oscillation frequency Converter Characteristics +85°C, AVSS
Parameter Resolution Overall error MNote MNote AVREF1 AVREF1 AVREF1 Output resistance Analog reference voltage AVREF1 current AVREF1 AIREF1 Note DACS0 DACS1 Symbol Conditions MIN. TYP. MAX. Unit
MNote Settling time pFNote
Notes load resistance load capacitance converter output pin. Value converter channel. Remark DACS0, DACS1: conversion value setting register
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR Subsystem clock unused (XT1 VDD), feedback resistor disconnected Release RESET Release interrupt request 217/fX Note Conditions MIN. TYP. MAX. Unit
Release signal time Oscillation stabilization wait time
tSREL tWAIT
Note Selection 212/fXX, 214/fXX through 217/fXX possible using bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS). Remark fXX: Main system clock frequency fX/2) Main system clock oscillation frequency Data Retention Timing (STOP mode release RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby release signal: STOP mode release interrupt request signal)
HALT mode STOP mode Operating mode
Data retention mode
STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Interrupt Request Input Timing
INTL INTP0 INTP6 INTH
RESET Input Timing
RESET
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Programming Characteristics Characteristics PROM write mode ±5°C, ±0.25 12.5 ±0.3
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Conditions MIN. 0.7VDD 12.8 6.75 TYP. MAX. 0.3VDD Unit
PROM read mode ±5°C, ±0.5 ±0.6
Parameter Input voltage, high Input voltage, Output voltage, high Symbol VOH1 VOH2 Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current SymbolNote VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, Conditions MIN. 0.7VDD TYP. MAX. 0.3VDD Unit
Note Corresponding symbols µPD27C1001A.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics PROM write mode Page program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time time setup time Input data setup time Address hold time (from Symbol SymbolNote tOES tCES tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching time hold time hold time tVPS tVDS tPGMS tCEH tOEH tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Byte program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time PGM) time setup time PGM) Input data setup time PGM) Address hold time (from Input data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time Symbol SymbolNote tOES tCES tVPS tVDS tOEH tOES tCES tVPS tVCS Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note Corresponding symbols µPD27C1001A.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM read mode ±5°C, ±0.5 ±0.6
Parameter Data output delay time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol tACC SymbolNote tACC Conditions MIN. TYP. MAX. Unit
Note Corresponding symbols µPD27C1001A. PROM programming mode setting 25°C,
Parameter PROM programming mode setup time Symbol tSMA Conditions MIN. TYP. MAX. Unit
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Write Mode Timing (Page program mode)
Page data latch
Page program
Program verify
Hi-Z Hi-Z tPGMS Data output Hi-Z tAHL tAHV
tVPS tVDS
Data input
tCES tOES tCEH
tOEH
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Write Mode Timing (Byte program mode)
Program Program Verify
Hi-Z tVDS tCES tOES tOEH tVPS Page Data input Data Latch Hi-Z Data output Hi-Z
Cautions should applied before removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP. PROM Read Mode Timing
Effective address
tACC
Note
Note
Note Data output Hi-Z
Hi-Z
Notes read within tACC range, make delay time from input fall maximum tACC tOE. time from when either first reaches VIH.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PROM Programming Mode Setting Timing
RESET
tSMA
Effective address
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CHARACTERISTICS CURVES (FOR REFERENCE ONLY)
Characteristics curves µPD78P054 (1/2) MHz, MHz)
25°C)
10.0
HALT oscillation, oscillation)
Supply current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply voltage
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics curves µPD78P054 (2/2) MHz)
25°C) HALT oscillation, oscillation)
10.0
Supply current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply voltage
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics curves µPD78P058 (1/2) MHz, MHz)
10.0 HALT oscillation, oscillation) 25°C)
Supply current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply voltage
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Characteristics curves µPD78P058 (2/2) MHz)
10.0 25°C) HALT oscillation, oscillation)
Supply current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply voltage
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
Remark dimensions materials products same those mass-production products.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
PLASTIC TQFP (FINE PITCH) (12x12)
detail lead
NOTE
ITEM MILLIMETERS 14.00±0.20 12.00±0.20 12.00±0.20 14.00±0.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.145 +0.055 -0.045 0.10 1.05±0.07 0.10±0.05 5°±5° 1.27 MAX. P80GK-50-BE9-6
Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
Remark dimensions materials products same those mass-production products.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CERAMIC WQFN
X80KW-65A-1 MILLIMETERS 14.0 13.6 13.6 14.0 1.84 MAX. 0.45 0.10 0.06 0.65 (T.P.) 0.15 0.825 0.825 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 0.012 0.032 0.032 0.079 0.354 0.083 0.030+0.006 -0.007 0.004
NOTE Each lead centerline located within 0.06 (0.003 inch) true position (T.P.) maximum material condition. ITEM
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, please contact your sales representative. Table 12-1. Surface Mount Type Soldering Conditions (1/2) µPD78P054GC-8BT 80-pin plastic resin thickness:
µPD78P058GC-8BT 80-pin plastic resin thickness:
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row)
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Table 12-1. Surface Mount Type Soldering Conditions (2/2) µPD78P054GK-BE9 80-pin plastic TQFP (fine pitch)
Soldering Method Soldering Conditions Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row) Recommended Condition Symbol IR35-107-3
Infrared reflow
VP15-107-3
Partial heating
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
APPENDIX DEVELOPMENT TOOLS
following support tools available system development using µPD78P054 78P058. Refer Cautions Using Development Tools. Language Processing Software
RA78K/0 CC78K/0 DF78054 CC78K/0-L Assembler package common 78K/0 Series compiler package common 78K/0 Series
µPD78054 Subseries device file
compiler library source file common 78K/0 Series
PROM Writing Tools
PG-1500 PA-78P054GC PA-78P054GK PA-78P054KK-T PG-1500 controller PROM programmer Programmer adapter connected PG-1500
PG-1500 control program
Debugging Tools When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PANote IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-780308-NS-EM1 NP-80GC NP-80GK EV-9200GC-80 TGK-080SDW ID78K0-NS SM78K0 DF78054 In-circuit emulator common 78K/0 Series Power supply unit IE-78K0-NS Performance board enhance expand function IE-78K0-NS Interface adapter when using PC-9800 Series (except notebook type computer) host machine supported) card interface cable when using notebook type computer host machine (PCMCIA socket supported) Interface adapter when using PC/ATor compatible host machine Adapter necessary when using computer including host machine Emulation board common µPD780308 Subseries Emulation probe 80-pin plastic (GC-8BT type) Emulation probe 80-pin plastic TQFP (GK-BE9 type) Conversion socket connect target system board which 80-pin plastic (GC-8BT type) mounted NP-80GC Conversion adapter connect target system board which 80-pin plastic TQFP (GK-BE9 type) mounted NP-80GK Integrated debugger IE-78K0-NS System simulator common 78K/0 Series Device file µPD78054 Subseries
Note Under development
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-780308-NS-EM1 IE-780308-R-EM IE-78K0-R-EX1 EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SDW ID78K0 SM78K0 DF78054 In-circuit emulator common 78K/0 Series Interface adapter when using PC-9800 Series (except notebook type computer) host machine supported) Interface adapter when using PC/AT compatible host machine (ISA supported) Adapter necessary when using computer including host machine Interface adapter cable when using host machine Emulation board common µPD780308 Subseries Emulation probe conversion board necessary when using IE-780308-NS-EM1 IE-78001-R-A Emulation probe 80-pin plastic (GC-8BT type) Emulation probe 80-pin plastic TQFP (GK-BE9 type) Conversion socket connect target system board which 80-pin plastic (GC-8BT type) mounted EP-78230GC-R Conversion adapter connect target system board which 80-pin plastic TQFP (GK-BE9 type) mounted EP-78054GK-R Integrated debugger IE-78001-R-A System simulator common 78K/0 Series Device file µPD78054 Subseries
Real-Time
RX78K/0 MX78K0 Real-time 78K/0 Series 78K/0 Series
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Cautions Using Development Tools ID78K0-NS, ID78K0, SM78K0 used combination with DF78054. CC78K/0 RX78K/0 used combination with RA78K/0 DF78054. NP-80GC NP-80GK products Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). Consult sales representative regarding purchase these products. TGK-080SDW product TOKYO ELETECH CORPORATION. Reference Daimaru Kogyo Corporation Tokyo electronic (TEL +81-3-3820-7112) Osaka electronic (TEL +81-6-6244-6672) third party development tools, refer 78K/0 Series Selection Guide (U11126E). host machines operating systems corresponding each software follows.
Host Machine [OS] Software RA78K/0 CC78K/0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0 PC-9800 Series [WindowsTM] PC/AT compatibles [Japanese/English Windows] Note Note Note Note Note HP9000 Series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note DOS-based software
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CONVERSION SOCKET (EV-9200GC-80) DRAWING FOOTPRINT Figure A-1. EV-9200GC-80 Drawing (For Reference Only)
EV-9200GC-80
No.1 index
EV-9200GC-80-G1E ITEM MILLIMETERS 18.0 14.4 14.4 18.0 16.0 18.7 16.0 18.7 0.35 INCHES 0.709 0.567 0.567 0.709 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091 0.059
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Figure A-2. EV-9200GC-80 Footprint (For Reference Only)
EV-9200GC-80-P1E ITEM Caution MILLIMETERS 19.7 15.0 0.65±0.02 19=12.35±0.05 INCHES 0.776 0.591 0.026+0.001 -0.002 0.748=0.486 +0.003 -0.002
0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 0.05 0.05 0.35 0.02 0.591 0.776 0.236+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
CONVERSION ADAPTER (TGK-080SDW) DRAWING Figure A-3. TGK-080SDW Drawing (For Reference Only)
ITEM MILLIMETERS 18.0 11.77 0.5x19=9.5 0.5x19=9.5 11.77 18.0 1.58 7.64 1.58 1.58 7.64 1.58 INCHES 0.709 0.463 0.020x0.748=0.374 0.020 0.020x0.748=0.374 0.463 0.709 0.020 0.062 0.047 0.301 0.047 0.062 0.062 0.047 0.301 0.047 0.062 ITEM MILLIMETERS 0.5x19=9.5±0.10 0.25 INCHES 0.020x0.748=0.374±0.004 0.010
screw
Protrusion places
3.55
1.85±0.2 0.25 14.0 1.4±0.2 1.4±0.2 h=1.8 0~5°
0.209 0.209 0.051 0.140 0.012
0.073±0.008 0.138 0.079 0.118 0.010 0.551 0.055±0.008 0.055±0.008 h=0.071 0.051 0.000~0.197° 0.232 0.031 0.094 0.106 0.154 TGK-080SDW-G1E
3.55
12.31 10.17 8.24 14.8 1.4±0.2
0.140
0.079 0.485 0.400 0.268 0.324 0.583 0.055±0.008
note: Product TOKYO ELETECH CORPORATION.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name Document (English) U11747E U12327E This document U12326E U10182E IEA-1289 Document (Japanese) U11747J U12327J U10417J U12326J U10904J U10903J U10102J U10182J U13482J
µPD78054, 78054Y Subseries User's Manual µPD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet µPD78P054, 78P058 Data Sheet
78K/0 Series User's Manual Instructions 78K/0 Series Instruction 78K/0 Series Instruction Table
µPD78054 Subseries Special Function Register Table
78K/0 Series Application Note Basic (III) Floating Point Arithmetic Programs
Documents Related Development Tools (User's Manuals)
Document Name Document (English) Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 Compiler Operation Language CC78K0 Compiler Application Note PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) based PG-1500 Controller Series DOSTM) based IE-78K0-NS IE-78001-R-EM IE-780308-NS-EM1 IE-780308-R-EM EP-78230 EP-78054GK-R SM78K0 System Simulator Windows based SM78K Series System Simulator Reference External Part User Open Interface Specifications ID78K0-NS Integrated Debugger Windows based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger Windows based Reference Reference Reference Guide U12900E U11539E U11649E U12900J U11151J U11539J U11649J Programming Know-how U11802E U11801E U11789E EEU-1402 U11517E U11518E U13034E U11940E EEU-1291 U10540E prepared prepared prepared U11362E EEU-1515 EEU-1468 U10181E U10092E Document (Japanese) U11802J U11801J U11789J U12323J U11517J U11518J U13034J U11940J EEU-704 EEU-5008 prepared prepared prepared U11362J EEU-985 EEU-932 U10181J U10092J
RA78K0 Assembler Package
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Documents Related Embedded Software (User's Manuals)
Document Name Document (English) Basics Installation 78K/0 Series MX78K0 Basics U11537E U11536E U12257E Document (Japanese) U11537J U11536J U12257J
78K/0 Series Real-time
Other Related Documents
Document Name Document (English) X13769X C10535E C11531E C10983E C11892E C10535J C11531J C10983J C11892J U11416J Document (Japanese)
SEMICONDUCTORS SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Microcomputer Product Series Guide
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
[MEMO]
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U10417EJ3V0DS00
µPD78P054, 78P058
FIP, IEBus, QTOP trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademarks International Business Machines Corporation. HP9000 Series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative. License needed:
µPD78P054KK-T, 78P058KK-T µPD78P058GC-8BT
customer must judge need license: µPD78P054GC-8BT, 78P054GK-BE9
information this document subject change without notice. Before using this document, please confirm that this latest version. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.
98.8

µPD78P054, 78P058 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPT

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