Microcomputer ADSP-21161N Integrated peripherals-integrated proce
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Preliminary Technical DatSUMMARY High performance 32-bit DSP-applications audio, medical, military, wireless communications, graphics, imaging, motor-control, telephony Super Harvard Architecture-four independent buses dual data fetch, instruction fetch, nonintrusive, zero-overhead Code-compatible with other SHARC Family DSPs (SIMD) computational architecture-two 32-bit IEEE floating-point computation units, each with multiplier, ALU, shifter, register file Serial ports offer support programmable simultaneous receive transmit pins, which supports transmit receive channels audio
Microcomputer ADSP-21161N
Integrated peripherals-integrated processor, Mbit on-chip dual-ported SRAM, SDRAM controller, glueless multiprocessing features, ports (serial, link, external bus, SPI, JTAG) ADSP-21161N supports 32-bit fixed, 32-bit float, 40-bit floating point formats FEATURES core instruction rate Single-cycle instruction execution, including SIMD operations both computational units MFLOPS peak MFLOPs sustained performance 225-ball 17x17mm MBGA package Mbit on-chip dual-ported SRAM (0.5 Mbit block Mbit block independent access core processor
ADSP-21161N Functional Block Diagram
CORE PROCESSOR
ADDR ADDR
DUAL-PORTED SRAM
BLOCK
BLOCK
DATA DATA
FLAGS
DATA DATA ADDR
ADDR
SDRA
DAG2
EXTERNAL PORT
ADDR MULTIPROCESSOR INTERFACE DATA
DATA
MULT
DATA FILE
BARREL
40-B
REGISTERS (MEMORY MAPPED) DATA BUFFERS
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This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing. Technology Way, .O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 World Wide Site: http://www.analog.com Fax:781/326-8703 ©Analog Devices,Inc., 2001
PRELIMINARY TECHNICAL DATA ADSP-21161N
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September 2001
FEATURES (CONTINUED) million fixed-point MACs sustained performance Dual Data Address Generators (DAGs) with modulo bit-reverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing IEEE 1149.1 JTAG standard test access port on-chip emulation Single Instruction Multiple Data (SIMD) architecture provides: computational processing elements Concurrent execution-Each processing element executes same instruction, operates different data Code compatibility-At assembly level, uses same instruction other SHARC DSPs Parallelism busses computational units allows: Single-cycle execution (with without SIMD) multiply operation, operation, dual memory read write, instruction fetch Transfers between memory core four 32-bit floating- fixed-point words cycle, sustained Gbytes/s bandwidth Accelerated butterfly computation through multiply with subtract Controller supports: zero-overhead channels transfers between ADSP-21161N internal memory external memory, external peripherals, host processor, serial ports, link ports Serial Peripheral Interface (SPI-compatible) 64-bit background transfers core clock speed, parallel with full-speed processor execution Mbytes/s transfer rate over Host processor interface 32-bit microprocessors, host directly read/write ADSP-21161N registers. 32-bit 48-bit) wide synchronous External Port provides: Glueless connection asynchronous, SBSRAM SDRAM external memories Memory interface supports programmable wait state generation wait mode off-chip memory operation non-SDRAM accesses 1:2, 1:3, 1:4, 1:6, clock Core Clock frequency multiply ratios 24-bit address, 32-bit data bus. additional data lines multiplexed link port data pins allow complete 48-bit wide data single-cycle external instruction execution Direct reads writes registers from host other 21161N DSPs 62.7 Mega-word address range off-chip SRAM SBSRAM memories 32-48, 16-48, 8-48 execution packing executing instruction directly from 32-bit, 16-bit, 8-bit wide external memories
32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, data packing transfers directly from 32-bit, 16-bit, 8-bit wide external memories from internal 32-, 48-, 64-bit internal memory configured have 48-bit wide external data possible, link ports used. link port data lines multiplexed with data lines enabled through control bits SYSCON SDRAM Controller glueless interface cost external memory Zero wait state, operation most accesses Extended external memory banks M-words) SDRAM accesses Page sizes 2048 words SDRAM controller supports SDRAM memory banks Support interface core clock half core clock frequency Support Mbits, Mbits, Mbits, Mbits with SDRAM data configurations x16, Mega-word address range off-chip SDRAM memory Multiprocessing support provides: Glueless connection scalable multiprocessing architecture Distributed on-chip arbitration parallel connect ADSP-21161Ns, global memory host 8-bit wide link ports point-to-point connectivity between ADSP-21161Ns Mbytes/s transfer rate over parallel Mbytes/s transfer rate over link ports Serial Ports provide: Four Mbit/s synchronous serial ports with companding hardware bi-directional serial data pins, configurable either transmitter receiver Support, programmable direction simultaneous Receive Transmit channels, either Transmit channels Receive channels. support interfaces, channel support newer telephony interfaces such H.100/H.110 Companding selection channel basis mode Serial Peripheral Interface (SPI) Slave Serial boot through from Master device Full-duplex operation Master-Slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities phases Programmable pins Programmable Timer
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GENERAL DESCRIPTION
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ADSP-21161N
ADSP-21161N SHARC first low-cost derivative ADSP-21160 featuring Analog Devices' Super Harvard Architecture. Easing portability, ADSP-21161N source code compatible with ADSP-21160 with first generation ADSP-2106x SHARCs SISD (Single Instruction, Single Data) mode. Like other SHARCs, ADSP-21161N 32-bit processor that optimized high performance applications. ADSP-21161N includes core, dual-ported on-chip SRAM, integrated processor with multiprocessing support, multiple internal busses eliminate bottlenecks. ADSP-21161N offers (SIMD) architecture, which first offered ADSP-21160. Using computational units (ADSP-2106x SHARCs have one), ADSP-21161N double cycle performance versus ADSP-2106x range algorithms. Fabricated state art, high speed, power CMOS process, ADSP-21161N instruction cycle time. With SIMD computational hardware running MHz, ADSP-21161N perform million math operations second. Table shows performance benchmarks ADSP-21161N.
Table ADSP-21161N Benchmarks MHz) Benchmark Algorithm Speed MHz)
block diagram ADSP-21161N page illustrating following architectural features: processing elements, each made ALU, Multiplier, Shifter Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle Interval timer On-Chip SRAM Mbit) SDRAM Controller glueless interface SDRAMs External port that supports: Interfacing off-chip memory peripherals Glueless multiprocessing support ADSP-21161N SHARCs Host port read/write registers controller Four serial ports link ports SPI-compatible interface JTAG test access port General Purpose Pins Figure shows typical single-processor system. multi-processing system appears Figure page
ADSP-21161N Family Core Architecture
1024 Point Complex (Radix with reversal) Filter (per tap) Filter (per biquad) Matrix Multiply (pipelined) [3x3] [3x1] [4x4] [4x1] Divide (y/x) Inverse Square Root
ADSP-21161N includes following architectural features ADSP-2100 family core. ADSP-21161N code compatible assembly level with ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062 ADSP-21065L.
SIMD Computational Engine
ADSP-21161N continues SHARC's industry leading standards integration DSPs, combining high performance 32-bit core with integrated, on-chip system features. These features include Mbit dual ported SRAM memory, host processor interface, processor that supports channels, four serial ports, link ports, SDRAM controller, interface, external parallel bus, glueless multiprocessing.
ADSP-21161N contains computational processing elements that operate Single Instruction Multiple Data (SIMD) engine. processing elements referred each contains ALU, multiplier, shifter register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math intensive algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory
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This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21161N
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September 2001
CLKD
ADDR
EPROM
BRST
ADDR
SDRA
ADDR CESSO
DEVICE (OPTIONAL)
SPIC
REDY
ADDR
Figure ADSP-21161N System
processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file.
Independent, Parallel Computation Units
Data Register File
Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier shifter. These units perform single-cycle instructions. three units within each processing element arranged parallel, maximizing computational throughput. Single multi-function instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, 32-bit fixed-point data formats.
general purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-21100 enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Single-Cycle Fetch Instruction Four Operands
ADSP-21161N features enhanced Harvard architecture which data memory (DM) transfers data program memory (PM) transfers both instructions data (see Figure page With ADSP-21161N's separate program data memory buses on-chip instruction cache, processor simultaneously fetch four operands (two over each data bus) instruction (from cache), single cycle.
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Instruction Cache
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ADSP-21161N
ADSP-21161N includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache allows full-speed execution core, looped operations such digital filter multiply-accumulates butterfly processing.
Data Address Generators With Hardware Circular Buffers
bus, with dedicated each memory block assures single-cycle execution with data transfers. this case, instruction must available cache.
Off-Chip Memory Peripherals Interface
ADSP-21161N's data address generators (DAGs) used indirect addressing implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital signal processing, commonly used digital filters Fourier transforms. DAGs ADSP-21161N contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, simplify implementation. Circular buffers start memory location.
Flexible Instruction
ADSP-21161N's external port provides processor's interface off-chip memory peripherals. 62.7-megaword off-chip address space (254-megaword SDRAM) included ADSP-21161N's unified address space. separate on-chip buses-for addresses, data, addresses, data, addresses, data-are multiplexed external port create external system with single 24-bit address single 32-bit data bus. Every access external memory based address that fetches 32-bit word. When fetching instruction from external memory, 32-bit data locations being accessed packed instructions. Unused link port lines also used additional data lines DATA[0]-DATA[15], allowing single cycle execution instructions from external memory MHz. Figure page shows alignment various accesses external memory. external port supports asynchronous, synchronous, synchronous burst accesses. Synchronous burst SRAM interfaced gluelessly. ADSP-21161N also interface gluelessly SDRAM. Addressing external memory devices facilitated on-chip decoding high-order address lines generate memory bank select signals. Separate control lines also generated simplified addressing page-mode DRAM. ADSP-21161N provides programmable memory wait states external memory acknowledge controls allow interfacing memory peripherals with variable access, hold, disable time requirements.
SDRAM Interface
48-bit instruction word accommodates variety parallel operations, concise programming. example, ADSP-21161N conditionally execute multiply, add, subtract both processing elements, while branching, single instruction.
ADSP-21161N Memory Interface Features
ADSP-21161N adds following architectural features ADSP-2100 family core:
Dual-Ported On-Chip Memory
ADSP-21161N contains megabit on-chip SRAM, organized blocks Mbits. Each block configured different combinations code data storage. Each memory block dual-ported single-cycle, independent accesses core processor processor. dual-ported memory combination with three separate on-chip buses allow data transfers from core from processor, single cycle. ADSP-21161N, memory configured maximum words 32-bit data, words 16-bit data, 21.25K words 48-bit instructions 40-bit data), combinations different word sizes megabit. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion between 32-bit floating-point 16-bit floating-point formats done single instruction. While each memory block store combinations code data, accesses most efficient when block stores data using transfers, other block stores instructions data using transfers. Using REV.
SDRAM interface enables ADSP-21161N transfer data from synchronous DRAM (SDRAM) core clock frequency one-half core clock frequency. synchronous approach, coupled with core clock frequency, supports data transfer high throughput-up Mbytes/s. 32-bit transfers Mbytes/s. 48-bit transfers. SDRAM interface provides glueless interface with standard SDRAMs-16 Mb-and includes options support additional buffers between ADSP-21161N SDRAM. SDRAM interface extremely flexible provides capability connecting SDRAMs ADSP-21161N's four external memory banks, with four banks mapped SDRAM. Systems with several SDRAM devices connected parallel require buffering meet overall system timing requirements. ADSP-21161N supports pipelining address control signals enable such buffering between itself multiple SDRAM devices.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21161N
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September 2001
FFFF 7FFF FFFF on-S FFFF
Inte Space
Long Norm Word dress Word ressin
Bank
FFFF
FFFF
Bank
ultipro
FFFF
FFFF on-S FFFF
FFFF
FFFF
Bank
FFFF on-S FFFF
FFFF FFFF
Exte rnal
Bank
FFFF on-S FFFF
Figure ADSP-21161N Memory Target Board JTAG Emulator Connector Controller
Analog Devices Tools product line JTAG emulators uses IEEE 1149.1 JTAG test access port ADSP-21161N processor monitor control target board processor during emulation. Analog Devices Tools product line JTAG emulators provides emulation full processor speed, allowing inspection modification memory, registers, processor stacks. processor's JTAG interface ensures that emulator will affect target system loading timing. complete information SHARC Analog Devices Tools product line JTAG emulator operation, appropriate Emulator Hardware User's Guide". detailed information interfacing Analog Devices JTAG emulators with Analog Devices products with JTAG emulation ports, please refer Engineer Engineer Note EE-68, "Analog Devices JTAG Emulation Technical Reference". Both these documents found Analog Devices web-site:
ADSP-21161N's on-chip controller allows zero-overhead data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21161N's internal memory external memory, external peripherals, host processor. transfers also occur between ADSP-21161N's internal memory serial ports, link ports, Serial Peripheral Interface (SPI)-compatible port. External packing unpacking 16-, 32-, 48-, 64-bit words internal memory performed during transfers from either 16-, 32-bit wide external memory. Fourteen channels available ADSP-21161N-two shared between interface link ports, eight serial ports, four processor's external port (for either host processor, other ADSP-21161Ns, memory transfers). Programs downloaded ADSP-21161N using transfers. Asynchronous off-chip peripherals control channels using Request/Grant lines (DMAR1-2, DMAG1-2). Other REV.
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ADSP-21161N
features include interrupt generation upon completion transfers, chaining automatic linked transfers.
throughput interprocessor communications over links Mbytes second. link ports cluster multiprocessing used concurrently independently.
L1DATA[7:0] L0DATA[7:0] DATA 15-8 DATA
Link Ports
DATA 47-16
DATA 15-0
PROM BOOT 8-bit Packed Data 8-bit Packed Instruction Execution 16-bit Packed Data 16-bit Packed Instruction Execution Float Fixed, D31-D0, 32-bit Packed 32-bit Packed Instruction 48-bit Instruction Fetch Packing) Extra Data Lines DATA[15-0] Only Accessible Link Ports Disabled. Enable These Additional Data Lines setting IPACK[1:0] SYSCON.
ADSP-21161N features 8-bit link ports that provide additional capabilities. With capability running MHz, each link port support Mbytes/s. Link port especially useful point-to-point interprocessor communication multiprocessing systems. link ports operate independently simultaneously, with maximum data throughput Mbytes/s. Link port data packed into 32-bit words directly read core processor DMA-transferred on-chip memory. Each link port double-buffered input output registers. Clock/acknowledge handshaking controls link port transfers. Transfers programmable either transmit receive.
Serial Ports
ADSP-21161N features four synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices. Each serial port made data lines, clock frame sync. data lines programmed either transmit receive. serial ports operate half clock rate core, providing each with maximum data rate Mbit/s. serial data pins programmable either transmitter receiver, providing greater flexibility serial communications. Serial port data automatically transferred from on-chip memory dedicated DMA. Each serial ports features Time Division Multiplex (TDM) multichannel mode, where serial ports transmitters serial ports receivers (SPORT0 paired with SPORT2 SPORT1 paired with SPORT3 TX). Each serial ports also support protocol industry standard interface commonly used audio codecs, ADCs DACs), with data pins, allowing four channels (using stereo devices) serial port, with maximum channels. serial ports permit little-endian big-endian transmission formats word lengths selectable from bits bits. mode, data-word lengths selectable between bits bits. Serial ports offer selectable synchronization transmit modes well optional µ-law A-law companding. Serial port clocks frame syncs internally externally generated.
Serial Peripheral (Compatible) Interface
Figure ADSP-21161N External Data Alignment Options Multiprocessing
ADSP-21161N offers powerful features tailored multi-processing systems. external port link ports provide integrated glueless multiprocessing support. external port supports unified address space (see Figure page that allows direct interprocessor accesses each ADSP-21161N's internal memory-mapped (I/O processor) registers. other internal memory indirectly accessed transfers initiated programming parameter control registers. Distributed arbitration logic included on-chip simple, glueless connection systems containing ADSP-21161Ns host processor. Master processor change over incurs only cycle overhead. arbitration selectable either fixed rotating priority. lock allows indivisible read-modify-write sequences semaphores. vector interrupt provided interprocessor commands. Maximum throughput interprocessor data transfer Mbytes/s over external port. link ports provide second method multiprocessing communications. Each link port support communications another ADSP-21161N. ADSP-21161N running maximum REV.
Serial Peripheral Interface (SPI) industry standard synchronous serial link, enabling ADSP-21161N SPI-compatible port communicate with other SPI-compatible devices. 4-wire interface consisting data pins, device select pin, clock pin.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21161N
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September 2001
P-2116
P-2116 P-2116
P-2116
HOST
SDCLK[1-0] SDCKE
SDA10
Figure ADSP-21161N Shared Memory Multiprocessing System
full-duplex synchronous serial interface, supporting both master slave modes. port operate multi-master environment interfacing with four
other SPI-compatible devices, either acting master slave device. ADSP-21161N SPI-compatible peripheral implementation also features programmable baud rate REV.
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PRELIMINARY TECHNICAL DATA September 2001
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ADSP-21161N
clock phase/polarities. ADSP-21161N SPI-compatible port uses open drain drivers support multi-master configuration avoid data contention.
Host Processor Interface
ADSP-21161N host interface allows easy connection standard 8-bit, 16-bit, 32-bit microprocessor buses with little additional hardware required. host interface accessed through ADSP-21161N's external port. Four channels available host interface; code data transfers accomplished with software overhead. host processor requests ADSP-21161N's external with host request (HBR), host grant (HBG), ready (REDY) signals. host directly read write internal registers ADSP-21161N, access channel setup message registers. setup host would allow access internal memory address transfers. Vector interrupt support provides efficient execution host commands.
General Purpose Ports
Note that analog supply (AVDD) powers ADSP-21161N's clock generator PLL. produce stable clock, provide external circuit filter power input AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AGND) signal install decoupling capacitor close possible pin.
VDDINT 0.01 AVDD
AGND
Figure Analog Power (AVDD) Filter Circuit Development Tools
ADSP-21161N also contains twelve programmable, general purpose pins that function either input output. output, these pins signal peripheral devices; input, these pins provide test conditional branching.
Program Booting
ADSP-21161N supported with complete software hardware development tools, including Analog Devices' emulators VisualDSP++1 development environment. same emulator hardware that supports other ADSP-21xxx DSPs, also fully emulates ADSP-21161N. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler that based algebraic syntax; archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. points these tools are: Compiled ADSP-21161N C/C++ code efficiency-the compiler been developed efficient translation C/C++ code ADSP-21161N assembly. architectural features that improve efficiency compiled C/C++ code. ADSP-2106x family code compatibility-The assembler legacy features ease conversion existing ADSP-2106x applications ADSP-21161N. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert break points conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory
internal memory ADSP-21161N booted system power-up from either 8-bit EPROM, host processor, interface, through link ports. Selection boot source controlled Boot Memory Select (BMS), EBOOT (EPROM Boot), Link/Host Boot (LBOOT) pins. 16-, 32-bit host processors also used booting.
Phased Locked Loop Crystal Double Enable
ADSP-21161N uses on-chip Phase Locked Loop (PLL) generate internal clock core. CLK_CFG[1:0] pins used select ratios 2:1, 3:1, 4:1. addition ratios, CLKDBL used more clock ratio options. (1x/2x CLKIN) rate CLKDBL determines rate input clock rate which synchronous external port operates. With combination CLK_CFG[1:0] CLKDBL, ratios 2:1, 3:1, 4:1, 6:1, between core CLKIN supported. also Figure page
Power Supplies
ADSP-21161N separate power supply connections internal (VDDINT), external (VDDEXT), analog (AVDD/AGND) power supplies. internal analog supplies must meet 1.8V requirement. external supply must meet 3.3V requirement. external supply pins must connected same supply.
1VisualDSP++
registered trademark Analog Devices, Inc.
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Source level debugging Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage ADSP-21xxx development tools, including syntax highlighting VisualDSP++ editor. This capability permits: Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. Analog Devices' emulators IEEE 1149.1 JTAG test access port ADSP-21161N processor monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting ADSP-21xxx processor family. Hardware tools include ADSP-21xxx plug-in cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
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September 2001
Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector.
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
White Mountain (Product Line Analog Devices, Inc.) family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices' JTAG emulation header custom target board.
Target Board Header
seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used board-level (boundary scan) testing. When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
JTAG Emulator Connector
emulator interface Analog Devices' JTAG 14-pin header, shown Figure customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board.
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area allows connector properly seat onto target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.25" square post pin.
Design-for-Emulation Circuit Information
details target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website-use site search
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ADSP-21161N
FUNCTION DESCRIPTIONS
ADSP-21161N definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TMS, TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST).Tie pull unused inputs VDDEXT GND, except following: ADDR23-0, DATA47-16, BRST, CLKOUT (NOTE: These pins have logic-level hold circuit enabled ADSP-21161N with 00x) ACK, DMARx, DMAGx, (ID2-0 00x) (NOTE: These pins have pull-up enabled ADSP-21161N with 00x) LxCLK, LxACK, LxDAT7-0 (LxPDRDE (NOTE: Link Port Buffer Control Register definitions ADSP-21161 SHARC Hardware Reference). DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU, TMS,TRST, (NOTE: These pins have pull-up.) following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State (when SBTS asserted when ADSP-21161N slave).
VIEW
Figure JTAG Target Board Connector with Local Boundary Scan
0.64"
0.24" 0.88"
Figure JTAG Connector Dimensions
0.10"
0.15"
Unlike previous SHARC processors, ADSP-21161N contains internal series resistance equivalent input drivers except CLKIN XTAL pins. Therefore, traces longer than inches, external series resisters control, data, clock frame sync pins required dampen reflections from transmission line effects point-to-point connections. However, more complex networks such star configuration, series termination still recommended. Note that protection feedback path only found pins that bidirectional (I/O, I/O/T). Pins listed type include this signal feedback path.
Figure JTAG Connector Keep-Out
"EE-68" (www.analog.com). This document updated regularly keep pace with improvements emulator support.
Additional Information
This data sheet provides general overview ADSP-21161N architecture functionality. detailed information ADSP-2116x Family core architecture instruction set, refer ADSP-21161 Sharc Hardware Reference 21160 Sharc Instruction Reference.
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PRELIMINARY TECHNICAL DATA ADSP-21161N
Table Descriptions Type Function
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September 2001
ADDR23-0
I/O/T
External Address. ADSP-21161N outputs addresses external memory peripherals these pins. multiprocessor system master outputs addresses read/writes registers other ADSP-21161Ns while other internal memory resources accessed indirectly control (that accessing parameter registers). ADSP-21161N inputs addresses when host processor multiprocessing master reading writing registers. keeper latch DSP's ADDR23-0 pins maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. External Data. ADSP-21161N inputs outputs data instructions these pins. Pull-up resistors unused data pins necessary. keeper latch DSP's DATA47-16 pins maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. Note: DATA[15:8] pins (multiplexed with L1DATA[7:0]) also used extend data link ports disabled will used. addition, DATA[7:0] pins (multiplexed with L0DATA[7:0]) also used extend data link ports used. This allows execution 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) SDRAM (core clock one-half core clock speed). IPACKx Instruction Packing Mode Bits SYSCON should correctly (IPACK1-0 0x1) enable this full instruction Width/No-packing Mode operation. Memory Select Lines. These outputs asserted (low) chip selects corresponding banks external memory. Memory bank sizes fixed Mwords non-SDRAM Mwords SDRAM. MS3-0 outputs decoded memory address lines. asynchronous access mode, MS3-0 outputs transition with other address outputs. synchronous access modes, MS3-0 outputs assert with other address lines; however, they de-assert after first CLKIN cycle which sampled asserted. multiprocessor systems, signals tracked slave SHARCs. Memory Read Strobe. asserted whenever ADSP-21161N reads word from external memory from registers other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert reading from word ADSP-21161N register memory. multiprocessing system, driven master. internal pull-up resistor that enabled DSPs with ID2-0 00x. Memory Write Strobe. asserted when ADSP-21161N writes word external memory registers other ADSP-21161Ns. External devices must assert writing ADSP-21161N's registers. multiprocessing system, driven master. internal pull-up resistor that enabled DSPs with ID2-0 00x.
DATA47-16
I/O/T
MS3-0
I/O/T
I/O/T
I/O/T
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Table Descriptions (Continued) Function
BRST
I/O/T
Sequential Burst Access. BRST asserted ADSP-21161N indicate that data associated with consecutive addresses being read written. slave device samples initial address increments internal address counter after each transfer. incremented address pipelined bus. master ADSP-21161N multiprocessor environment read slave external port buffers (EPBx) using burst protocol. BRST asserted after initial access burst transfer. asserted every cycle after that, except last data request cycle (denoted asserted BRST negated). keeper latch DSP's BRST maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. Memory Acknowledge. External devices de-assert (low) wait states external memory access. used devices, memory controllers, other peripherals hold completion external memory access. ADSP-21161N deasserts output wait states synchronous access registers. internal pull-up resistor that enabled during reset DSPs with ID2-0 00x. Suspend Three-State. External devices assert SBTS (low) place external address, data, selects, strobes high impedance state following cycle. ADSP-21161N attempts access external memory while SBTS asserted, processor will halt memory access will completed until SBTS de-asserted. SBTS should only used recover from host processor/ADSP-21161N deadlock. SDRAM Column Access Strobe. conjunction with RAS, MSx, SDWE, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Access Strobe. conjunction with CAS, MSx, SDWE, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Write Enable. conjunction with CAS, RAS, MSx, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Data Mask. write mode, latency zero used during precharge command during SDRAM power-up initialization. SDRAM Clock Output Clock SDRAM devices. SDRAM Clock Output Additional clock SDRAM devices. systems with multiple SDRAM devices, handles increased clock load requirements, eliminating need off-chip clock buffers. Either SDCLK1 both SDCLKx pins three-stated. SDRAM Clock Enable. Enables disables signal. details, data sheet supplied with SDRAM device. SDRAM Pin. Enables applications refresh SDRAM parallel with non-SDRAM accesses host accesses. Interrupt Request Lines. These sampled rising edge CLKIN either edge-triggered level-sensitive.
I/O/S
SBTS
I/O/T
I/O/T
SDWE SDCLK0 SDCLK1
I/O/T I/O/S/T O/S/T
SDCKE SDA10 IRQ2-0
I/O/T
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Table Descriptions (Continued) Function
FLAG11-0
I/O/A
Flag Pins. Each configured control bits either input output. input, tested condition. output, used signal external peripherals. Timer Expired. Asserted four CLKIN cycles when timer enabled TCOUNT decrements zero. Host Request. Must asserted host processor request control ADSP-21161N's external bus. When asserted multiprocessing system, ADSP-21161N that master will relinquish assert HBG. relinquish bus, ADSP-21161N places address, data, select, strobe lines high impedance state. priority over ADSP-21161N requests (BR6-1) multiprocessing system. Host Grant. Acknowledges request, indicating that host processor take control external bus. asserted (held low) ADSP-21161N until released. multiprocessing system, output ADSP-21161N master monitored others. Chip Select. Asserted host processor select ADSP-21161N. Host Acknowledge. ADSP-21161N de-asserts REDY (low) waitstates host access registers when inputs asserted. Request (DMA Channel 11). Asserted external port devices request services. DMAR1 internal pull-up resistor that enabled DSPs with ID2-0 00x. Request (DMA Channel 12). Asserted external port devices request services. DMAR2 internal pull-up resistor that enabled DSPs with ID2-0 00x. Grant (DMA Channel 11). Asserted ADSP-21161N indicate that requested starts next cycle. Driven master only. DMAG1 internal pull-up resistor that enabled DSPs with ID2-0 00x. Grant (DMA Channel 12). Asserted ADSP-21161N indicate that requested starts next cycle. Driven master only. DMAG2 internal pull-up resistor that enabled DSPs with ID2-0 00x. Multiprocessing Requests. Used multiprocessing ADSP-21161Ns arbitrate mastership. ADSP-21161N only drives line (corresponding value ID2-0 inputs) monitors others. multiprocessor system with less than ADSP-21161Ns, unused pins should pulled high; processor's line must pulled high because output. Master Output. multiprocessor system, indicates whether ADSP-21161N current master shared external bus. ADSP-21161N drives BMSTR high only while master. single-processor system 000), processor drives this high.
TIMEXP
REDY DMAR1
(O/D)
DMAR2
DMAG1
DMAG2
BR6-1
I/O/S
BMSTR
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Table Descriptions (Continued) Function
ID2-0
Multiprocessing Determines which multiprocessing request (BR1 BR6) used ADSP-21161N. corresponds BR1, corresponds BR2, single-processor systems. These lines system configuration selection that should hardwired only changed reset. Rotating Priority Arbitration Select. When RPBA high, rotating priority multiprocessor arbitration selected. When RPBA low, fixed priority selected. This signal system configuration selection that must same value every ADSP-21161N. value RPBA changed during system operation, must changed same CLKIN cycle every ADSP-21161N. Priority Access. Asserting allows ADSP-21161N slave interrupt background transfers gain access external bus. connected ADSP-21161Ns system. access priority required system, should left unconnected. internal pull-up resistor that enabled DSPs with ID2-0 00x. Data Transmit Receive Channel (Serial Ports Each internal pull-up resistor. Bidirectional data pin. This signal configured output transmit serial data, input receive serial data. Data Transmit Receive Channel (Serial Ports Each internal pull-up resistor. Bidirectional data pin. This signal configured output transmit serial data, input receive serial data. Transmit/Receive Serial Clock (Serial Ports Each SCLK internal pull-up resistor. This signal either internally externally generated. Transmit Receive Frame Sync (Serial Ports frame sync pulse initiates shifting serial data. This signal either generated internally externally. active high early late frame sync, reference shifting serial data. Serial Peripheral Interface Clock Signal. Driven master, this signal controls rate which data transferred. master transmit data variety baud rates. SPICLK cycles once each transmitted. SPICLK gated clock that active during data transfers, only length transferred word. Slave devices ignore serial clock slave select input driven inactive (HIGH). SPICLK used shift shift data driven MISO MOSI lines. data always shifted clock edge clock sampled opposite edge clock. Clock polarity clock phase relative data programmable into SPICTL control register define transfer format. SPICLK internal pull-up resistor.
RPBA
I/O/T
SCLKx
SPICLK
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Table Descriptions (Continued) Function
SPIDS
Serial Peripheral Interface Slave Device Select. active signal used enable slave devices. This input signal behaves like chip select, provided master device slave devices. multi-master mode SPIDS signal asserted master device signal that error occurred, some other device also trying master device. asserted when device master mode, considered multi-master error. Single-Master, Multiple-Slave configuration where FLAG3-0 used, this must tied high VDDINT. ADSP-21161N ADSP-21161N interaction, master ADSP-21161N's FLAG3-0 pins used drive SPIDS signal ADSP-21161N slave device. Master Slave. ADSP-21161N configured master, MOSI becomes data transmit (output) pin, transmitting output data. ADSP-21161N configured slave, MOSI becomes data receive (input) pin, receiving input data. ADSP-21161N interconnection, data shifted from MOSI output master shifted into MOSI input(s) slave(s). MOSI internal pull-up resistor. Master Slave Out. ADSP-21161N configured master, MISO becomes data receive (input) pin, receiving input data. ADSP-21161N configured slave, MISO becomes data transmit (output) pin, transmitting output data. ADSP-21161N interconnection, data shifted from MISO output slave shifted into MISO input master. MISO internal pull-up resistor. MISO configured setting SPICTL register. Note: Only slave allowed transmit data given time. Link Port Data (Link Ports 0-1). Each LxDAT internal pull-down resistor that enabled disabled LxPDRDE LCTL register. Note: L1DATA[7:0] multiplexed with DATA[15:8] pins L0DATA[7:0] multiplexed with DATA[7:0] pins. link ports disabled used, then these pins used additional data lines executing instructions full clock rate from external memory. DATA47:16 more information. Link Port Clock (Link Ports 0-1). Each LxCLK internal pull-down resistor that enabled disabled LxPDRDE LCTL register. Link Port Acknowledge (Link Ports 0-1). Each LxACK internal pull-down resistor that enabled disabled LxPDRDE LCTL register. EPROM Boot Select. description this operates, table description. This signal system configuration selection that should hardwired. Link Boot. description this operates, table description. This signal system configuration selection that should hardwired. Boot Memory Select. Serves output input selected with EBOOT LBOOT pins; table below. This input system configuration selection that should hardwired. Host PROM boot, channel (EPB0) used. Link boot boot, channel used. Three-state only EPROM boot mode (when output).
MOSI
(o/d)
MISO
(o/d)
LxDAT7-0 [DATA15-0]
[I/O/T]
LxCLK LxACK
EBOOT
LBOOT
I/O/T
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Table Descriptions (Continued) Function
CLKIN
Local Clock Used conjunction with XTAL. CLKIN ADSP-21161N clock input. configures ADSP-21161N either internal clock generator external clock source. Connecting necessary components CLKIN XTAL enables internal clock generator. Connecting external clock CLKIN while leaving XTAL unconnected configures ADSP-21161N external clock source such external clock oscillator.The ADSP-21161N external port cycles frequency CLKIN. instruction cycle rate multiple CLKIN frequency; programmable power-up CLK_CFG1-0 pins. CLKIN halted, changed, operated below specified frequency. Crystal Oscillator Terminal Used conjunction with CLKIN enable ADSP-21161N's internal clock oscillator disable external clock source. CLKIN. Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate equal PLLICLK where user selectable using CLK_CFG1-0 inputs. These pins also used combination with CLKDBL generate additional core clock rates CLKIN CLKIN (see table below).
XTAL
CLK_CFG1-0
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Table Descriptions (Continued) Function
CLKDBL
Crystal Double Mode Enable. This used enable clock double circuitry, where CLKOUT configured either rate CLKIN. Crystal Double Mode Enable. This used enable clock double circuitry, where CLKOUT configured either rate CLKIN. This CLKIN double circuit primarily intended used external crystal conjunction with internal clock generator XTAL pin. internal clock generator when used conjunction with XTAL external crystal designed support maximum external crystal frequency. CLKDBL used XTAL mode generate input into PLL. clock mode enabled (during RESET low) tying CLKDBL GND, otherwise connected VDDEXT clock mode. example, this allows crystal enable core clock rates CLKOUT operation when CLK_CFG1='0', CLK_CFG1='0' CLKDBL='0'. This also used generate different clock rate ratios external clock oscillators well. possible clock rate ratio options MHz) either CLKIN (external clock oscillator) XTAL (crystal input) follows Clock Rate Ratios
CLKDBL
CLK_CFG1
CLK_CFG0
Core Clock Ratio
Clock Ratio
ratio allows 12.5 crystal generate core (instruction clock) rate CLKOUT (external port) clock rate. also Figure page Note: When using external crystal, maximum crystal frequency cannot exceed Mhz. other external clock sources, maximum CLKIN frequency MHz. CLKOUT Local Clock Out. CLKOUT driven either frequency CLKIN frequency current master. frequency determined CLKDBL pin. This output three-stated when ADSP-21161N master when host controls (HBG asserted). keeper latch DSP's CLKOUT maintains output level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. CLKDBL enabled, CLKOUT 2xCLKIN CLKDBL disabled, CLKOUT 1xCLKIN Note: CLKOUT only controlled CLKDBL operates either 1xCLKIN 2xCLKIN. CLKOUT multiprocessing systems. CLKIN instead. Processor Reset. Resets ADSP-21161N known state begins execution program memory location specified hardware reset vector address. RESET input must asserted (low) power-up. Test Clock (JTAG). Provides clock JTAG boundary scan.
RESET
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Table Descriptions (Continued) Function
TRST
Test Mode Select (JTAG). Used control test state machine. internal pull-up resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. internal pull-up resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21161N. TRST internal pull-up resistor. Emulation Status. Must connected ADSP-21161N Analog Devices Tools product line JTAG emulators target board connector only. internal pullup resistor. Core Power Supply. Nominally +1.8 supplies DSP's core processor pins). Power Supply. Nominally +3.3 pins). Analog Power Supply. Nominally +1.8 supplies DSP's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. more information, Power Supplies page Analog Power Supply Return. Power Supply Return. pins). Connect. Reserved pins that must left open unconnected. pins).
(O/D)
VDDINT VDDEXT AVDD
AGND
Boot Modes
Table Boot Mode Selection EBOOT LBOOT Booting Mode
Output
(Input) (Input) (Input) (Input)
(Input)
EPROM (Connect EPROM chip select.) Host Processor Serial Boot Link Port Booting. Processor executes from external memory. Reserved
Host PROM boot, channel (EPB0) used. Link Boot boot, channel used. *Can three-state only EPROM boot mode (when output).
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September 2001
RECOMMENDED OPERATING CONDITIONS
Signal Grade Parameter1 Unit
VDDINT AVDD VDDEXT VIH1 VIH2 TCASE
2Applies
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, VDDEXT High Level Input Voltage3, VDDEXT Level Input Voltage2,3 VDDEXT Case Operating Temperature4
1.71 1.71 3.13 -0.5
1.89 1.89 3.47 VDDEXT+0.5 VDDEXT+0.5
Specifications subject change without notice. input bidirectional pins: DATA47-16, ADDR23-0, MS3-0, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, HBR, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, TMS, TDI. input pins: CLKIN, RESET, TRST. Environmental Conditions page information thermal specifications.
3Applies 4See
ELECTRICAL CHARACTERISTICS
Parameter1 Test Conditions
Unit
IIHC IILC IILPU IOZH IOZL IOZLPU1 IOZLPU2 IOZHPD1 IDD-INPEAK IDD-INHIGH IDD-INLOW IDD-IDLE AIDD
High Level Output Voltage Level Output Voltage1 High Level Input Current3,4 Level Input Current3 CLKIN High Level Input Current5 CLKIN Level Input Current5 Level Input Current Pull-Up4 Three-State Leakage Current 6,7,8 Three-State Leakage Current6,9 Three-State Leakage Current Pull-Up1 Three-State Leakage Current Pull-Up2 Three-State Leakage Current Pull-Down19 Supply Current (Internal)10 Supply Current (Internal)11 Supply Current (Internal)12 Supply Current (Idle)13 Supply Current (Analog)14 Input Capacitance15,16
VDDEXT min, -2.0 VDDEXT min, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT VDDEXT max, VDDEXT= max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, tCCLK 10.0 VDDINT tCCLK 10.0 VDDINT tCCLK 10.0 VDDINT VDDINT @AVDD fIN=1 MHz, TCASE=25°C, VIN=1.8V
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ADSP-21161N
Applies output bidirectional pins: DATA47-16, ADDR23-0, MS3-0, ACK, DQM, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR6-1, BMSTR, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL, TDO, CLKOUT, TIMEXP. Output Drive Currents page typical drive current capabilities. SBTS, IRQ2-0, FLAG11-0, HBG, HBR, BR6-1, ID2-0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN. input pins with internal pull-ups:RD, ACK, DMAR1, DMAR2, TRST, TMS, TDI. CLKIN only.
2See
3Applies input pins: DATA47-16, ADDR23-0, MS3-0,
4Applies 5Applies 6Applies
three-statable pins DATA47-16, ADDR23-0, MS3-0, CLKOUT, FLAG11-0, REDY, HBG, BMS, BR6-1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10, BRST. three-statable pins with pull-ups: DMAG1, DMAG2, three-statable pins with internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI three-statable pins with internal pull-downs: LxDAT7-0, LxCLK, LxACK.
7Applies 8Applies 9Applies 10The
test program used measure IDDINPEAK represents worst case processor operation sustainable under normal application conditions. Actual internal power measurements made using typical applications less than specified. more information, "Power Dissipation" page
DDINHIGH
composite average based range high activity code. more information, Power Dissipation page
DDINLOW composite average based range activity code. more information, Power Dissipation page
13Idle
denotes ADSP-21161N state during execution IDLE instruction. more information, Power Dissipation page tested. signal pins. tested.
14Characterized, 15Applies
16Guaranteed,
Table Absolute Maximum Ratings1 Parameter Absolute Maximum Rating
Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (AVDD) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range
1Stresses greater than those listed
-0.3 +2.2 -0.3 +2.2 -0.3 +4.6 -0.5 VDDEXT -0.5 VDDEXT -65°C +150°C
above cause permanent damage device. These stress ratings only, functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION: (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-21161N features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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Timing Specifications
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ADSP-21161N's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source external port logic pads). ADSP-21161N's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, link ports, serial ports, external port
required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLK_CFG1-0 CLKDBL pins. Even though internal clock clock source external port, behaves described Clock Rate Ratio chart CLKDBL description (see CLKDBL description page 18). determine switching frequencies serial link ports, divide down internal clock, using programmable divider control each port (DIVx serial ports LxCLKD link ports).
scillato
Loop
CCLK
enable operation
CLKDBL
CLKOUT
[1:0]
Figure Core Clock System Clock Relationship CLKIN
Note following definitions various clock periods that function CLKIN appropriate ratio control.
Figure allows Core-to-CLKIN ratios 1:1, 2:1, 3:1, 4:1, 6:1, with external oscillator crystal:
Table ADSP-21161N CLKOUT CCLK Clock Generation Operation Timing Requirements Calculation Description
CLKIN CLKOUT PLLICLK CCLK
1/tCKIN 1/tTCK 1/tPLLIN 1/tCCLK
Description1
Input Clock External Port System Clock Input Clock Core Clock
Timing Requirements
tCCLK tLCLK tSCLK tSDK tSPICLK
CLKIN Clock Period (Processor) Core Clock Period Link Port Clock Period (tCCLK) Serial Port Clock Period (tCCLK) SDRAM Clock Period (tCCLK) SDCKR Clock Period (tCCLK) SPIR
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1where:
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ADSP-21161N
link port-to-core clock ratio 1:4, determined LxCLKD) serial port-to-core clock ratio (wide range, determined CLKDIV) SDCKR SDRAM-to-Core Clock Ratio (1:1 1:2, determined SDCTL register) SPIR SPI-to-Core Clock Ratio (wide range, determined SPICTL register) LCLK Link Port Clock SCLK Serial Port Clock SDRAM Clock SPICLK Clock
exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure page under Test Conditions voltage reference levels. Switching Characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timing Requirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices.
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Power Dissipation
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Total power dissipation components: internal circuitry switching external output drivers. Internal power dissipation depends instruction execution sequence data operands involved. Using current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from Electrical Characteristics page current-versus-operation information Table programmer estimate ADSP-21161N's internal power supply (VDDINT) input current specific application, according following formula:
Table ADSP-21161N Operation Types Versus Input Current Operation Peak Activity1 (IDDINPEAK)
Peak DDINPEAK High DDINHIGH DDINLOW Idle DDIDLE DDINT
High Activity1 (IDDINHIGH)
Activity1 (IDDINLOW)
Instruction Type Instruction Fetch Core Memory Access2 Internal Memory External Memory Data pattern core memory access
1The 2These
Multifunction Cache cycle tCCLK cycles external port cycle Worst case
Multifunction Internal Memory cycle tCCLK cycles external port cycle Random
Single Function Internal Memory None
state PEYEN (SIMD versus SISD mode) does influence these calculations. assume core clock ratio. more information ratios clocks (tCK tCCLK), timing ratio definitions page
external component total power dissipation caused switching output pins. magnitude depends number output pins that switch during each cycle maximum frequency which they switch Their load capacitance Their voltage swing (VDD) calculated PEXT VDD2 load capacitance should include processors package capacitance (CIN). switching frequency includes driving load high then back low. Address data pins drive high maximum rate 1TCK while writing SDRAM Memory. Example: Estimate PEXT with following assumptions: system with bank external memory bit) SDRAM chips used, each with load 10pF
External Data Memory writes occur every cycle rate 1/tck, with pins switching cycle time 50Mhz external SDRAM clock rate 100Mhz
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PEXT equation calculated each class pins that drive:
Table External Power Calculations (3.3 Device) Type Pins Switching VDD2 PEXT
Address SDWE Data SDCLK0 PEXT 0.298
44.7 44.7 44.7 14.7 10.7
10.9 10.9 10.9 10.9 10.9
0.134 0.000 0.024 0.128 0.012
typical power consumption calculated these conditions adding typical internal power dissipation: PTOTAL PEXT PINT PPLL Where: PEXT from Table PINT IDDINT 1.8V, using calculation IDDINT listed Power Dissipation page PPLL AIDD 1.8V, using value AIDD listed Electrical Characteristics page Note that conditions causing worst-case PEXT different from those causing worst-case PINT. Maximum PINT cannot occur while 100% output pins switching from ones zeros. Note also that common application have 100% even outputs switching simultaneously.
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Power Sequencing
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timing requirements startup given Table
Table Power Sequencing Timing Requirements (DSP Startup) Name Parameter Units
Timing Requirements tRSTVDD tVDDRAMP tVDDEVDD tCLKRST tPLLRST
1Applies
RESET before VDDINT/VDDEXT VDDINT/VDDEXT voltage ramp rate VDDINT before VDDEXT CLKIN running before RESET de-asserted PLLCNTL1 setup before RESET de-asserted
V/µs
pins CLK_CFG1-0
Figure Power Sequencing
During powerup sequence DSP, differences ramp rates activation time between supplies cause current flow protection circuitry. prevent this damage diode protection circuitry, Analog Devices recommends including bootstrap Schottky diode. bootstrap Schottky diode connected between 1.8V 3.3V power supplies shown Figure protects ADSP-21161 from partially powering 3.3V supply. Including Schottky diode will shorten delay between supply ramps thus prevent damage diode protection circuitry. With this technique, 1.8V rail rises ahead 3.3V rail, Schottky diode pulls 3.3V rail along with 1.8V rail.
input source
3.3V oltage egulator
ADSP-21161
1.8V oltage egulator
Figure Dual Voltage Schottky Diode
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Clock Input
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CLKIN must used clock source SBSRAM. cannot external crystal when interfacing with SBSRAM.
Table Clock Input
CLKOUT clock source SBSRAM device. Using external crystal conjunction with CLKDBL generate CLKOUT frequency supported. Negative hold times result from potential skew between CLKIN CLKOUT.
Parameter Units
Timing Requirements tCKL tCKH tCKRF CLKIN Period CLKIN Width CLKIN Width High CLKIN Rise/Fall (0.4V-2.0V)
Figure Clock Input Clock Signals
ADSP-21161N external clock crystal. CLKIN description. programmer configure ADSP-21161N internal clock generator connecting necessary components CLKIN XTAL. Figure shows component connections used crystal operating fundamental mode.
XTAL
27pF
27pF
27pF 27pF
Figure Operation (Fundamental Mode Crystal)
REV.
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Reset Table Reset Parameter Units
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Timing Requirements tWRST tSRST
1Applies
RESET Pulse Width Low1 RESET Setup Before CLKIN High2
4tCK
after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than while RESET low, assuming stable CLKIN (not including start-up time external clock oscillator). ADSP-21161Ns communicating over shared (through external port), because arbitration logic synchronizes itself automatically after reset.
2Only required multiple ADSP-21161Ns must come reset synchronous CLKIN with program counters (PC) equal. required multiple
RESET
Figure Reset Interrupts Table Interrupts Parameter Units
Timing Requirements tSIR tHIR tIPW
1Only 2Applies
IRQ2-0 Setup Before CLKIN High1 IRQ2-0 Hold After CLKIN High1 IRQ2-0 Pulse Width2
required IRQx recognition following cycle. only tSIR tHIR requirements met.
Figure Interrupts
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Timer Table Timer Parameter Units
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Switching Characteristic tDTEX CLKIN High TIMEXP
DTEX
DTEX
Figure Timer Flags Table Flags Parameter Units
Timing Requirement tSFI tHFI tDWRFI tHFIWR FLAG11-0IN Setup Before CLKIN High1 FLAG11-0IN Hold After CLKIN High1 FLAG11-0IN Delay After RD/WR Low1 FLAG11-0IN Hold After RD/WR Deasserted1
Switching Characteristics tDFO tHFO tDFOE tDFOD
1Flag
FLAG11-0OUT Delay After CLKIN High FLAG11-0OUT Hold After CLKIN High CLKIN High FLAG11-0OUT Enable CLKIN High FLAG11-0OUT Disable
inputs meeting these setup hold times instruction cycle will affect conditional instructions instruction cycle N+2.
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Figure Flags
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Memory Read-Bus Master
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these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when ADSP-21161N master accessing external
Table Memory Read-Bus Master Parameter
memory space asynchronous access mode. Note that timing ACK, DATA, DMAG strobe timing parameters only apply asynchronous access mode.
Units
Timing Requirements: tDAD tDRLD tHDA tSDS tHDRH tDAAK tDSAK tSAKC tHAKC Address, Selects Delay Data Valid1,2 Data Valid1,3 Data Hold from Address, Selects4 Data Setup High Data Hold from High3,4 Delay from Address, Selects2,5 Delay from Low3,5 Setup CLKIN3,5 Hold After CLKIN3 0.5tCCLK+3 tCK-0.5tCCLK-12+W tCK-0.75tCCLK-11+W tCK-.025tCCLK-11+W 0.75tCK-11+W
Switching Characteristics tDRHA tDARL tRWR Address Selects Hold After High3 Address Selects Low2 Pulse Width3 High DMAGx Low3 0.25tCCLK-1+H 0.25tCCLK-3 tCK-0.5tCCLK-1+W 0.5tCCLK-1+HI
(number wait states specified WAIT register) tCK.
address hold cycle idle cycle occurs, specified WAIT register; otherwise address hold cycle occurs specified WAIT register; otherwise
1Data 2The
Delay/Setup: User must meet tDAD, tDRLD, tSDS. that timing ACK, DATA, DMAG strobe timing parameters only apply asynchronous access mode.
falling edge MSx, referenced.
3Note 4Dat
Hold: User must meet tHDA tHDRH asynchronous access mode. Example System Hold Time Calculation page calculation hold times given capacitive loads.
DAAK, tDSAK, tSAKC deassertion (Low), three specifications must assertion (High).
5ACK Delay/Setup: User must meet
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LKIN
Figure Memory Read-Bus Master
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Memory Write-Bus Master
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these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when
ADSP-21161N master accessing external memory space asynchronous access mode. Note that timing ACK, DATA, DMAG strobe timing parameters only apply asynchronous access mode.
Table Memory Write-Bus Master Parameter Units
Timing Requirements: tDAAK tDSAK tSAKC tHAKC Delay from Address, Selects1,2 Delay from Low1,3 Setup CLKIN1,3 Hold After CLKIN1,3 0.5tCCLK tCK-0.5tCCLK-12+W tCK-0.75tCCLK-11+W
Switching Characteristics: tDAWH tDAWL tDDWH tDWHA tDWHD tDATRWH tWWR tDDWR tWDE Address, CIF, Selects Deasserted2,3 Address, CIF, Selects Low2 Pulse width3 Data Setup before High3 Address Hold after Deasserted3 Data Hold after Deasserted3 Data Disable after Deasserted3,4 High DMAGx Low3 Data Disable before Data Enabled 0.25tCCLK 0.25tCCLK 0.5tCCLK 0.25tCCLK 12.5+W 0.25tCCLK 0.25tCCLK 0.25tCCLK 0.5tCCLK 0.25tCCLK -0.25tCCLK .25tCCLK+2+H
(number wait states specified WAIT register) tCK. address hold cycle occurs, specified WAIT register; otherwise address hold cycle idle cycle occurs, specified WAIT register; otherwise idle cycle occurs, specified WAIT register; otherwise
1ACK Delay/Setup: User must meet 2The
DAAK tDSAK tSAKC deassertion (Low), three specifications must assertion (High).
falling edge MSx, referenced. that timing ACK, DATA, DMAG strobe timing parameters only applies asynchronous access mode. Example System Hold Time Calculation page calculation hold times given capacitive loads.
3Note 4See
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LKIN
Figure Memory Write-Bus Master
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Synchronous Read/Write-Bus Master
these specifications interfacing external memory systems that require CLKIN, relative timing accessing slave ADSP-21161N multiprocessor memory space). These synchronous switching characteristics also valid during asynchronous memory reads writes except where noted (see Memory Read-Bus Master page Synchronous Read/Write-Bus Master
Table Synchronous Read/Write-Bus Master Parameter
page 35). When accessing slave ADSP-21161N, these switching characteristics must meet slave's timing requirements synchronous read/writes (see Synchronous Read/Write-Bus Slave page 37). slave ADSP-21161N must also meet these (bus master) timing requirements data acknowledge setup hold times.
Units
Timing Requirements tSSDATI tHSDATI tSACKC tHACKC Data Setup Before CLKIN Data Hold After CLKIN1 Setup Before CLKIN1 Hold After CLKIN
0.5tCCLK+3
Switching Characteristics tDADDO tHADDO tDRDO tDWRO tDRWL tDDATO tHDATO tDACKMO tACKMTR tDCKOO tCKOP tCKWH tCKWL
1Note 2Applies 3Applies
Address, MSx, BMS, BRST, Delay After CLKIN Address, MSx, BMS, BRST, Hold After CLKIN High Delay After CLKIN1 High Delay After CLKIN
0.25tCCLK-1 0.25tCCLK-1 0.25tCCLK-1 .025tCCLK+9 0.25tCCLK+9 0.25tCCLK+9 12.5 0.25tCCLK+3 0.25tCCLK+9
RD/WR Delay After CLKIN Data Delay After CLKIN Data Hold After CLKIN Delay After CLKIN2 Disable Before CLKIN
0.25tCCLK-3 tCK-1 tCK/2 tCK/2 tCK+13 tCK/2 tCK/2
CLKOUT Delay After CLKIN CLKOUT Period CLKOUT Width High CLKOUT Width
that timing ACK, DATA, DMAG strobe timing parameters only applies synchronous access mode. broadcast write, master precharge ACK.
only when drives operation; CLKOUT held inactive three-state otherwise, more information, System Design chapter ADSP-21160 ADSP-21161N SHARC Technical Reference.
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CLKIN
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tCKOP tDCKOO
CLKOUT
tCKWH
tCKWL
tDADDO
ADDRESS MSX, BRST
tHADDO
tSACKC
(IN)
tHACKC
tDACKMO
(OUT)
tACKMTR
tDRW
tDRDO
tSSDATI
DATA (IN)
tHSDATI
tDRWL
tDWRO
tDDATO
DATA (OUT)
tHDATO
Figure Synchronous Read/Write-Bus Master
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Synchronous Read/Write-Bus Slave
these specifications ADSP-21161N master accesses slave's registers multiprocessor memory space. master must meet these (bus slave) timing requirements.
Table Synchronous Read/Write-Bus Slave Parameter Units
Timing Requirements: tSADDI tHADDI tSRWI tHRWI tSSDATI tHSDATI Address, BRST Setup Before CLKIN Address, BRST Hold After CLKIN RD/WR Setup Before CLKIN RD/WR Hold After CLKIN Data Setup Before CLKIN Data Hold After CLKIN
Switching Characteristics tDDATO tHDATO tDACKC tHACKO Data Delay After CLKIN Data Hold After CLKIN Delay After CLKIN Hold After CLKIN 12.5
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Figure Synchronous Read/Write-Bus Slave
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Multiprocessor Request Host Request
these specifications passing mastership between multiprocessing ADSP-21161Ns (BRx) host processor (HBR, HBG).
Table Multiprocessor Request Host Request Parameter Units
Timing Requirements: tHBGRCSV tSHBRI tHHBRI tSHBGI tHHBGI tSBRI tHBRI tSPAI tHPAI tSRPBAI tHRPBAI RD/WR/CS Valid Setup Before CLKIN Hold After CLKIN1 Setup Before CLKIN Hold After CLKIN High BRx, Setup Before CLKIN BRx, Hold After CLKIN High Setup Before CLKIN Hold After CLKIN High RPBA Setup Before CLKIN RPBA Hold After CLKIN
Switching Characteristics tDHBGO tHHBGO tDBRO tHBRO tDPASO tTRPAS tDPAMO tPATR tDRDYCS tTRDYHG tARDYTR
1Only 2(O/D)
Delay After CLKIN Hold After CLKIN Delay After CLKIN Hold After CLKIN Delay After CLKIN, Slave Disable After CLKIN, Slave Delay After CLKIN, Master Disable Before CLKIN, Master REDY (O/D) (A/D) from Low2 tCK+25 0.25tCCLK-5
0.25tCCLK+9
0.5tCK
REDY (O/D) Disable REDY (A/D) High from HBG2 REDY (A/D) Disable from High
required recognition current cycle. open drain, (A/D) active drive.
REV.
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LKIN
tDPA
(SLA
tTRPA
STER)
tSPA
tHPA
RPBA
TRDY
TIVE DRIVE
Figure Multiprocessor Request Host Request
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Asynchronous Read/Write-Host ADSP-21161N
these specifications asynchronous host processor accesses ADSP-21161N, after host asserted (low). After returned
ADSP-21161N, host drive pins access ADSP-21161N's register. assumed this timing. Note: Host internal memory access supported.
Table Read Cycle Parameter Units
Timing Requirements tSADRDL tHADRDH tWRWH tDRDHRDY tDRDHRDY Address Setup Before Low1 Address Hold Hold After RD/WR High Width High Delay After REDY (O/D) Disable High Delay After REDY (A/D) Disable
Switching Characteristics tSDATRDY tDRDYRDL tRDYPRD tHDARWH
1Not
Data Valid Before REDY Disable from REDY (O/D) (A/D) Delay After REDY (O/D) (A/D) Pulse Width Read Data Disable After High
2tCK
required address valid tHBGRCSV after goes low. first access after asserted, ADDR23-0 must non-MMS value (TBD) before goes tHBGRCSV after goes low. This easily accomplished driving upper address signal high when asserted.
Table Write Cycle Parameter Units
Timing Requirements tSCSWRL tHCSWRH tSADWRH tHADWRH tWWRL tWRWH tDWRHRDY tSDATWH tHDATWH Setup Before Hold After High Address Setup Before High Address Hold After High Width RD/WR High Width High Delay After REDY (O/D) (A/D) Disable Data Setup Before High Data Hold After High
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Table Write Cycle Parameter Units
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Switching Characteristics tDRDYWRL tRDYPWR REDY (O/D) (A/D) Delay After WR/CS REDY (O/D) (A/D) Pulse Width Write
TIVE
Figure Asynchronous Read/Write-Host ADSP-21161N
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Three-State Timing-Bus Master, Slave, HBR, SBTS
These specifications show memory interface disabled (stops driving) enabled (resumes driving) relative CLKIN SBTS pin. This timing applicable master transition cycles (BTC) host transition cycles (HTC) well SBTS pin.
Table Three-State Timing-Bus Slave, HBR, SBTS Parameter Units
Timing Requirements tSTSCK tHTSCK SBTS Setup Before CLKIN SBTS Hold After CLKIN
Switching Characteristics tMIENA tMIENS tMIENHG tMITRA tMITRS tMITRHG tDATEN tDATTR tACKEN tACKTR tCDCEN tCDCTR tMTRHBG tMENHBG
1Strobes
Address/Select Enable After CLKIN Strobes Enable After CLKIN1 Enable After CLKIN Address/Select Disable After CLKIN Strobes Disable After CLKIN Disable After CLKIN Data Enable After CLKIN2 Data Disable After CLKIN2 Enable After CLKIN2 Disable After CLKIN CLKOUT Enable After CLKIN CLKOUT Disable After CLKIN Memory Interface Disable Before Low3 Memory Interface Enable After High3
0.25tCCLK-1 0.25tCCLK-4 tCCLK-3 tCK-6 tCK-5
0.25tCCLK+4 0.25tCCLK tCCLK+1 tCK+2 tCK+5
DMAGx. Interface Address, MSx, DMAGx, EPROM boot mode).
addition master transition cycles, these specs also apply master slave synchronous read/write.
3Memory
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Figure Three-State Timing
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Handshake
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These specifications describe three handshake modes. three modes DMAR used initiate transfers. handshake mode, DMAG controls latching enabling data externally. external handshake mode, data transfer controlled ADDR23-0, MS3-0, ACK, DMAG signals. Paced Master mode,
Table Handshake Parameter
data transfer controlled ADDR23-0, MS3-0, (not DMAG). Paced Master mode, Memory Read-Bus Master, Memory Write-Bus Master, Synchronous Read/Write-Bus Master timing specifications ADDR23-0, MS3-0, DATA47-16, also apply.
Unit
Timing Requirements: tSDRC tWDR tSDATDGL tHDATIDG tDATDRH tDMARLL tDMARH DMARx Setup Before CLKIN1 DMARx Width (Nonsynchronous)2 Data Setup After DMAGx Low3 Data Hold After DMAGx High Data Valid After DMARx High3 DMARx Edge Edge4 DMARx Width High2 0.5tCCLK 0.5tCCLK 0.5tCCLK
Switching Characteristics: tDDGL tWDGH tWDGL tHDGC tVDATDGH tDATRDGH tDGWRL tDGWRH tDGWRR tDGRDL tDRDGH tDGRDR tDGWR tDADGH tDDGHA DMAGx Delay After CLKIN DMAGx High Width DMAGx Width DMAGx High Delay After CLKIN Data Valid Before DMAGx High5 Data Disable After DMAGx High6 Before DMAGx DMAGx Before High High Before DMAGx High7 Before DMAGx Before DMAGx High High Before DMAGx High7 DMAGx High WRx, RDx, DMAGx Address/Select Valid DMAGx High Address/Select Hold after DMAGx High 0.25tCCLK 0.5tCCLK 1+HI 0.5tCCLK 0.25tCCLK 0.25tCCLK 0.25tCCLK -1.5 0.5tCCLK -1.5 -1.5 0.5tCCLK -2+W -1.5 0.5tCCLK 2+HI 0.25tCCLK 0.25tCCLK 0.25tCCLK +1.5 0.25tCCLK
(number wait states specified WAIT register) tCK. data idle cycle occurs, specified WAIT register; otherwise REV.
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1Only 2Maximum
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required recognition current cycle.
throughput using DMARx/DMAGx handshaking equals tWDR tDMARH (tCCLK +4.5) (tCCLK 4.5)=29 (34.5 MHz). This throughput limit applies non-synchronous access mode only.
SDATDGL data setup requirement DMARx being used hold completion write. Otherwise, DMARx holds completion write, data driven tDATDRH after DMARx brought high.
4Use
tDMARLL DMARx transitions synchronous with CLKIN. Otherwise, tWDR tDMARH.
VDATDGH valid DMARx being used hold completion read. DMARx used prolong read, then tVDATDGH .25tCCLK tCK) where equals number extra cycles that access prolonged.
6See
Example System Hold Time Calculation page calculation hold times given capacitive loads. parameter applies synchronous access mode only.
7This
SFER
-2116X IVE)
SP-21161
TIDG
SFER
STER STER IFIC 23-0 PPLY
Figure Handshake Timing
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SDRAM Interface Master
these specifications ADSP-21161N master accesses SDRAM:
Table SDRAM Interface Master
Parameter Timing Requirements: tSDSDK tHDSDK tDSDK1 tSDK tSDKH tSDKL tDCADSKD tHCADSDK tSDTRSDK tSDENSDK tSDCTR tSDCEN tSDSDKTR tSDSDKEN tSDATR tSDAEN
1For
Data Setup before SDCLK Data Hold after SDCLK First SDCLK Rise Delay after CLKIN1 SDCLK Period SDCLK Width High2 SDCLK Width Command, Address, Data, Delay after SDCLK3 Command, Address, Data, Hold after SDCLK3 Data Three-State after SDCLK Data Enable After SDCLK4 Command Three-State After CLKIN Command Enable After CLKIN SDCLK Three-State after CLKIN SDCLK Enable after CLKIN Address Three-State after CLKIN Address Enable after CLKIN 0.75 tCCLK tCCLK -0.4 -0.4 -0.4 -0.4 SDCKR tCCLK -0.25 tCCLK 10.0
Units
Switching Characteristics: SDCKR tCCLK -0.25 tCCLK tCCLK tCCLK tCCLK tCCLK
second, third, forth rising edges SDCLK delay from CLKIN, appropriate number SDCLK period tDSDK1 tSSDKC1 values, depending upon SDCKR value Core CLKIN ratio. SDCLK equal core clock frequency SDCKR SDCLK equal half core clock frequency. SDCKE, RAS, CAS, SDWE. Controller adds SDRAM three-stated cycle delay read followed, write.
2SDCKR
3Command 4SDRAM
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SDRAM Interface Slave
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These timing requirements allow slave sample master's SDRAM command detect when refresh occurs.
CLKIN
DSDK1
DSDK2
SDKH
SDCLK DATA(IN)
SDSDK
THDSDK
SDKL
DCADSDK SDENSDK
SDTRSDK
HCADSDK
DATA(OUT) CMND1ADDR (OUT)
DCADSDK
SDCEN
HCADSDK
SDCTR
CMND1(OUT)
ADDR (OUT)
SDAEN
SDATR
CLKOUT
SSDKC1
SSDKC2
SDCLK (IN)
tSCSDK
CMND2 (IN)
HCSDK
ontro thre e-sta llow rite.
Figure SDRAM Interface
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Link Ports
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Calculation link receiver data setup hold relative link clock required determine maximum allowable skew that introduced transmission path between LDATA LCLK. Setup skew maximum delay that introduced LDATA relative LCLK, (setup skew tLCLKTWH tDLDCH tSLDCL). Hold skew maximum delay that introduced LCLK relative LDATA, (hold skew tLCLKTWL tHLDCH tHLDCL). Calculations made directly from speed specifications will
Table Link Ports Receive Parameter
result unrealistically small skew times because they include multiple tester guardbands. setup hold skew times shown below calculated include only tester guardband. ADSP-21161N Setup Skew ADSP-21161N Hold Skew Note that there two-cycle effect latency between link port enable instruction enabling link port.
Units
Timing Requirements tSLDCL tHLDCL tLCLKIW tLCLKRWL tLCLKRWH Data Setup Before LCLK Data Hold After LCLK LCLK Period LCLK Width LCLK Width High tLCLK
Switching Characteristics tDLALC
1LACK
LACK Delay After LCLK High1
goes with tDLALC relative rise LCLK after first nibble, doesn't receiver's link buffer about fill.
T(7:0)
Figure Link Ports-Receive
Table Link Ports Transmit Parameter Units
Timing Requirements tSLACH tHLACH LACK Setup Before LCLK High LACK Hold After LCLK High
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Parameter
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Units
Table Link Ports Transmit (Continued)
Switching Characteristics tDLDCH tHLDCH tLCLKTWL tLCLKTWH tDLACLK Data Delay After LCLK High Data Hold After LCLK High LCLK Width LCLK Width High LCLK Delay After LACK High .5tLCLK-1.5 .5tLCLK-1.5 .5tLCLK+5 .5tLCLK+1.5 .5tLCLK+1.5 3tLCLK+11
ITTE
FIRS ITTE
T(7:0)
PPLIE
ITTE
Figure Link Ports-Transmit
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Serial Ports
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determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width.
Table Serial Ports-External Clock Parameter Units
Timing Requirements tSFSE tHFSE tSDRE tHDRE tSCLKW tSCLK
1Referenced 2FSx
Transmit/Receive Setup Before Transmit/Receive SCLK1 Transmit/Receive Hold After Transmit/Receive SCLK1, Receive Data Setup Before Receive SCLK1, Receive Data Hold After SCLK1, SCLKx Width SCLKx Period
sample edge.
2tCCLK
hold after Receive SCLK when minimum from drive edge. Transmit hold after Transmit SCLK late external Transmit minimum from drive edge. Configured receive clock/frame sync with DDIR SPCTLx register. Configured transmit clock/frame sync with DDIR SPCTLx register.
3SCLK/FS 4SCLK/FS
Table Serial Ports-Internal Clock Parameter Units
Timing Requirements tSFSI tHFSI tSDRI tHDRI
1Referenced 2SCLK/FS 3FSx
Setup Time Before SCLK1, Hold After SCLK1, Receive Data Setup Before SCLK1 Receive Data Hold After SCLK1
sample edge.
configured receive clock/frame sync with DDIR SPCTLx register.
hold after Receive SCLK when minimum from drive edge. Transmit hold after Transmit SCLK late external Transmit minimum from drive edge.
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Parameter
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Units
Table Serial Ports-External Internal Clock
Switching Characteristics tDFSE tHOFSE
1SCLK/FS
Delay After SCLK1 (Internally Generated Hold After Receive SCLK (Internally Generated FS)1
drive edge.
Configured receive clock/frame sync with DDIR SPCTLx register.
2Referenced
Table Serial Ports-External Clock Parameter Units
Switching Characteristics tDFSE tHOFSE tDDTE tHODTE
1Referenced 2SCLK/FS
Delay After Transmit SCLK (Internally Generated Transmit Hold After Transmit SCLK (Internally Generated Transmit Transmit Data Delay After Transmit SLCK Transmit Data Hold After Transmit SCLK
drive edge.
Configured transmit clock/frame sync with DDIR SPCTLx register.
Table Serial Ports-Internal Clock Parameter Units
Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW
1Referenced 2SCLK/FS
Transmit Delay After SCLK (Internally Generated Transmit FS)1, Transmit Hold After SCLK (Internally Generated Transmit FS)1, Transmit Data Delay After SCLK1, Transmit Data Hold After SCLK1, Transmit Receive SCLK Width2
drive edge.
-1.5 .5tSCLK-2.5 .5tSCLK+2
Configured transmit clock/frame sync with DDIR SPCTLx register.
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Table Serial Ports-Enable Three-State
Switching Characteristics tDDTEN tDDTTE tDDTIN tDDTTI
1Referenced 2SCLK/FS
Data Enable from External Transmit SCLK1, Data Disable from External Transmit SCLK1 Data Enable from Internal Transmit SCLK1 Data Disable from Internal Transmit SCLK1
drive edge.
Configured transmit clock/frame sync with DDIR SPCTLx register.
Table Serial Ports-External Late Frame Sync Parameter Units
Switching Characteristics tDDTLFSE tDDTENFS
1MCE
Data Delay from Late External Transmit External Receive with Data Enable from Late
Transmit enable Transmit valid follow tDDTLFSE tDDTENFS.
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/DxB
ITHE ISIN LLIN TIVE
ITHE ISIN LLIN TIVE
/DxB
/DxB
Figure Serial Ports
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/DxB
Figure External Late Frame Sync
REV.
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Interface Specifications Table Interface Protocol Master Switching Timing Specifications Name Parameter Units
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Switching Characteristics tSPICLKM tSPICHM tSPICLM tDDSPIDM tHDSPIDM tSDSCIM tHDSM Timing Requirements tSSPIDM tHSPIDM tSPITDM Data input valid SPICLK edge (data input set-up time) SPICLK last sampling edge data input valid Sequential transfer delay tCCLK+8 tCCLK+1 tCCLK Serial clock cycle Serial clock high period Serial clock period SPICLK edge data valid (data delay time) SPICLK edge data valid (data hold time) FLAG3-0 (SPI device select) first SPICLK edge Last SPICLK edge FLAG3-0 high tCCLK tCCLK tCCLK tCCLK-4 tCCLK-4
Table Interface Protocol -Slave Switching Timing Specifications Name Parameter Units
Switching Characteristics tDSOE tDSDHI tDDSPIDS tHDSPID tDSOV Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Serial clock cycle Serial clock high period Serial clock period SPIDS assertion first SPICLK edge CPHASE CPHASE Last SPICLK edge SPIDS asserted CPHASE tCCLK tCCLK-4 tCCLK-4 tCCLK+1 tCCLK+1 SPIDS assertion data active SPIDS deassertion data high impedance SPICLK edge data valid (data delay time) SPICLK edge data valid (data hold time) SPIDS assertion data valid (CPHASE=0) tCCLK+8 2.25 tCCLK+8 tCCLK+7 tCCLK+7 tCCLK+8
tHDS
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Table Interface Protocol -Slave Switching Timing Specifications (Continued) Parameter
tSSPIDS tHSPIDS tSPITDS
Data input valid SPICLK edge (data input set-up time) SPICLK last sampling edge data input valid SPIDS deassertion pulse width (CPHASE=0)
tCCLK+1 tCCLK
tSDSCIM
PICHM
tSPICLM
PICLK
tHDSM
tSPITDM
tSPICHM
tDDSPID
tHDS
SPIDM
SPIDM
tDDSPID
MOSI
tHDS
tHSPIDM
Figure Master Timing
REV.
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PICHS
tHDS
PITDS
tSDS
PICLS
tSPICHS
tDSDHI
HA=1
PIDS
tHSPIDS
PIDS
PIDS
tDSDHI
HA=0
tHSPIDS
Figure Slave Timing
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JTAG Test Access Port Emulation Table JTAG Test Access Port Emulation Parameter Units
Timing Requirements tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW Period TDI, Setup Before High TDI, Hold After High System Inputs Setup Before Low1 System Inputs Hold After Low1 TRST Pulse Width 4tCK
Switching Characteristics tDTDO tDSYS
1System
Delay from System Outputs Delay After Low2
Inputs DATA47-16, ADDR23-0, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2-1, CLK_CFG1-0, CLKDBL, HBR, SBTS, ID2-0, IRQ2-0, RESET, BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6-1, MS3-0, FLAG11-0
2System
Outputs BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, DATA47-16, SDWE, ACK, HBG, RAS, CAS, SDCLK1-0, SDCKE, BRST, BR6-1, MS3-0, ADDR23-0, FLAG11-0, DMAG2-1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR.
tSTA
DTDO
SYSTEM PUTS
HSYS
DSYS
SYSTEM UTPU
Figure IEEE 11499.1 JTAG Test Access Port
REV.
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Output Drive Currents
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Figure shows typical characteristics output drivers ADSP-21161N. curves represent current drive capability output drivers function output voltage.
high voltage level point when output reached specified high trip point, shown Output Enable/Disable diagram (Figure 36). multiple pins (such data bus) enabled, measurement value that first start driving.
Output Disable Time
-100 -120
3.47V, 3.3V, +25°C 3.13V, +85°C
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation: tDECAY (CLV)/IL output disable time tDIS difference between tMEASURED tDECAY shown Figure time tMEASURED interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY calculated with test loads with equal
3.13V, +85°C 3.3V, +25°C 3.47V,
(VDDEXT)
Example System Hold Time Calculation
Figure ADSP-21161N Typical Drive Test Conditions
Output Enable Time
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when reference signal reaches
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-21161N's output voltage input threshold device requiring hold time. typical will total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY plus minimum disable time (i.e., tDATRWH write cycle).
EFER tDIS 2.0V 1.0V
TPUT
TPUT DITIO TELY 1.5V
Figure Output Enable/Disable Capacitive Loading
Output delays holds based standard capacitive loads: pins (see Figure page 61). delay hold specifications given should derated factor ns/50 loads other than nominal value
Figure Figure show output rise time varies with capacitance. Figure shows graphically output delays holds vary with load capacitance (Note that this graph derating does apply output
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
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1.5V
Figure Equivalent Device Loading Measurements (Includes Fixtures)
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
Figure Typical Output Delay Hold Load Capacitance Case Temperature)
disable delays; Output Disable Time page 60.). graphs Figures linear outside ranges shown=Max) Load CapacitanceTypical Output Rise Time (10%-90%, V=Min) Load Capacitance.
Environmental Conditions
K6-10) provide thermal pathways printed circuit board's ground plane. heatsink should attached ground plane close possible thermal pathways) with thermal adhesive. TCASE Case temperature (measured surface package) Power dissipation (this value depends upon specific application; method calculating shown under Power Dissipation).
Thermal Characteristics
ADSP-21161N packaged 225-lead Mini Ball Grid Array (MBGA). ADSP-21161N specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heatsink and/or flow source used. center block ground pins (MBGA balls: F6-10, G6-10, H6-10, J6-10, REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
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16.0 14.0 12.0 10.0
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Figure Typical Output Rise Time (10%-90%, Vddext Max)
=TBD
Figure Typical Output Rise Time (10%-90%, Vddext Min)
CASE
Value from Table 8.0°C/W
Table Airflow Over Package Versus
Airflow (Linear Ft./Min.) (°C/W)1 °C/W.
17.82
15.2
13.68
This information applies product under development. characteristics specifications subject change without notice. Analog Devi
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