8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232 SERIAL

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8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232 SERIAL

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FEATURES Nonvolatile Memory Preset Maintains Wiper Settings Dual Channel, 256-Position Resolution Full Monotonic Operation Terminal Resistance Linear Taper Settings Push-Button Increment/Decrement Compatible SPI-Compatible Serial Data Input with Readback Function Single Supply Dual Supply Operation Bytes User EEMEM Nonvolatile Memory Constant Storage Permanent Memory Write Protection 100-Year Typical Data Retention APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment Switch Setting GENERAL DESCRIPTION
8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232
SERIAL INTERFACE ADDR DECODE RDAC1 REGISTER
AD5232
RDAC1 EEMEM1
EEMEM CONTROL BYTES USER EEMEM
RDAC2 REGISTER
RDAC2
EEMEM2
AD5232 device provides nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. These devices perform same electronic adjustment function potentiometer variable resistor. AD5232's versatile programming microcontroller allows multiple modes operation adjustment. direct program mode predetermined setting RDAC register loaded directly from microcontroller. Another mode operation allows RDAC register refreshed with setting previously stored EEMEM register. When changes made RDAC register establish wiper position, value setting saved into EEMEM executing EEMEM save operation. Once settings saved EEMEM register these values will automatically transferred RDAC register wiper position system power Such operation enabled internal preset strobe preset also accessed externally. internal register contents read serial data output (SDO). This includes RDAC1 RDAC2 registers, corresponding nonvolatile EEMEM1 EEMEM2 registers, spare USER EEMEM registers available constant storage.
*Patent pending.
basic mode adjustment increment decrement command controlling present setting Wiper position setting (RDAC) register. internal scratch RDAC register moved DOWN step nominal terminal resistance between terminals This linearly changes wiper terminal resistance (RWB) position segment devices' end-to-end resistance (RAB). exponential/logarithmic changes wiper setting, left/right shift command adjusts levels steps, which useful audio light alarm applications. AD5232 available thin TSSOP-16 package. parts guaranteed operate over extended industrial temperature range -40°C +85°C. evaluation board available, Part Number: AD5232EVAL.
PERCENT NOMINAL END-TO-END RESISTANCE
CODE Decimal
Figure Symmetrical RDAC Operation
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2001
AD5232-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS,
Parameter
VERSIONS
Typ1 Unit
+VDD, unless otherwise noted.)
Symbol Conditions
CHARACTERISTICS RHEOSTAT MODE Specifications Apply Resistor Differential Nonlinearity2 R-DNL Resistor Nonlinearity2 R-INL Nominal Resistor Tolerance Resistance Temperature Coefficient RAB/ Wiper Resistance
RWB, RWB, Code Code
-0.4
+0.4
ppm/°C Bits ppm/°C
POTENTIOMETER DIVIDER MODE Specifications Apply Resolution Differential Nonlinearity3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Code Half-Scale Full-Scale Error VWFSE Code Full-Scale Code Zero-Scale Zero-Scale Error VWZSE RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 Capacitance5 Common-Mode Leakage Current5, DIGITAL INPUTS OUTPUTS Input Logic High Input Logic Input Logic High Input Logic Input Logic High Input Logic Output Logic High (SDO RDY) Output Logic Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity5 VA,B,W CA,B VDD/VSS IDD(PG) IDD(XFR) PDISS
-0.4
+0.4
MHz, Measured GND, Code Half-Scale MHz, Measured GND, Code Half-Scale VDD/2 With Respect GND, With Respect GND, With Respect GND, VDD= With Respect GND, With Respect GND, +2.5 -2.5 With Respect GND, +2.5 -2.5 RPULL-UP VLOGIC
0.01
GND, +2.5 -2.5
2.25 0.018 0.002
2.75 0.05 0.01
REV.
AD5232
Parameter DYNAMIC CHARACTERISTICS Bandwidth Total Harmonic Distortion
Symbol
Conditions BW_10 rms, kHz, rms, kHz, VDD, 0.50% Error Band, Code k/50 k/100 Crosstalk (CW1/CW2) VDD, Measure with Adjacent Making Full-Scale Code Change VDD, Measure with kHz, Code1 80H; Code2
Typ1 0.022 0.045
Unit nV/Hz nV-s
THDW THDW
Settling Time Resistor Noise Voltage
eN_WB
0.65/3/6
Analog Crosstalk (CW1/CW2)
0.15
tCYC tCYC Cycles Years
INTERFACE TIMING CHARACTERISTICS Applies Parts5, Clock Cycle Time (tCYC) Setup Time Shutdown Time Rise Input Clock Pulsewidth Clock Level High From Positive Transition Data Setup Time Data Hold Time From Positive Transition SDO-SPI Line Acquire SDO-SPI Line Release Propagation Delay11 Data Hold Time High Pulsewidth12 High High12 Rise Fall Rise Fall Time Read/Store Nonvolatile EEMEM13 Applies Command Rise Clock Rise/Fall Setup Shown Timing Diagram Preset Pulsewidth (Asynchronous) tPRW Preset Response Time High tPRESP Pulsed Refreshed Wiper Positions FLASH/EE MEMORY RELIABILITY CHARACTERISTICS Endurance14 Data Retention15
NOTES Typical parameters represent average readings 25°C Resistor position nonlinearity error R-INL deviation from ideal value measured between maximum resistance minimum resistance wiper postions. R-DNL measures relative step change from ideal between successive positions. Parts guaranteed monotonic. version, version. Figure measured with RDAC configured potentiometer divider similar voltage output converter. VSS. specification limits maximum Guaranteed Monotonic operating conditions. Figure Resistor terminals have limitations polarity with respect each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment. Guaranteed design subject production test. Common-mode leakage current measure leakage from terminal common-mode bias level VDD/2. Transfer (XFR) Mode current continuous. Current consumed while EEMEM locations read transferred RDAC register. PDISS calculated from VDD) (ISS VSS). dynamic characteristics +2.5 -2.5 unless otherwise noted. timing diagram location measured values. input control voltages specified with (10% timed from voltage level Switching characteristics measured using both Propagation delay depends value RPULL_UP, applications text. Valid commands that activate pin. only instruction commands hardware pulse: CMD_8 CMD_9,10 0.12 CMD_2,3 Device operation -40°C extends save time Endurance qualified 100,000 cycles JEDEC Std. method A117 measured -40°C +85°C, typical endurance 25°C 700,000 cycles. Retention lifetime equivalent junction temperature 55°C JEDEC Std. Method A117. Retention lifetime based activation energy 0.6eV will derate with junction temperature shown Figure Flash/EE Memory description section this data sheet. AD5232 contains 9,646 transistors. size: mil, 7,993 mil. Specifications subject change without notice
REV.
AD5232
CPHA
CPOL
*NOT DEFINED, NORMALLY CHARACTER PREVIOUSLY TRANSMITTED.
CPOL MICROCONTROLLER COMMAND ALIGNS INCOMING DATA POSITIVE EDGE CLOCK.
Figure CPHA Timing Diagram
CPHA
CPOL
*NOT DEFINED, NORMALLY CHARACTER JUST RECEIVED.
CPOL MICROCONTROLLER COMMAND ALIGNS INCOMING DATA POSITIVE EDGE CLOCK.
Figure CPHA Timing Diagram
REV.
AD5232
ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted)
-0.3 +0.3 Intermittent2 Continuous Digital Inputs Output Voltage -0.3 +0.3 Operating Temperature Range3 -40°C +85°C Maximum Junction Temperature Max) 150°C Storage Temperature -65°C +150°C Lead Temperature, Soldering Vapor Phase sec) 215°C Infrared sec) 220°C
Package Power Dissipation TA)/ Thermal Resistance Junction-to-Ambient TSSOP-16 150°C/W Thermal Resistance Junction-to-Case TSSOP-16 28°C/W
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Maximum terminal current bounded maximum current handling switches, maximum power dissipation package, maximum applied voltage across terminals given resistance. Includes programming nonvolatile memory.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD5232 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE
Model AD5232BRU10 AD5232BRU10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRU100 AD5232BRU100-REEL7
Number Channels
End-to-End
Temperature Package Package Range (°C) Description Option TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Number Devices Container 1,000 1,000 1,000
Branding* Information 5232B10 5232B10 5232B50 5232B50 5232BC 5232BC
*Line contains logo symbol data code YYWW, line contains detail model number listed this column.
REV.
AD5232
CONFIGURATION
VIEW (Not Scale)
AD5232
FUNCTION DESCRIPTIONS
Number
Mnemonic
Description Serial Input Register Clock Pin. Shifts time positive clock edges. Serial Data Input Pin. Loaded First. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands activate output. Table Other commands shift previously loaded pattern delayed clock pulses. This allows daisy-chain operation multiple packages. Ground Pin, Logic Ground Reference. Negative Supply. Connect zero volts single supply applications. Terminal RDAC1 Wiper Terminal RDAC1, ADDR(RDAC1) Terminal RDAC1 Terminal RDAC2 Wiper Terminal RDAC2, ADDR(RDAC2) Terminal RDAC2 Positive Power Supply Write Protect Pin. When active low, prevents changes present register contents, except will refresh RDAC register from EEMEM. Execute instruction before returning logic high. Hardware Override Preset Pin. Refreshes scratch register with current contents EEMEM register. Factory default loads midscale until EEMEM loaded with value user activated logic high transition). Serial Register Chip Select Active Low. Serial register operation takes place when returns logic high. Ready. Active-high open drain output, requires pull-up resistor. Identifies completion commands
REV.
AD5232
OPERATIONAL OVERVIEW
AD5232 digital potentiometer designed operate true variable resistor replacement device analog signals that remain within terminal voltage range VTERM VDD. basic voltage range limited |VDD VSS| digital potentiometer wiper position determined RDAC register contents. RDAC register acts scratch pad, register allowing many value changes necessary place potentiometer wiper correct position. scratch register programmed with position value using standard serial interface mode loading complete representative data word. Once desirable position found, this value saved into corresponding EEMEM register. Thereafter wiper position will always that position future ON-OFF-ON power supply sequence. EEMEM save process takes approximately during this time shift register locked preventing changes from taking place. indicates completion this EEMEM save.
SCRATCH EEMEM PROGRAMMING
Table Digital POTs Independent Data Values then Save Wiper Positions Corresponding Nonvolatile EEMEM Registers
B040H 20xxH B180H 21xxH
XXXXH B040H 20xxH B180H
Action Loads data into RDAC1 register, Wiper moves full-scale position. Saves copy RDAC1 register contents into corresponding EEMEM0 register. Loads data into RDAC2 register, Wiper moves full-scale position. Saves copy RDAC2 register contents into corresponding EEMEM1 register.
aware that pulse first sets wiper midscale when brought logic zero, then positive transition logic high, reloads wiper register with contents EEMEM. Many additional advanced programming commands available simplify variable resistor adjustment process. example, wiper position changed step time using software-controlled Increment/Decrement instruction time, with Shift Left/Right instruction command. Once Increment, Decrement, Shift command been loaded into shift register, subsequent strobes will repeat this command. This useful push-button control applications. Advanced Control Modes description following Table serial data output available daisy chaining readout internal register contents. serial input data register uses 16-bit [instruction/address/data] WORD.
EEMEM PROTECTION
scratch register (RDAC register) directly controls position digital potentiometer wiper. When scratch register loaded with zeros, wiper will connected B-Terminal variable resistor. When scratch register loaded with midscale code (1/2 full-scale position), wiper will connected middle variable resistor. when scratch loaded with full-scale code, wiper will connect A-Terminal. Since scratch register standard logic register, there restriction number changes allowed. EEMEM registers have program erase/write cycle limitation described Flash/ EEMEM Reliability section.
BASIC OPERATION
basic mode setting variable resistor wiper position (programming scratch register) accomplished loading serial data input register with command instruction #11, which includes desired wiper position data. When desired wiper position found, user loads serial data input register with command instruction which copies desired wiper position data into corresponding nonvolatile EEMEM register. After wiper position will permanently stored corresponding nonvolatile EEMEM location. Table provides application-programming example listing sequence serial data input (SDI) words corresponding serial data output appearing hexadecimal format. system power-on, scratch register refreshed with value last saved EEMEM register. factory preset EEMEM value midscale. scratch (wiper) register refreshed with current contents nonvolatile EEMEM register under hardware control pulsing pin.
Write protect (WP) disables changes scratch register contents regardless software commands, except that EEMEM setting refreshed using commands Therefore, write-protect (WP) provides hardware EEMEM protection feature. Execute command before returning logic high.
DIGITAL INPUT/OUTPUT CONFIGURATION
digital inputs ESD-protected high input impedance that driven directly from most digital sources. which active logic low, must biased they being used. internal pull-up resistors present digital input pins. pins open-drain digital outputs where pull-up resistors needed only using these functions. resistor value range optimizes power switching speed trade-off.
REV.
AD5232
SERIAL DATA INTERFACE
AD5232 contains 4-wire SPI-compatible digital interface (SDI, SDO, CLK), uses 16-bit serial data word loaded first. format SPI-compatible word shown Table chip select (CS) needs held until complete data word loaded into pin. When returns high, serial data word decoded according instructions Table III. Command Bits (Cx) control operation digital potentiometer. Address Bits (Ax) determine which register activated. Data Bits (Dx) values that loaded into decoded register. Table provides address EEMEM locations. last instruction executed prior period programming activity should Operation (NOP) instruction. This will place internal logic circuitry minimum power dissipation state.
VALID COMMAND COUNTER
INPUT
AD5232
Figure Equivalent Input Protection
DAISY CHAINING OPERATION
COMMAND PROCESSOR ADDRESS DECODE
RPULLUP SERIAL REGISTER
AD5232
Figure Equivalent Digital Input-Output Logic
equivalent serial data input output logic shown Figure open-drain output disabled whenever chip select logic high. interface used slave modes CPHA CPOL CPHA CPOL CPHA CPOL refer control bits, which dictate timing these MicroConverters® microprocessors: ADuC812/ADuC824, M68HC11, MC68HC16R1/916R1. protection digital inputs shown Figures
serial data output (SDO) serves purposes. used read contents wiper setting EEMEM values using instruction respectively. remaining instructions (#0-8, #11-15) valid daisychaining multiple devices simultaneous operations. Daisy-chaining minimizes number port pins required from controlling (see Figure contains open drain N-Channel that requires pull-up resistor this function used. shown Figure users need package next package. Users need increase clock period because pull-up resistor capacitive loading SDO-SDI interface require additional time delay between subsequent packages. AD5232's daisy-chained, bits data required. first bits second bits with same format bits formatted contain 4-bit instruction, followed 4-bit address, then bits data. should kept until bits locked into their respective serial registers. then pulled high complete operation.
AD5232
AD5232
LOGIC PINS
INPUTS
Figure Daisy-Chain Configuration Using
AD5232
Figure Equivalent Digital Input Protection
Table 16-Bit Serial Data Word
AD5232
Command bits identified address bits data bits Command instruction codes defined Table III.
MicroConverter registered trademark Analog Devices, Inc.
REV.
AD5232
Table III. Instruction/Operation Truth Table
Inst
Instruction Byte
Data Byte
Operation Operation (NOP). nothing. Write contents EEMEM(A0) RDAC(A0) Register. This command leaves device Read Program power state. return part idle state, perform instruction SAVE WIPER SETTING. Write contents RDAC(ADDR) EEMEM(A0) Write contents Serial Register Data Byte EEMEM(ADDR). Decrement right shift contents RDAC(A0), stops "Zeros." Decrement right shift contents RDAC Registers, stops "Zeros." Decrement contents RDAC(A0) "One," stops "Zeros." Decrement contents RDAC Registers "One," stops "Zeros." RESET. Load RDACs with their corresponding EEMEM previously-saved values. Write contents EEMEM(ADDR) Serial Register Data Byte Write contents RDAC(A0) Serial Register Data Byte Write contents Serial Register Data Byte RDAC(A0). Increment left shift contents RDAC(A0), stops "Ones." Increment left shift contents RDAC Registers, stops "Ones." Increment contents RDAC(A0) "One," stops "Ones." Increment contents RDAC Registers "One," stops "Ones."
ADDR
ADDR
NOTES output shifts last eight bits data clocked into serial register daisy-chain operation. Exception: following Instruction selected internal register data will present data byte Instructions following must full 16-bit data word completely clock contents serial register. RDAC register volatile scratch register that refreshed power-on from corresponding nonvolatile EEMEM register. increment, decrement, shift commands ignore contents shift register Data Byte Execution Operation column noted table takes place when strobe returns logic high. Execution instruction minimizes power dissipation.
REV.
AD5232
ADVANCED CONTROL MODES
AD5232 digital potentiometer contains user programming features address wide applications available these universal adjustment devices. programming features include: Independently Programmable Read Write registers. Simultaneous refresh RDAC wiper registers from corresponding internal EEMEM registers. Increment Decrement instructions each RDAC wiper register. Left right shift RDAC wiper registers achieve level changes. Nonvolatile storage present scratch RDAC register values into corresponding EEMEM register. Fourteen extra bytes user-addressable electrical-erasable memory.
Increment Decrement Commands
Also left shift commands were modified that data RDAC register greater than equal midscale data left shifted then data RDAC register full-scale. This makes left shift function close ideally logarithmic possible. right shift commands will ideal only zero (i.e., ideal logarithmic-no error). then right shift function generates linear half error, which translates code dependent logarithmic error codes only shown attached plots, (see Figure plot shows errors codes AD5232.
LEFT SHIFT 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 RIGHT SHIFT 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000
LEFT SHIFT
RIGHT SHIFT
increment decrement commands (#14, #15, useful basic servo adjustment application. This command simplifies microcontroller software coding eliminating need perform readback current wiper position, then register contents using microcontroller's adder. microcontroller simply sends increment command (#14) digital POT, which will automatically move wiper next resistance segment position. master increment command (#15) will move wipers position from their present position next resistor segment position. direction movement referenced Terminal Thus each increment command will move wiper position farther away from Terminal
Logarithmic Taper Mode Adjustment
Figure Detail Left Right Shift Function 8-Bit AD5232
Programming instructions allow decrement increment wiper position control individual ganged arrangement where both wiper positions changed same time. These settings activated decrement increment instructions respectively. example, starting with wiper connected Terminal executing nine increment instructions (#12) would move wiper steps from terminal) position 100% position AD5232 8-Bit potentiometer. increment instruction doubles value RDAC register contents each time command executed. When wiper position greater than midscale, last increment instruction will cause wiper Full-Scale code position. additional instruction will longer change wiper position from full scale (RDAC register code 255). Figure illustrates operation shifting function individual RDAC register data bits 8-bit AD5232 example. Each line going down table represents successive shift operation. Very important: left shift commands were modified that data RDAC register equal zero data left shifted, then code
Actual conformance logarithmic curve between data contents RDAC register wiper position each Right Shift command execution contains error only codes. Even codes ideal except zero right shift greater than half-scale left shift. graph Figure shows plots Log_Error [i.e., (error/code)]. example, code Log_Error (0.5/3) -15.56 which worst case. plot Log_Error more significant lower codes.
LOG_ERROR (CODE) 8-BIT
CODE, FROM
Figure Plot Log_Error Conformance Codes Only (Even Codes Ideal)
-10-
REV.
AD5232
USING ADDITIONAL INTERNAL NONVOLATILE EEMEM
AD5232 contains additional internal user storage registers (EEMEM) saving constants other 8-bit data. Table provides address internal nonvolatile storage registers shown functional block diagram EEMEM1, EEMEM2, bytes USER EEMEM. Table EEMEM Address EEMEM Address (ADDR) 0000 0001 0010 0011 0100 0101 1111 EEMEM Contents Each Device EEMEM (ADDR) AD5232 (8B) RDAC1 RDAC2 USER USER USER USER USER
Figure Maximum Terminal Voltages
DETAIL POTENTIOMETER OPERATION
NOTES RDAC data stored EEMEM locations transferred their corresponding RDAC REGISTER Power when instructions Inst#1 Inst#8 executed. USER <data> internal nonvolatile EEMEM registers available store retrieve constants using Inst#3 Inst#9 respectively. AD5232 EEMEM locations byte each bits). Execution instruction leaves device Read Mode power consumption state. After last Instruction executed, user should perform NOP, Instruction mand return device power idle state.
Table RDAC Digital Register Address
Register Address (ADDR) 0000 0001
Name Register* AD5232 (8B) RDAC1 RDAC2
actual structure RDAC designed emulate performance mechanical potentiometer. patent-pending RDAC contains multiple strings connected resistor segments, with array analog switches that wiper connection several points along resistor array. number points resolution device. example, AD5232 connection points allowing provide better than 0.5% setability resolution. Figure provides equivalent diagram connections between three terminals that make channel RDAC. will always while switches SW(0) SW(2N-1) will time depending upon resistance step decoded from Data Bits. resistance contributed must accounted output resistance. will always while switches SW(0) SW(2 N-1) will time, depending upon resistance step decoded from Data Bits. resistance contributed must accounted output resistance.
*RDACx registers contain data determining position variable resistor wiper.
TERMINAL VOLTAGE OPERATING RANGE
digital potentiometer's positive negative power supply defines boundary conditions proper three-terminal programmable resistance operation. Signals present terminals that exceed will clamped forward biased diode; Figure ground AD5232 device primarily used digital ground reference, which needs tied PCBs' common ground. digital input logic signals AD5232 must referenced devices' ground (GND), satisfy logic minimum input high level maximum level defined specification table this data sheet. internal level-shift circuit between digital interface wiper switch control ensures that common-mode voltage range three-terminals extends from VDD.
SW(2N RDAC WIPER REGISTER DECODER
SW(2N
SW(1)
DIGITAL CIRCUITRY OMITTED CLARITY
SW(0)
Figure Equivalent RDAC Structure (Patent Pending)
REV.
-11-
AD5232
Table Nominal Individual Segment Resistor Values
PERCENT NOMINAL END-TO-END RESISTANCE
Device Resolution 8-Bit
Segment Resistor Size End-to-End Values 78.10 Version 390.5 Version 781.0 Version
PROGRAMMING VARIABLE RESISTOR Rheostat Operation
nominal resistances RDAC between terminals available with values final digits part number determine nominal resistance value, e.g., 100. nominal resistance (RAB) AD5232 contact points accessed wiper terminal, plus terminal contact. 8-bit data word RDAC latch decoded select possible settings. general transfer equation, which determines digitally programmed output resistance between RWB(Dx) (Dx)/2
CODE Decimal
Figure Symmetrical RDAC Operation
Where resolution data contained RDACx latch, nominal end-to-end resistance. example, following output resistance values will following RDAC latch codes (applies 8-bit, potentiometers):
Table VII. Nominal Resistance Value Selected Codes
Like mechanical potentiometer RDAC replaces, AD5232 parts totally symmetrical. resistance between wiper terminal also produces digitally controlled resistance RWA. Figure shows symmetrical programmability various terminal connections. When these terminals used B-terminal should tied wiper. Setting resistance value starts maximum value resistance decreases data loaded latch increased value. general transfer equation this operation RWA(Dx) (2N-Dx)/2N where resolution data contained RDACx latch, nominal end-to-end resistance. example, following output resistance values will following RDAC latch codes (applies 8-bit, potentiometers).
(DEC)
10011 5050
Output State Full-Scale Midscale Zero-Scale*(Wiper Contact Resistance)
*Note that zero-scale condition finite wiper resistance present. Care should taken limit current flow between this state maximum continuous value avoid degradation possible struction internal switch metalization. Intermittent current operation allowed.
Table VIII. Nominal Resistance Value Selected Codes
(DEC)
5050 10011 10050
Output State Full-Scale Midscale Zero-Scale
multichannel AD5232 0.2% typical distribution internal channel-to-channel match. Device-to-device matching process-lot-dependent exhibits -40% +20% variation. change with temperature ppm/°C temperature coefficient.
-12-
REV.
AD5232
PROGRAMMING POTENTIOMETER DIVIDER Voltage Output Operation
digital potentiometer easily generates output voltage proportional input voltage applied given terminal. example, connecting A-terminal B-terminal ground produces output voltage wiper which value starting zero volts Each voltage equal voltage applied across terminal divided position resolution potentiometer divider. general equation defining output voltage with respect ground given input voltage applied terminals VW(Dx) Dx/2N Operation digital potentiometer divider mode results more accurate operation over temperature. Here output voltage dependent ratio internal resistors, absolute value; therefore, drift improves ppm/°C. There voltage polarity restriction between terminals long terminal voltage (VTERM) stays within VTERM VDD.
OPERATION FROM DUAL SUPPLIES
internal parasitic capacitances external capacitive loads dominate characteristics RDACs. Configured potentiometer divider bandwidth AD5232BRU10 resistor) measures half scale. Figure provides large signal BODE plot characteristics three resistor versions parasitic simulation model been developed, shown Figure Listing provides macro model list RDAC:
Listing Macro Model List RDAC
.PARAM DW=255, RDAC=10E3 .SUBCKT DPOT (A,W,B) .ENDS DPOT
APPLICATION PROGRAMMING EXAMPLES
{45E-12} {(1-DW/256)*RDAC+50} 60E-12 {DW/256*RDAC+50} {45E-12}
AD5232 operated from dual supplies enabling control ground-referenced signals. Figure typical circuit connection.
+2.75V SCLK MOSI
following command sequence examples have been developed illustrate typical sequence events various features AD5232 nonvolatile digital potentiometer. [PCB Printed Circuit Board containing AD523x part]. Instruction numbers (Commands), addresses data appearing pins listed hexadecimal.
AD5232
Table Digital POTs Independent Data Values
-2.5V
Figure Operation from Dual Supplies
RDAC 45pF 45pF
XXXXH
Action Loads data into RDAC2 register, Wiper moves full-scale position. Loads data into RDAC1 register, Wiper moves Full-Scale position.
B140H
B080H
B140H
60pF
Figure RDAC Circuit Simulation Model RDAC
REV.
-13-
AD5232
Table Active Trimming Followed Save Nonvolatile Memory (PCB Calibrate)
B040H E0XXH E0XXH
XXXXH B040H E0XXH
Action Loads data into RDAC1 register, Wiper moves full-scale position. Increments RDAC1 register 41H, Wiper moves resistor segment away from terminal Increments RDAC1 register 42H, Wiper moves more resistor segment away from terminal Continue until desired wiper position reached. Saves RDAC1 register data into corresponding nonvolatile EEMEM1 memory ADDR
Analog Devices offers AD5232EVAL board sale simplify evaluation these programmable devices controlled personal computer printer port.
TEST CIRCUITS
Figures define test conditions used product specification's table.
CONNECT
20XXH
E0XXH
Figure Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
1LSB V+/2N
EQUIPMENT CUSTOMER STARTUP SEQUENCE CALIBRATED UNIT WITH PROTECTED SETTINGS
setting: [prevents changes wiper position] Power with respect Optional: Strobe [ensures full power preset wiper register with EEMEM contents unpredictable supply sequencing environments]
Table Using Left Shift Change Circuit Gain Steps
Figure Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
VMS2 VMS1 MS2]
C1XXH C1XXH
XXXXH XXXXH
Action Moves Wiper double present data value contained RDAC2 register, direction terminal. Moves Wiper double present data value contained RDAC2 register, direction terminal.
Figure Wiper Resistance Test Circuit
PSRR (dB) (%/%) VMS% VDD%
Table XII. Storing Additional Data Nonvolatile Memory
3280H 3340H
XXXXH XXXXH
Action Stores data into spare EEMEM location USER1. Stores data into spare EEMEM location USER2.
Figure Power Supply Sensitivity Test Circuit (PSS, PSRR)
OFFSET OP279 VOUT
Table XIII. Reading Back Data from Various Memory Locations
94XXH 00XXH
XXXXH XX80H
Action Prepares data read from USER3 location. Assumption: USER3 previously loaded with 80H. instruction sends 16-bit word where last bits contain contents USER3 location. command ensures device returns idle power dissipation state.
OFFSET BIAS
Figure Inverting Gain Test Circuit
-14-
REV.
AD5232
OP279 OFFSET VOUT
Endurance quantifies ability Flash/EE memory cycled through many Program, Read, Erase cycles. real terms, single endurance cycle composed four independent, sequential events. These events defined Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence During reliability qualification Flash/EE memory cycled from until first fail recorded, signifying endurance limit on-chip Flash/EE memory.
OFFSET BIAS
Figure Noninverting Gain Test Circuit
OFFSET +15V 2.5V OP42 VOUT
-15V
Figure Gain Frequency Test Circuit
0.1V CODE 0.1V
indicated specification pages this data sheet, AD5232 Flash/EE Memory Endurance qualification been carried accordance with JEDEC Specification A117 over industrial temperature range -40°C +85°C. results allow specification minimum endurance figure over supply temperature 100,000 cycles, with endurance figure 700,000 cycles being typical operation 25°C. Retention quantifies ability Flash/EE memory retain programmed data over time. Again, AD5232 been qualified accordance with formal JEDEC Retention Lifetime Specification (A117) specific junction temperature 55°C). part this qualification procedure, Flash/EE memory cycled specified endurance limit described above, before data retention characterized. This means that Flash/EE memory guaranteed retain data full-specified retention lifetime every time Flash/EE memory reprogrammed. should also noted that retention lifetime, based activation energy will derate with shown Figure
Figure Incremental Resistance Test Circuit
CONNECT
RETENTION Years
Figure Common-Mode Leakage Current Test Circuit
RDAC2 RDAC1
TYPICAL PERFORMANCE
VOUT
Figure Analog Crosstalk Test Circuit
Flash/EEMEM Reliability
JUNCTION TEMPERATURE
Flash/EE Memory array AD5232 fully qualified Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance Flash/EE Memory Data Retention.
Figure Flash/EE Memory Data Retention
REV.
-15-
AD5232-Typical Performance Characteristics
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 DIGITAL CODE 2.7V
2000
RHEOSTAT MODE TEMPCO ppm/
C/+85 1500 CONNECT MEASURED
IINL ERROR
1000
CODE Decimal
Code, Overlay
RWB/T Code
2.00 POTENTIOMETER MODE TEMPCO ppm/ 1.75 1.50 1.25 ERROR 1.00 0.75 0.50 0.25 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 DIGITAL CODE 2.7V
C/+85 2.00V
CODE Decimal
Code, Overlay
VWB/T Code
0.20
5.5V, +2.5V -2.5V FIGURE
0.15
0.10
R-DNL
0.05
0.00
-0.05 -0.10
0.01
-0.15 -0.20
CODE Decimal
0.001
TEMPERATURE
R-DNL Code Overlay
Temperature
-16-
REV.
AD5232
5.5V
f-3dB 500kHz,
GAIN
f-3dB 45kHz, 100k
f-3dB 95kHz,
100mV +2.5V, -2.5V 100k FREQUENCY
2.7V
TEMPERATURE
Temperature
Bandwidth Resistance
FILTER 22kHz
NOISE
0.01
100k
0.001
FREQUENCY
100k
Time (Save) Program Mode
Total Harmonic Distortion Frequency
2.7V
CODE
Time Read Mode
Wiper On-Resistance Code
REV.
-17-
AD5232
DATA DATA
100k
PSRR REJECTION
DATA DATA DATA DATA
GAIN
DATA +2.7V -2.7V 100mV 100k FREQUENCY- DATA
5.5V 100mV MEASURE WITH CODE 100k
FREQUENCY
Gain Frequency Code,
PSRR Frequency
ANALOG CROSSTALK REJECTION
DATA DATA DATA DATA DATA DATA
100k
GAIN
DATA +2.7V -2.7V 100mV 100k FREQUENCY DATA
+2.75V -2.75V +2.5VP
TEST CIRCUIT, FIGURE FREQUENCY
Gain Frequency Code,
DATA DATA DATA DATA DATA DATA DATA +2.7V -2.7V 100mV 100k FREQUENCY DATA
Analog Crosstalk Frequency
GAIN
100k
Gain Frequency Code,
-18-
REV.
AD5232
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE Number Terminal Part Voltage Number Package Range AD5201 +5.5 Interface Nominal Data Resistance Control 3-wire Resolution (Number Wiper Positions) Power Supply Current (IDD)( Packages µSOIC-10
Comments Full Specs, Dual Supply, Pwr-On-Reset, Cost Rollover, Pwr-On-Reset Single Dual Supply Operation Full Specs, Dual Supply, Pwr-On-Reset Full Specs Operation, ppm/°C Compatible, ppm/°C Nonvolatile Memory, Direct Program, I/D, Settability Rollover, Stereo, Pwr-On-Reset, ppm/°C Full Specs, Shutdown Current Full Specs, Dual Supply, Pwr-OnReset, Nonvolatile Memory, Direct Program, I/D, Settability Nonvolatile Memory, Direct Program, ppm/°C Compatible, ppm/°C Operation, ppm/°C Full Specs, Shutdown Current Nonvolatile Memory, Direct Program, I/D, Settability Full Specs, Dual Supply, Pwr-On-Reset Full Specs, Shutdown Current Full Specs, Dual Supply, Pwr-On-Reset
AD5220 AD7376
+5.5
DOWN 3-wire
100, 1000
AD5200
3-wire
PDIP, SO-8, µSOIC-8 PDIP-14, SOL-16, TSSOP-14 µSOIC-10
AD8400 AD5260
+5.5 ±2.75, +5.5 +5.5
3-wire 3-wire
SO-8 TSSOP-14
AD5241 AD5231
2-wire 3-wire
100, 1000
1024
SO-14, TSSOP-14 TSSOP-16
AD5222
DOWN 3-wire 3-wire
100, 1000
SO-14, TSSOP-14 PDIP, SO-14, TSSOP-14 TSSOP-14
AD8402 AD5207
+5.5 ±2.75, +5.5 ±2.75, +5.5 +5.5
AD5232
3-wire
TSSOP-16
AD5235*
3-wire
1024
TSSOP-16
AD5242 AD5262*
2-wire 3-wire
100, 1000
SO-16, TSSOP-16 TSSOP-16
AD5203 AD5233
±2.75, +5.5 +5.5
3-wire 3-wire
PDIP, SOL-24, TSSOP-24 TSSOP-16
AD5204
3-wire
PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24
AD8403 AD5206
+5.5
3-wire 3-wire
*Future Product, consult factory latest status. Latest Digital Potentiometer Information located
REV.
-19-
AD5232
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10)
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-20-
REV.
PRINTED U.S.A.
C02618-1-10/01(0)

8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232 SERIAL

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