High-Density Embedded Programmable Logic Devices System-Level Integrat

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High-Density Embedded Programmable Logic Devices System-Level Integrat

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APEX Devices
High-Density Embedded Programmable Logic Devices System-Level Integration
20KC APEXaturing
Coppe Layer Allonn Interc
January 2001
APEXprogrammable logic devices provide flexibility high density needed system-on-a-programmable-chip (SOPC) applications. MultiCorearchitecture combines benefits look-up table logic with embedded memory, saving board space simplifying complex system design. APEX devices also offer True-LVDSdedicated circuitry 840-Mbps data transfer rates, fastest industry. APEX 20KC devices, manufactured using all-layer copper interconnect technology, feature increased performance address high-bandwidth needs communications applications.
APEX: Revolutionary Embedded Architecture
Altera® APEXdevice family offers complete system-level integration single device. With innovative MultiCorearchitecture, APEX family combines enhances strengths previous programmable logic device (PLD) architectures delivers ultimate design flexibility efficiency high-performance, system-on-aprogrammable-chip (SOPC) applications. APEX 20KC devices manufactured 0.15 all-layer copper interconnect technology address high-density, high-performance needs communication applications.
APEX Device Features
MultiCore Architecture Memory Embedded System Block (ESB) Dual-Port
Features LVDS SSTL-2/-3 GTL+ HSTL LVPECL MultiVolt Clock Management PLLs ClockShift Circuitry ClockBoost Circuitry ClockLock Circuitry
Breakthrough MultiCore Architecture
With densities ranging from 30,000 over million gates (113,000 over million maximum system gates) performance enhancements from copper interconnect technology, multiple phase-locked loops (PLLs), this family designed 64-bit, 66-MHz PCI-X compliant. With APEX True-LVDS circuitry, this family achieve data transfer rates Mbps. 2.5-V APEX devices fabricated advanced 0.22-µm, six-layer-metal SRAM process. 1.8-V APEX 20KE devices, which functional superset APEX devices, utilize 0.18-µm, eight-layer-metal process. 1.8-V all-layer copper APEX 20KC devices fabricated 0.15-µm, eight-layer-metal process. innovative APEX MultiCore architecture contains types structures: look-up-table (LUT) logic FLEX® FLEX 6000 devices enhanced embedded memory blocks FLEX 10KE devices. Both structures combined into single integrated architecture, eliminating need multiple devices, saving board space, simplifying implementation complex designs. MultiCore architecture introduces level hierarchy called MegaLABstructure. Each MegaLAB structure contains logic array blocks (LABs) that consist logic elements, each which used implement logic, advanced embedded structure called embedded system block (ESBs). MegaLAB local interconnect ties LABs ESBs together without using valuable global routing resources. MegaLAB structures connected FastTrackAPEX 20KC
All-Layer Copper
Improved Performance with APEX 20KC Devices
Interconnect continuous routing structure fast, predictable delays.
Performance
APEX 20KE
Aluminum
APEX
Aluminum
FLEX 10KE
Aluminum
0.25-µm 6-layer metal
0.22-µm 6-layer metal
0.18-µm 8-layer metal
0.15-µm 8-layer metal
Process Metal Layers
Altera Corporation
APEX Highlights
Feature
840-MHz data rates All-layer copper interconnect MultiCore architecture Embedded system block (ESB) compliance Support emerging standards SignalTap® logic analysis Density million gates (2.4 million system gates) 1.8-V 2.5-V operation four phase-locked loops (PLLs) Reduces power consumption Supports ClockLockTM, ClockBoostTM, ClockShiftcircuitry, 160x clock multiplication, clock division with extended frequency range MultiVolt operation FineLine BGApackaging Ideal mixed-voltage systems Area-optimized, better thermal characteristics, high-pin-count offerings packaging migration flexibility Vertical migration Addresses changing density without need re-spin board
Benefit
High-speed interface provide true system-level programmable solution Improves performance over 0.18 aluminum-based devices Integrates logic memory into single architecture Implements dual-port RAM, first-in first-out (FIFO), ROM, Meets specifications 64-bit, 66-MHz compliance PCI-X support Supports LVDS, LVTTL, LVCMOS, GTL+, CTT, AGP, HSTL, LVPECL, SSTL-2/-3 standards Improves verification chip functionality Addresses system-level density needs
APEX 20KC Device Features (1.8
Device
Maximum system gates Logic elements Maximum bits Phase-locked loops (PLLs) Speed grades
Notes:
EP20K100C
263,000 4,160 53,248
EP20K200C
526,000 8,320 106,496
EP20K400C
1,052,000 16,640 212,992
EP20K600C
1,537,000 24,320 311,296
EP20K1000C
1,772,000 38,400 327,680
EP20K1500C
2,392,000 51,840 442,368
fastest speed grade APEX 20KC family.
APEX 20KE Device Features (1.8
Device
Maximum system gates Logic elements Maximum bits Phase-locked loops (PLLs) Speed grades1 Maximum user pins Package 144-Pin TQFP2 144-Pin FineLine BGA3 208-Pin PQFP4 240-Pin PQFP 324-Pin FineLine 356-Pin 484-Pin FineLine 652-Pin 672-Pin FineLine 1,020-Pin FineLine "F33"
Notes:
EP20K30E EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
113,000 1,200 24,576 162,000 2,560 32,768 263,000 4,160 53,248 404,000 6,400 81,920 526,000 8,320 106,496
728,000 11,520 147,456
1,052,000 16,640 212,9924
1,537,000 24,320 311,296
1,772,000 38,400 327,680
2,392,000 51,840 442,368
Maximum User Pins
fastest speed grade APEX APEX 20KE families TQFP: thin quad flat pack BGA: ball-grid array PQFP: plastic quad flat pack
Altera Corporation
APEX Device Features (2.5
Device
Maximum system gates Logic elements Maximum bits Phase-locked loops (PLLs) Speed grade Maximum user pins Package 144-Pin TQFP 144-Pin FineLine 208-Pin PQFP 240-Pin PQFP 324-Pin FineLine 356-Pin 484-Pin FineLine 652-Pin 672-Pin FineLine
commonly used data communication
EP20K200
526,000 8,320 106,496
EP20K100
263,000 4,160 53,248
EP20K400
1,052,000 16,640 212,992
applications. Because APEX 20KE APEX 20KC functions high-speed parallel comparator, opens many applications designs. APEX supports single match, multiple match, fast multiple match, ternary CAM. Each configured 32-word 32-bit CAM, ESBs cascaded build larger CAMs. integrated APEX 20KE APEX 20KC devices offers considerable gains system performance configuration flexibility relative discrete solutions.
Maximum User Pins
High-Bandwidth, Low-Voltage
demand higher system performance lower supply voltages growing. APEX 20KE APEX 20KC devices support multiple interfacing standards, including LVTTL, LVCMOS, GTL+, SSTL-3/2, HSTL, AGP, CTT, LVPECL, LVDS with performance Mbps. APEX devices support Altera MultiVoltI/O
Applications
Address translation Cache tagging filtering address look-up Packet header identification Pattern recognition Switch address mapping VPI/VCI translation Aswitches
interface, which ideal mixed-voltage systems.
Enhanced Phase-Locked Loop
increase system-clock rates, APEX 20KE APEX 20KC devices feature four PLLs with enhanced ClockLockTM, ClockBoostTM, ClockShiftcircuitry. ClockLock circuitry uses synchronizing with extended frequency range that reduces clock delay skew within device. ClockBoost circuitry provides clock multiplier that allows designer distribute low-speed clock multiply that clock device. also allows resourcesharing within device enhances device area efficiency. ClockShift circuitry provides programmable clock delay phase-shift capability.
Embedded System Block Configuration
Embedded system blocks heart MultiCore architecture. 2,048 programmable bits each APEX configured dual-port RAM, ROM, content-addressable memory (CAM). Embedded Dual-Port APEX ESBs support dual-port with independent read/write ports, synchronous asynchronous operation, high-speed first-in first-out (FIFO) performance wide range widths depths (128 1,024 2,048 APEX ESBs also support 225-MHz cache performance performance over MHz. Multiple ESBs combined build wider deeper memories. High-Performance Within APEX 20KE APEX 20KC devices, ESBs configured CAM, parallel processing memory that facilitates fast address search functions. operates like reverse RAM: while receives address input supplies data output, receives data input supplies address that contains input data.
High-Bandwidth True-LVDS Support
APEX 20KE APEX 20KC interface meets Mbps data transfer rate specifications supports data transfer rates Gbps under laboratory conditions. With dedicated built-in True-LVDS circuitry, APEX 20KE APEX 20KC LVDS supports programmable bandwidths Gbps. APEX devices offer highest performance, highest bandwidth SOPC solution high-speed data transmission designs.
Altera Corporation
APEX 20KE LVDS Running Gbps Data Transfer Rate*
Aluminum Copper Delays
Relative Interconnect Delays
1.00
0.30
0.15-µm, Aluminum
0.15-µm, Copper
Interconnect Material
performance improvements. Copper also more scalable than aluminum, resulting smaller size, enhanced internal performance speed. APEX 20KC devices range density from
*Data taken under laboratory conditions.
100,000 million system gates (263,000 milliion maximum system gates) with embedded memory ranging from 53,248 442,368 bits. Three speed grades (-7, represent faster performance these devices.
Greater Performance with All-Layer Copper Interconnect
APEX 20KC devices offer improved internal performance address high-density, highperformance needs communication applications. With internal performance improvements transmission speeds Mbps, these devices ideal applications such OC-192 SONET protocol, well gigabit Ethernet applications. APEX 20KC devices build state-of-the-art features offered industry-leading APEX 20KE devices. Combined with revolutionary MultiCore architecture, wide density range, advanced FineLine package offering four PLLs multiple userselectable I/Os, APEX 20KC devices provide even greater system-level integration. Copper technology replaces aluminum APEX 20KC devices routing structure performance enhancements. Copper resistivity better electro-migration characteristics, making best-known electrical conductors. Interconnect delays lower than aluminum delays, which translates significant core
Intellectual Property Quartus Development Tool Simplify Design
Altera's Quartusdevelopment tool allows designers process multi-million gate designs using advanced features development tools. streamline development flow increase productivity, Quartus software supports system-level solutions, schematic block-level editing, integrates with standard revision control software. Quartus software allows designers implement advanced device features such CAM, PLL, LVDS, integrate intellectual property (IP) megafunctions easily. SignalTap logic analysis tool reduces verification time enabling engineers internal chip signal values while system running speed. Enhanced timing analysis tools support designs with single multiple clocks well designs with multicycle paths. PowerFitfitting technology optimizes designs based user's timing specifications meets design requirements with only minimal user effort. Quartus software uses
Altera Corporation
SignalTap Logic Analysis Tool
Download Cable Quartus Software
NativeLinkintegration seamlessly interface with third-party software tools, "Internet-aware," providing up-to-the-minute information file exchanges, software updates, support services through Internet. Together these features make Quartus software ideal platform multi-million gate designs.
Contact Altera Today
APEX device family provides level capability offers platform system-on-aprogrammable-chip applications. revolutionary MultiCore architecture brings together power logic embedded memory system-level integration. Call Altera today learn more about this multi-milliongate programmable logic family visit Altera world-wide site http://www.altera.com.
Altera Corporation
Programmable Solutions Company
Altera Offices
Altera Corporation Innovation Drive Jose, 95134 Tel: (408) 544-7000 http://www.altera.com Altera U.K., Ltd. Holmers Farm High Wycombe, Buckinghamshire HP12 Tel: (44) Altera Japan, Ltd. Shinjuku i-Land Tower 5-1, Nishi-Shinjuku, 6-Chome Shinjuku-ku, Tokyo 163-1332 Japan Tel: (81) 3340 9480 http://www.altera.com/japan Altera International, Ltd. Suites 908-920, Tower MetroPlaza Hing Fong Road Kwai Fong, Territories Hong Kong Tel: (852) 2487 2030
Copyright 2000 Altera Corporation. Altera, APEX, APEX 20K, APEX 20KC, APEX 20KE, ClockLock, ClockBoost, ClockShift, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 6000, MegaLAB, MultiCore, MultiVolt, NativeLink, Quartus, SignalTap, True-LVDS, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved. M-GB-APEX20K-04

High-Density Embedded Programmable Logic Devices System-Level Integrat

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