Low-Cost Solutions High Volume Applications look-up table (LUT)-b

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Low-Cost Solutions High Volume Applications look-up table (LUT)-b

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ACEX Devices
Low-Cost Solutions High Volume Applications
look-up table (LUT)-based ACEXprogrammable logic device (PLD) family provides value performance costsensitive, volume-driven applications. These devices ideal communications consumer marketplaces applications such cable modems, xDSL modems, low-cost switches, routers. ACEX devices have low-cost advantages application-specific integrated circuits (ASICs) application-specific specialized products (ASSPs), with added benefits fast time-to-market programmable flexibility. ACEX devices offer in-circuit reconfigurability (ICR), eliminating costly delays allowing designers quickly implement complete design revisions. These devices supported Altera's powerful development software preoptimized, drop-in intellectual property megafunctions, further reducing time-to-market. Products designed, revised, released, updated with minimal complications delays.
advanced packaging technologies. ACEX devices support phase-locked loop (PLL) circuitry drive separate ClockLockTM- ClockBoostTMgenerated signals extensive clock management capability.
High Performance, Cost
High performance, integral volume-driven telecommunications products, requires delicate balance between performance price. ACEX devices meet these requirements. Despite their price points, system performance ACEX devices reach speeds over with minimal intervention. Advanced software fitting techniques place route designs, achieving accelerated design performance within ACEX interconnect architecture.
Cutting-Edge ACEX Family
ACEX family, which based advanced cost-optimized 2.5-V SRAM process, ranges from 10,000 100,000 gates. next-generation ACEX family, ACEX family, will offer densities ranging from 30,000 160,000 gates. Additionally, ACEX family will support wide range specialized standards, enabling effective highspeed, board-level communications. Operating ACEX devices fully 64-bit, 66-MHz compliant feature embedded dual-port
ACEX Devices
DEVICE
EP1K10 EP1K30 EP1K50 EP1K100
GATES
10,000 30,000 50,000 100,000
PIN/PACKAGE OPTIONS
100-Pin TQFP1, 144-Pin TQFP1, 208-Pin PQFP2, 256-Pin BGA3 144-Pin TQFP1, 208-Pin PQFP2, 256-Pin BGA3 144-Pin TQFP1, 208-Pin TQFP1, 256-Pin BGA3, 484-Pin BGA3 208-Pin TQFP1, 256-Pin BGA3, BGA3
PINS
102, 130, 102, 147, 102, 147, 186, 147, 186,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,728 2,880 4,992
BITS
12,288 24,576 40,960 49,152
SPEED GRADES
Notes:
Plastic thin quad flat pack. Plastic quad flat pack. Space-saving FineLine BGApackage.
Altera Corporation
ACEX Cost Performance
Opportunity Cost
Altera ACEX PLDs require charges associated with ASICs. ASIC development also introduces unforeseeable opportunity costs risks, including respins that result additional expenses protracted development effort, leading lost revenue smaller market opportunity.
Total Cost
elop
Versatile Memory Blocks Embedded Functions
embedded array blocks (EABs) ACEX devices flexible blocks memory that support variety functions, including dual-port with independent read/write ports, synchronous/asynchronous operation, high performance first-in first-out (FIFO) buffers. Complex memory-intensive designs implemented single ACEX device without routing timing performance degradation, often case with devices that feature smaller, segmented structures. resource optimization, size individual EABs tailored suit design requirements, covering range widths depths. Larger aggregate structures implemented memory-intensive functions that require larger blocks transparently cascading adjacent EABs. EABs ACEX devices also used more than just on-chip memory-they implement specialized arithmetic functions such multipliers, arithmetic logic units, sequencers more efficiently than traditional logic array, making microprocessors, microcontrollers, complex digital signal processing functions reality.
Development Cost
Cost
Cost
ACEX
ASICs
Total Cost: PLDs ASICs
ACEX family-as well PLDs-offers cost leadership over traditional ASICs. Design costs, development costs, non-recurring engineering (NRE) charges, lost opportunity costs combine make total cost ASIC design higher than cost Altera's ACEX solution. ASIC development costs, including costs engineering resources development tools, significant. Traditional ASIC development requires increased engineering resources perform software verification silicon verification, both time- resource-intensive tasks. With pre-verified silicon, PLDs offer lower engineering resource requirements faster-time-to-market customer designs.
ACEX Performance
APPLICATION
16-bit loadable counter 16-bit read cycle speed1 16-bit, 8-tap parallel finite impulse response (FIR) filter
RESOURCES USED
PERFORMANCE
Speed Grade
UNITS
Speed Grade
MSPS2
EABs
Speed Grade
Note: This application uses registered inputs outputs. Million samples second.
Altera Corporation
Value Proposition
Criteria
Costs Fast Development Time Fast Time-to-Market Easy Customization High Flexibility Product Upgrades
ASIC
ASSP
ACEX
between Altera third-party megafunction developers. Together, Altera's MegaCore AMPP functions cover wide range applications simplify complex design tasks, dramatically shorten design cycles, provide results that extend performance programmable logic solutions.
Advanced Development Software Support
Altera's design flow equips ACEX developers with powerful, easy-to-use tool, MAX+PLUS® development tool, that contributes overall reduction design cycle times. Advanced fitting techniques ensure optimal placement routing, culminating maximized system performance. Seamless integration with synthesis simulation software from leading vendors well stateof-the-art intellectual property cores allow take advantage full potential ACEX devices minimal cost.
Phase-Locked Loop Clock Management
Phase-locked loop (PLL) circuitry clock management available ACEX devices increased clock performance flexibility. ClockLock ClockBoost features permit advanced clock manipulation, efficiently reducing effects external board delay internal device skew while improving input/output timing performance. PLLs provide significant improvements overall system performance design versatility, resulting optimized resource usage enhanced clock functionality.
Contact Altera Today
ACEX devices ultimate combination highperformance programmable logic technology with industry-leading, cost-effective price points. advanced process technology extensive feature set, coupled with significant pricing advantages commitment technological excellence, resulted unprecedented value high-volume marketplace. Call Altera today learn more about revolutionary ACEX device family visit Altera site http://www.altera.com.
Intellectual Property Support Complex Functions
further reduce design times, Altera offers variety pre-built functional blocks, called megafunctions, that optimized ACEX architecture. These off-the-shelf megafunctions simplify complex design tasks dramatically shorten design cycles. Altera offers both Altera-developed MegaCore functions functions developed through Altera Megafunction Partners Program (AMPPSM), alliance
Altera Offices Altera Corporation Innovation Drive Jose, 95134 Telephone: (408) 544-7000 http://www.altera.com
Altera European Headquarters Holmers Farm High Wycombe Buckinghamshire HP12 United Kingdom Telephone: (44)
Altera Japan Ltd. Shinjuku i-Land Tower 5-1, Nishi-Shinjuku, 6-Chome Shinjuku-ku, Tokyo 163-1332 Japan Telephone: (81) 3340 9480 http://www.altera.com/japan
Altera International Ltd. Suites 908-920, Tower MetroPlaza Hing Fong Road Kwai Fong, Territories Hong Kong Telephone: (852) 2487 2030
Copyright 2000 Altera Corporation. Altera, ACEX, ACEX ACEX AMPP, ClockBoost, ClockLock, FineLine BGA, MAX, MAX+PLUS, MAX+PLUS MegaCore, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved. M-GB-ACEX-01

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