APEX Devices Application Note October 2001, ver. Introd

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APEX Devices Application Note October 2001, ver. Introd

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Using ClockLock ClockBoost Features
APEX Devices
Application Note
October 2001, ver.
Introduction
APEX20K devices have ClockLockand ClockBoostfeatures, which phase-locked loops (PLLs) increase performance provide clock-frequency synthesis. ClockLock feature minimizes clock delay clock skew within device, reducing clock-to-output setup times while maintaining zero hold times. ClockBoost feature allows designers internal logic device faster slower rate than input clock frequency. This technique simplifies board design because clock tree board does have distribute high-speed signal. Through time-domain multiplexing, ClockBoost feature allows designer improve device area efficiency sharing resources within device. APEX 20KE devices include PLLs with enhanced ClockLock feature set, such advanced ClockBoost capability m/(n multiplication, LVDS support, external clock outputs feedback ability, ClockShiftcircuitry more complex clock-frequency synthesis applications. These enhanced features permit system-level clock management skew control APEX 20KE devices. ClockLock ClockBoost features provide significant improvements system performance, bandwidth, system-on-aprogrammable-chip (SOPC) integration. This application note explains APEX APEX 20KE ClockLock ClockBoost features also describes common applications these features.
Clock Delay Skew
delay from clock register, especially large devices, significant enough degrade both off-chip performance. Figure shows equation pin-to-pin clock-to-output delay (tCO). clock delay (tCLOCK) clock skew (tSKEW) parameters account significant portion total clock-to-output delay larger devices. reducing clock delay clock skew, ClockLock ClockBoost circuitry improves device's clock-to-output times.
Altera Corporation
A-AN-115-2.2
115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX APEX 20KE Hold, Setup Clock-to-Output Times
data1 clock Clock Delay Data Delay Output Delay
Skew
data2
Data Delay
Output Delay
tREG_H tCLOCK tSKEW tDATA tREG_SU tDATA tCLOCK tSKEW tCLOCK tSKEW tREG_CO tOUTPUT
Clock skew-the difference between clock delays different registers- also increases setup time indirectly. ensure zero hold time (tH), data delay account longest clock delay register. This delay must long enough ensure zero hold time under fast process, voltage, temperature conditions. However, added data delay also increases register's setup time under slow process, voltage, temperature conditions. When ClockLock signal feeds register, signal bypasses data delay element register, resulting decreased setup time. Because clock skew delay reduced, register maintains zero hold time. programmable logic devices (PLDs) become larger, clock delay skew become problem. Clock skew also affect board's design. address these issues, designers either PLLs delay-locked loops (DLLs). Although both reduce skew within system clocks, PLLs more flexible than DLLs frequency synthesis system clocks. addition, DLLs capable performing non-integer scaling, they cannot attenuate input jitter. DLLs, input jitter propagates output accumulates when DLLs cascaded. Because PLLs perform non-integer scaling, they ideal clock multiplication division applications.
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115: Using ClockLock ClockBoost Features APEX Devices
Table shows ClockLock features APEX APEX 20KE devices. Table APEX APEX 20KE ClockLock Features Device Number PLLs ClockBoost Feature Note LVDS LVDS Clock Data
T1/E1 Number Number ClockShift Conversion External Feedback Inputs Clock Outputs
EP20K100 EP20K200 EP20K400 EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E Notes:
m/(n (2),
m/(n (2), m/(n (2), m/(n (2), m/(n (2), m/(n (2), m/(n (2),
APEX devices that support ClockLock ClockBoost features denoted suffix ordering code (e.g., EP20K400FC672-1X). integer that ranges from 160. quantity range from 280. special multiplication rate also provided frequency conversion (i.e., 256/193), frequency conversion (i.e., 193/256). EP20K300E device supports LVDS data transfer megabits second (Mbps).
APEX Devices
APEX devices have that features ClockLock ClockBoost circuitry. This instantiated using altclklock megafunction. APEX devices support ClockBoost multiplication circuitry, offering clock multiplication. Figure shows ClockLock ClockBoost circuitry block diagrams within altclklock megafunction ports.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Figure ClockLock ClockBoost Circuitry APEX Devices
Phase Comparator
Voltage-Controlled Oscillator
clock0
inclock
ClockBoost clock1
altclklock Megafunction
Note:
This division used only purpose dividing down clock1 obtain clock0.
single output clock combination output clocks. Table describes clock multiplication combinations that altclklock megafunction supports APEX devices. Table APEX Multiplication Factor Combinations Clock
Clock
Input Frequency (MHz) Speed Grade
Speed Grade
dedicated clock (CLK2) supplies clock altclklock megafunction. Adhere following guidelines when using altclklock megafunction APEX devices:
inclock port must only directly dedicated clock input (CLK2) without inversion. altclklock only used clock positive negative edgetriggered registers logic elements (LEs), elements (IOEs), embedded system blocks (ESBs). registers only have single clock polarity from given altclklock output (i.e., registers must positive-edge triggered negative-edge triggered). both clock polarities needed IOE, outputs. CLK2 that directly feeds inclock port also drive other registers without PLL. However, doing makes CLK1 clock1 port unavailable. When outputs used, other clock (CLK1) cannot used.
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115: Using ClockLock ClockBoost Features APEX Devices
should connect board clock trace only CLK2 designs that require outputs from altclklock megafunction. Figure illustrates valid clock connections global clock lines. Figure APEX Dedicated Global Clock Connections Dedicated Clock Lines
Dedicated Clocks
CLK2
inclock
clock1
clock0 CLK1
Table shows timing parameters APEX ClockLock ClockBoost features speed-grade devices Table shows timing parameters APEX ClockLock ClockBoost features speed-grade devices. Table APEX ClockLock ClockBoost Parameters Speed-Grade Devices (Part Symbol
fOUT fCLK1
Parameter
Output frequency Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input duty cycle Duty cycle ClockLock/ClockBoost-generated clock Input deviation from user specification Quartus software (ClockBoost clock multiplication factor equals Input rise time
Unit
fCLK2 fCLK4 tINDUTY tOUTDUTY
fCLKDEV
25,000
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Table APEX ClockLock ClockBoost Parameters Speed-Grade Devices (Part Symbol
tLOCK
Parameter
Input fall time Time required ClockLock/ClockBoost acquire lock Skew delay between related ClockLock/ClockBoost-generated clocks Jitter ClockLock/ClockBoostgenerated clock Input clock stability (measured between adjacent clocks)
Unit
tSKEW
tJITTER tINCLKSTB
Notes:
input frequency range EP20K100-1X device multiplication MHz. input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. During device configuration, ClockLock ClockBoost circuitry configured first. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration, because lock time less than configuration time. jitter specification measured under long-term observation. input clock stability tJITTER
Table APEX ClockLock ClockBoost Parameters Speed -Grade Devices (Part Symbol
fOUT CLK1 CLK2 CLK4 OUTDUTY CLKDEV
Parameter
Output frequency Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Duty cycle ClockLock/ClockBoostgenerated clock Input deviation from user specification Quartus software (ClockBoost clock multiplication factor equals one)
25,000
Unit
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Table APEX ClockLock ClockBoost Parameters Speed -Grade Devices (Part Symbol
LOCK
Parameter
Input rise time Input fall time Time required ClockLock/ ClockBoost acquire lock Skew delay between related ClockLock/ ClockBoost-generated clock Jitter ClockLock/ ClockBoostgenerated clock Input clock stability (measured between adjacent clocks)
Unit
SKEW
JITTER INCLKSTB
Notes:
implement ClockLock ClockBoost circuitry with Quartus software, designers must specify input frequency. Quartus software tunes ClockLock ClockBoost circuitry this frequency. fCLKDEV parameter specifies much incoming clock differ from specified frequency during device operation. Simulation does reflect this parameter. 25,000 parts million (PPM) equates 2.5% input clock period. During device configuration, ClockLock ClockBoost circuitry configured before rest device. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration because tLOCK value less than time required configuration. tJITTER specification measured under long-term observation.
Table lists APEX ClockLock pins their functions. Table APEX Device ClockLock Pins Name
CLK2 LOCK
Type
Input Output
Description
Dedicated that drives ClockLock ClockBoost circuitry. Optional that shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high long clock input remains within specification.
Standards Supported
2.5-V I/O, LVCMOS, LVTTL, 3.3-V PCI, CMOS (2),
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices Notes:
PCI: peripheral component interconnect. APEX devices with suffix their ordering code 5.0-V tolerant.
APEX 20KE Devices
APEX 20KE devices incorporate multiple ClockLock circuits with advanced features. These features include ClockLock circuitry, advanced ClockBoost circuitry, LVDS support, ClockShift circuitry, external clock outputs with optional external feedback inputs.
Advanced ClockBoost Multiplication Division
Each APEX 20KE includes circuitry that provides clock synthesis outputs using m/(n m/(n scaling factors. When locked, locked output clock aligns rising edge input clock. closed loop equation Figure gives output frequency fCLOCK0 (m/(n fCLOCK1 (m/(n v))fIN. This equation allows multiplication division clocks programmable number. Quartus software automatically chooses appropriate scaling factors according frequency, multiplication, division values entered. scaling multiplication APEX 20KE PLLs allows wide range user-defined multiplication division ratios that possible with DLLs. example, frequency scaling factor 3.75 needed given input clock, enter multiplication factor division factor four. Because this advanced ClockBoost scaling performed with single PLL, need cascade outputs. APEX 20KE PLLs capable converting between clock frequencies. telecommunications standard uses 1.544-MHz clock, telecommunications standard uses 2.048-MHz clock. APEX 20KE PLLs convert frequency frequency vice versa.
LVDS Interface
EP20K400E larger devices, ClockLock PLLs (PLL3 PLL4) configured LVDS transmitter receiver interfaces. When configured LVDS, clock multiplied support high-speed data transfer rates convert between LVDS CMOS data. These PLLs interface with APEX 20KE LVDS receiver LVDS transmitter blocks.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
When used LVDS transmitter receiver modes, PLLs connections shown Figure These modes require ALTLVDS megafuntion.
Application (Using LVDS APEX 20KE Devices) more information LVDS.
External Clock Outputs
EP20K300E larger devices, low-jitter external clocks, CLKLK_OUT1P CLKLK_OUT2P, available external clock sources. EP20K30E, EP20K60E, EP20K100E, EP20K160E, EP20K200E devices, external clock, CLKLK_OUT2P, available external clock source. CLKLK_OUT1P signal originates from CLKLK_OUT2P signal originates from Other devices board these outputs clock sources. External clock outputs available three modes:
Zero Delay Buffer-The external clock output phase aligned with clock input zero delay. Phase shift allowed this configuration. Clock division possible external clock output this configuration. Multiplication possible remaining output that driven off-chip. altclklock megafunction's MegaWizard® Plug-In should used verify possible clock settings. External Feedback-The external feedback input phase aligned with clock input pin. aligning these clocks, actively remove clock delay skew between devices. This mode same restrictions zero delay buffer. Normal Mode-The external clock output will have phase delay relative clock input pin. internal clock used this mode, will phase aligned input clock pin.
ClockShift Circuitry
APEX 20KE PLLs have ClockShift circuitry that provides programmable clock delay phase shift. user enters desired phase shift. Phase shifts 90°, 180°, 270° implemented exactly. Other phase shift delay shift values time units) available with resolution range. This resolution varies with frequency input user-entered multiplication division factors. ClockShift circuitry only used multiplied divided clock input output frequency have integer multiple relationship (i.e., fIN/fOUT fOUT/fIN must integer). ClockShift circuitry only available Normal mode.
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115: Using ClockLock ClockBoost Features APEX Devices
Clock Enable Signal
APEX 20KE PLLs have CLKLK_ENA enabling disabling device PLLs. When CLKLK_ENA high, drives clock0 clock1 ports. When CLKLK_ENA low, clock0 clock1 ports driven PLLs lock. When CLKLK_ENA goes high again, must relock. individual enable port altclklock megafunction all-or-none control signal. enable port used altclklock instance, other instances must enable port connect same pin. port used, connected enable ports must CLKLK_ENA dedicated pin. inclocken input port altclklock megafunction should used designs. CLKLK_ENA control needed designer, must brought CLKLK_ENA input pin. Quartus software automatically assigns location this dedicated function pin. CLKLK_ENA control needed user Zero Delay Buffer Normal modes, inclocken port should connected input design. board, this connected since will floating input. CLKLK_ENA control needed user External Feedback mode, inclocken port must connected input pin. board, user must connect this directly INIT_DONE pin. INIT_DONE option must Device Options Compiler Settings Chips Devices dialog (Processing menu). system control over CLKLK_ENA needed External Feedback mode, open-drain control signal used wire-ANDed configuration with open-drain INIT_DONE pin. Figure demonstrates this should connected.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Figure Wire-ANDing with Open-Drain INIT_DONE
CLKLK_ENA
INIT_DONE Optional Control Signal
Lock Signals
APEX 20KE ClockLock circuits support individual LOCK signals. LOCK signal drives high when locked onto input clock. LOCK remains high long input remains within specification. will input specification. When using clock outputs from PLL, outputs become valid different times. This difference caused difference divider ratios between outputs. LOCK optional each used APEX 20KE devices; when used, they pins. This signal available internally. this signal used design, must back with input pin. Before configuration, circuits disabled powered down. During configuration, PLLs disabled. When device goes into user mode, lock time measured from CLKLK_ENA rising edge LOCK rising edge. During device configuration, standard each been set. this reason, does lock during configuration. LOCK signal indication also separate programmable latency controls LOCK assertion deassertion. Users select multipliers, indicate small large latency. number half cycles indication dependent multiplication/division ratio input frequency. Depending these factors, latency ranges from half-clock cycles; high latency ranges from half-clock cycles. APEX 20KE ClockLock circuits (general purpose PLLs) instantiated using altclklock megafunctions. Figure shows ClockLock ClockBoost circuitry APEX 20KE devices.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure ClockLock ClockBoost Circuitry APEX 20KE Devices
Phase Comparator
Voltage-Controlled Oscillator clock0
inclock
ClockShift Circuitry fbin clock1
altclklock Megafunction
Each dedicated global clock pins EP20K300E, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices (CLK1P, CLK2P, CLK3P, CLK4P) supplies clock general purpose mode. Each altclklock instance represents single general-purpose instantiation. altclklock megafunction APEX 20KE devices must adhere following guidelines:
only directly dedicated clock input without inversion. altclklock only used clock positive negative edgetriggered registers LEs, IOEs, ESBs. registers only have single clock polarity from given altclklock output (i.e., registers must positive-edge triggered negative-edge triggered). both clock polarities needed IOE, outputs. allowable frequency input range MHz, depending standard (see Table allowable frequency output range clock0 MHz, depending standard external clock and/or internal frequency shown Table allowable frequency output range clock1 12.5 MHz, depending standard external clock and/or internal frequency shown Table Phase shifting only possible multiplied clock input output frequency have integer-multiple relationship (i.e., fIN/fOUT fOUT/fIN must integer). Phase shifting, using degree time units, will delay output clock with respect input clock (see Figure ratio clock_boost clock_divide cannot greater than 280. special scaling ratio 256/193 193/256 allowed T1/E1 E1/T1 clock rate conversion, respectively.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Phase Delay Shifting Using APEX 20KE PLLs
Several conditions exist that govern relationship between input frequency, phase shift values. altclklock MegaWizard Plug-In automatically sets dividers satisfy these equalities accommodate phase shift entered clock multiplication division. MegaWizard Plug-In verifies validity settings reports multiplication/division frequency ratio valid. Each driven dedicated clock bypassed simultaneously. CLK3P CLK4P pins feed PLLs each, altclklock instances. This capability useful applications that need both phase-shifted non-phase-shifted versions clock. Because eight outputs shared among four possible dedicated global clock lines, certain combinations multiple altclklock instances their output connections possible. Quartus software uses different PLLs (i.e., based assignments made dedicated global clock that feeds altclklock megafunction. Figure illustrates valid clock connections dedicated global clock lines these devices. This figure should used determine whether design clocking scheme valid terms APEX 20KE clock connections. example, EP20K400E device, CLK4P feed simultaneously; however, only single internal output from each used, because four possible outputs feed global clock lines.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Figure Dedicated Global Clock Connections Dedicated Clock Lines EP20K300E, EP20K400E, EP20K600E, EP20K1000E EP20K1500E Devices
Dedicated Clocks LVDSTXOUTCLK1p/n
tx_outclock PLL4 Transmitter Mode tx_inclock
rx_outclock rx_inclock PLL3 Receiver Mode
LVDSRXINCLK1p/n
LVDSTXINCLK1p/n
CLK4p
clock1 PLL4 General Purpose Mode clock0 inclock
PLL3 General Purpose Mode clock0 inclock
clock1
CLK3p
clock1 inclock CLK2p fbin CLKLK_FB2p CLKLK_OUT2p PLL2 clock0
clock1 PLL1 clock0 inclock CLK1p fbin
CLKLK_FB1p
CLKLK_OUT1p
Notes:
EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices, used only possible modes, general purpose mode ALTLVDS_TX transmitter mode. Connections that apply chosen mode shown above exclusive that mode. Only mode used time EP20K300E devices only used general purpose mode. EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices, used only possible modes, general purpose mode ALTLVDS_RX receiver mode. Connections that apply chosen mode shown above exclusive that mode. Only mode used time EP20K300E devices only used general purpose mode. This output high-speed CMOS/LVDS interface clock that feeds LVDS transmitter block. This output high-speed LVDS/CMOS interface clock that feeds LVDS receiver block.
EP20K30E, EP20K60E, EP20K100E, EP20K160E, EP20K200E devices, CLK4P CLK2P dedicated clock pins supply clock PLLs. These PLLs have same usage guidelines EP20K400E device larger device's PLLs, with exception some connections. four possible output clocks that shared among four dedicated clock lines. outputs, CLK3P CLK1P pins cannot used. Figure illustrates valid clock connections global clock lines these devices. Figure determine whether design clocking scheme valid terms clock connections. altclklock megafunction port connections should follow usage guidelines illustrated Figures
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Figure Dedicated Global Clock Connections Dedicated Clock Lines EP20K30E, EP20K60E, EP20K100E, EP20K160E EP20K200E Devices
Dedicated Clocks clock1 CLK4p inclock PLL2 clock0 CLK3p
clock1 inclock CLK2p fbin CLKLK_FB2p CLKLK_OUT2p PLL1 clock0 CLK1p
Table shows APEX 20KE ClockLock ClockBoost parameters, Table shows APEX 20KE Clock Input Output parameters.
Table APEX 20KE ClockLock ClockBoost Parameters Symbol
INDUTY INJITTER tOUTJITTER tOUTDUTY
Note
input period 0.35% output period
Parameter
Input rise time Input fall time Input duty cycle Input jitter peak-to-peak Jitter ClockLock ClockBoostgenerated clock Duty cycle ClockLock ClockBoost-generated clock
Condition
Unit
peak-topeak
tLOCK (2), Time required ClockLock ClockBoost acquire lock
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115: Using ClockLock ClockBoost Features APEX Devices
Table APEX 20KE Clock Input Output Parameters Symbol Parameter Standard
Note Speed Grade
Speed Grade Units
(4), (5),
Input clock frequency
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
12.5
fVCO fCLOCK0 fCLOCK1
Voltage controlled oscillator operating range Clock0 output frequency internal Clock1 output frequency internal 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
fCLOCK0_EXT Output clock frequency external (4), (5), clock0 output
12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5
fCLOCK1_EXT Output clock frequency external (4), (5), clock1 output
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices Notes tables:
input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. maximum lock time 2000 input clock cycles, whichever occurs first. Before configuration, circuits disabled powered down. During configuration, PLLs still disabled. PLLs begin lock once device user mode. clock enable feature used, lock begins once CLKLK_ENA goes high user mode. external feedback mode, maximum clock frequency either maximum clock output according standard, whichever smaller. EP20K400E device, maximum external clock frequency external feedback mode MHz. external feedback mode, clock out, clock feedback input must have same standard. zero delay buffer mode, clock clock must have same standard. voltage-controlled oscillator (VCO) operating range wide enough support device's maximum LVDS data rate when LVDS mode.b
Table shows APEX 20KE device LVDS mode Parameters EP20K400E EP20K600E devices Table shows APEX 20KE LVDS Mode Parameters EP20K1000E EP20K1500E devices. Table EP20K400E EP20K600E LVDS Mode Parameters Symbol Parameter Mode
fINLVDS LVDS receiver/transmitter input clock frequency Maximum LVDS data transfer rate fLVDSDR Input Jitter Peak-to-peak input Jitter (peak-toon input clock peak) Output Jitter (RMS) tDUTY tLOCK output jitter LVDS mode (2), Duty cycle LVDS transmitter output clock Lock time LVDS transmitter receiver PLLs
Note Speed Grade
11.43 11.43 6.88
Speed Grade
Units
87.5 87.5 145.25 612.5 Mbps Mbps Mbps
LVDS receiver/transmitter input clock period
9.52 9.52 5.71
0.25%
0.25%
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115: Using ClockLock ClockBoost Features APEX Devices
Table EP20K1000E EP20K1500E LVDS Mode Parameters Symbol Parameter Mode
fINLVDS LVDS receiver/transmitter Input clock frequency Maximum LVDS data transfer rate fLVDSDR Input Jitter Peak-to-peak Input Jitter (peak-toon input clock peak) Output Jitter (RMS) tDUTY tLOCK Output Jitter LVDS mode (2), Duty cycle LVDS transmitter output clock Lock time LVDS transmitter receiver PLLs
Note Speed Grade
12.80 11.43 6.88
Speed Grade
93.7
Units
78.125 87.5 145.25 612.5 Mbps Mbps Mbps
LVDS receiver/transmitter Input clock period
10.67 9.52 5.71
0.25%
0.25%
Notes tables:
voltage-controlled oscillator (VCO) operating range wide enough support device's maximum LVDS data rate when LVDS mode. This assumes input clock with input jitter This jitter both receiver transmitter LVDS PLLs cascaded together. jitter receiver transmitter will less.
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115: Using ClockLock ClockBoost Features APEX Devices
Table lists APEX 20KE ClockLock pins their function. Table APEX 20KE Device ClockLock Pins Name
CLKp[1.4]
Type
Input
Description
Dedicated pins that drive clock inputs. EP20K400E larger devices, CLK3p CLK4p drive PLL3 PLL4, respectively, generalpurpose mode only. Dedicated pins that allow external feedback PLLs. Dedicated clock output that allows output driven off-chip.
Standards Supported
1.8-V I/O, 2.5-V I/O, AGP, CTT, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, GTL+, 3.3-V PCI, 3.3-V PCI-X, SSTL-2, SSTL-3
CLKLK_FB CLKLK_OUT LVDSTXINCLK1p/n LVDSRXINCLK1p/n
Input Output Input
Dual-purpose pins that drive clock input LVDS LVDS mode LVDS/CMOS data conversion. LVDS clock output that allows drive LVDS clock off-chip LVDS mode. LVDS output data synchronized this clock. These pins dual-purpose pins. Optional that shows status ClockLock 1.8-V I/O, 2.5-V I/O, ClockBoost circuitry. When ClockLock LVCMOS, LVTTL, ClockBoost circuitry locked incoming clock 3.3-V generates internal clock, LOCK driven high. LOCK remains high long clock input remains within specification.
LVDSTXOUTCLK1p/n Output
LOCK
Output
Note:
This available EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices only.
Board Layout
Each uses pins. APEX devices have pair pins ClockLock ClockBoost circuitry. APEX 20KE devices pair each each clock output pin. Separate pins external clock outputs reduce jitter isolating output from adjacent switching pins. also minimizes ground bounce effects from nearby switching outputs.
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115: Using ClockLock ClockBoost Features APEX Devices
Table shows power pins required APEX APEX 20KE devices. Table Power Requirements APEX APEX 20KE ClockLock Features Device
EP20K100 EP20K200 EP20K400
Name
VCC_CKLK GND_CKLK
Description
Power ground pins ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply should isolated from power ground rest device. VCC_CKLK pins have same specifications VCCINT should connected supply, even used. Power ground pins ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply should isolated from power ground rest device. VCC_CKLK pins have same specifications VCCINT should connected supply, even used. Power ground pins external clock output pins (CLKLK_OUT). These pins supply VCCIO GNDIO CLKLK_OUT pins. VCC_CKOUT pins have same specifications VCCIO should connected VCCIO supply even external clock used.
EP20K60E EP20K100E EP20K160E EP20K200E
VCC_CKLK2 VCC_CKLK4 GND_CKLK2 GND_CKLK4 VCC_CKOUT2 GND_CKOUT2
EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
VCC_CKLK[4.1] Power ground pins ClockLock ClockBoost circuitry. GND_CKLK[4.1] ensure noise resistance, power ground supply should isolated from power ground rest device. VCC_CKLK pins have same specifications VCCINT should connected supply even used. VCC_CKOUT1 VCC_CKOUT2 GND_CKOUT1 GND_CKOUT2 Power ground pins external clock output pins (CLKLK_OUT). These pins supply VCCIO GNDIO CLKLK_OUT pins. VCC_CKOUT pins have same specifications VCCIO should connected VCCIO level even external clock used.
ClockLock circuits contain analog components, which sensitive noise generated digital components. Voltage fluctuations power ground planes board, such ground bounce sag, directly affects clock jitter. avoid excessive jitter, designer must proper supply decoupling. devices with ClockLock circuitry have special pins, which provide power dedicated output pin. power ground connected these pins must isolated from power ground rest APEX device other digital devices. These pins named VCC_CKLK, GND_CKLK, VCC_CKOUT GND_CKOUT. file generated Quartus software APEX Device Family Data Sheet tables identify these pins.
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115: Using ClockLock ClockBoost Features APEX Devices
following recommended board layout techniques used:
separate VCC_CKLK, GND_CKLK, VCC_CKOUT GND_CKOUT power planes board layout.
designer mixed-signal system will have already partitioned system into analog digital sections, each with power ground planes board. this case, VCC_CKLK GND_CKLK pins connected analog power ground planes. VCC_CKOUT requires digital power plane connection.
Partition VCCINT, GNDINT, VCCIO, GNDIO planes include islands VCC_CKLK, GND_CKLK, VCC_CKOUT, GND_CKOUT respectively.
fully digital systems that already have separate analog power ground planes board, adding four planes board prohibitively expensive. Instead, board designer create islands VCC_CKLK/GND_CKLK VCC_CKOUT/GND_CKOUT. Figure shows example board layout with analog power island. This would need done VCC_CKLK/GND_CKLK VCC_CKOUT/GND_CKOUT. CLKLK_OUT pins used, isolation VCC_CKOUT necessary. Figure Board Layout Islands
Analog Power Ground Island
APEX Device
Dielectric Width least
Digital Power Planes
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115: Using ClockLock ClockBoost Features APEX Devices
Each VCC_CKLK/GND_CKLK VCC_CKOUT/GND_CKOUT pairs should decoupled with 2.2-µF, 0.1-µF 0.01-µF parallel combination ceramic capacitors located close possible APEX APEX 20KE device. Place 10-µF tantalum capacitor immediately adjacent location where power-supply lines PLLs come into along with ferrite bead. Values depend frequency application. Refer ferrite bead manufacturer frequency specifications. Figure PLLs used LVDS mode, VCC_CKLK4/GND_CKLK4 VCC_CKLK3/GND_CKLK3 pins should decoupled with 2.2-µF, 0.1-µF, 0.01-µF, 0.001-µF parallel capacitors. Figure shows general purpose power supply decoupling. Figure General Purpose Power Supply Decoupling
VCCINT VCCIO GNDIO
VCC_CKLK
0.01
GND_CKLK VCC_CKOUT
0.01
GND_CKOUT APEX Device
Notes:
VCC_CKOUT GND_CKOUT pins only available APEX 20KE devices. PLLs used LVDS mode, VCC_CKLK4/GND_CKLK4 VCC_CKLK3/GND_CKLK3 pins should decoupled with additional 0.001-µF parallel capacitor.
Software Support
ClockShift ClockBoost features, well other feature settings, controlled altclklock parameters. This section describes ports parameters altclklock megafunction shows function prototype component declarations.
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115: Using ClockLock ClockBoost Features APEX Devices
altclklock Ports Parameters
Tables through list altclklock input port, output port, parameter descriptions. Table altclklock Input Port Descriptions Name
inclock
Required
Description
Clock port that drives ClockLock enable signal
Comments
inclocken
When inclocken port high, drives clock0 clock1 ports. When inclocken port low, clock0 clock1 ports drive goes lock. When inclocken port goes high again, must relock. This port available APEX devices. complete feedback loop, there must board-level connection between fbin PLL's external clock output pin. This port available APEX devices.
fbin
External feedback input
Table altclklock Output Port Descriptions Name
clock0
Required
Description
Comments
First output APEX devices, driving PLL's inclock port clock used elsewhere design, only PLL's clock0 output port. possible simultaneously clock0 port, clock1 port, driving PLL's inclock port. APEX 20KE devices, clock0 port, clock1 port, driving PLL's inclock port. however, using generate only clock signal, should clock1 port give Compiler added flexibility when fitting PLL. Second output APEX devices, driving PLL's inclock port clock used elsewhere design, only PLL's clock0 output port. possible simultaneously clock0 port, clock1 port, driving PLL's inclock port. APEX 20KE devices, clock0 port, clock1 port, driving PLL's inclock port. however, using generate only clock signal, should clock1 port give Compiler added flexibility when fitting PLL. Status When locked, this signal VCC. When lock, this signal GND. locked port pulse high while process achieving lock.
clock1
locked
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
INCLOCK_PERIOD
Type
Integer
Required
Description
Specifies period inclock port This parameter required clock setting specified inclock port. Specifies clock setting assignment used with inclock port. INCLOCK_SETTINGS parameter specified, INCLOCK_PERIOD parameter required ignored. omitted, default "UNUSED". Specifies number half-clock cycles which clock0 clock1 ports must locked before locked goes high. This parameter used only third-party functional simulations. compute actual number half-clock cycles which clock0 clock1 ports must locked before locked goes high, Compiler uses value VALID_LOCK_MULTIPLIER parameter. computed value replaces manually-specified values VALID_LOCK_CYCLES parameter. Altera recommends creating with MegaWizard Plug-In Manager obtain select, based design, close approximation value VALID_LOCK_CYCLES parameter. MegaWizard Plug-In Manager automatically specifies values both VALID_LOCK_CYCLES VALID_LOCK_MULTIPLIER parameters. omitted, default five. This parameter available only APEX 20KE devices.
INCLOCK_SETTINGS
String
VALID_LOCK_CYCLES
Integer
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
INVALID_LOCK_CYCLES
Type
Integer
Required
Description
Specifies number half-clock cycles which clock0 clock1 ports must lock before locked goes low. This parameter used only third-party functional simulations. compute actual number half-clock cycles which clock0 clock1 ports must lock before locked goes low, Compiler uses value INVALID_LOCK_MULTIPLIER parameter. computed value replaces manually specified values INVALID_LOCK_CYCLES parameter. Altera recommends creating with MegaWizard Plug-In Manager obtain select, based design, close approximation value INVALID_LOCK_CYCLES parameter. MegaWizard Plug-In Manager automatically specifies values both INVALID_LOCK_CYCLES INVALID_LOCK_MULTIPLIER parameters. omitted, default five. This parameter available only APEX 20KE devices. Specifies scaling factor, half-clock cycles, which clock0 clock1 ports must locked before locked goes high. Compiler uses value VALID_LOCK_MULTIPLIER parameter compute value VALID_LOCK_CYCLES parameter. Altera recommends creating with MegaWizard Plug-In Manager obtain select, based design, close approximation scaling factor. MegaWizard Plug-In Manager automatically specifies values both VALID_LOCK_CYCLES VALID_LOCK_MULTIPLIER parameters. This parameter required locked port connected. Values five. omitted, default five. This parameter available only APEX 20KE devices.
VALID_LOCK_MULTIPLIER
Integer
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
INVALID_LOCK_MULTIPLIER
Type
Integer
Required
Description
Specifies scaling factor, half-clock cycles, which clock0 clock1 ports must lock before locked goes low. Compiler uses value INVALID_LOCK_MULTIPLIER parameter compute value INVALID_LOCK_CYCLES parameter. Altera recommends creating with MegaWizard Plug-In Manager obtain select, based design, close approximation scaling factor. MegaWizard Plug-In Manager automatically specifies values both INVALID_LOCK_CYCLES INVALID_LOCK_MULTIPLIER parameters. This parameter required locked port connected. Values five. omitted, default five. This parameter available only APEX 20KE devices.
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
OPERATION_MODE
Type
String
Required
Description
Normal mode, phase shift measured between internal clock network dedicated inclock pin. also feeds external CLKLK_OUT pin, phase difference results output external CLKLK_OUT time delay introduces. Zero Delay Buffer mode, behaves zero-delay buffer input clock. must connected external CLKLK_OUT pin, output external CLKLK_OUT phase with dedicated inclock pin. clock0 port used drive external CLKLK_OUT pin, CLOCK0_BOOST parameter must unused one; clock1 port used drive external CLKLK_OUT pin, CLOCK1_BOOST parameter must unused one. also used drive internal clock network, corresponding phase shift that network results. programmable phase shift feature available this mode. Thus, OUTCLOCK_PHASE_SHIFT parameter must unused zero. External Feedback mode, fbin port must used, board-level connection between external CLKLK_OUT CLKLK_FB must exist. addition, adjusts output cause signal observed CLKLK_FB synchronized with input clock. also used drive internal clock network, corresponding phase shift that network results. Values NORMAL, ZERO_DELAY_BUFFER, EXTERNAL_FEEDBACK. omitted, default NORMAL. This parameter available only APEX 20KE devices. Specifies integer multiplication factor, which must greater than zero, clock0 port with respect input clock frequency. This parameter specified only clock0 port used; however, required clock setting specified clock0 port. value this parameter must one, two, four APEX devices. Create with MegaWizard Plug-In Manager calculate value this parameter APEX 20KE devices. omitted, default one.
CLOCK0_BOOST
Integer
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
CLOCK0_DIVIDE
Type
Integer
Required
Description
Specifies integer division factor, which must greater than zero, clock0 port with respect input clock frequency. This parameter specified only clock0 port used; however, required clock setting specified clock0 port. setting this parameter must APEX devices. Create with MegaWizard Plug-In Manager calculate value this parameter APEX 20KE devices. omitted, default one. Specifies clock setting assignment used with clock0 port. this parameter specified, CLOCK0_BOOST, CLOCK0_DIVIDE, OUTCLOCK_PHASE_SHIFT parameters required ignored. both CLOCK0_SETTINGS CLOCK1_SETTINGS specified, both must have same phase shift. omitted, default "UNUSED". Specifies integer multiplication factor, which must greater than zero, clock1 port with respect input clock frequency. This parameter only specified clock1 port used; however, required clock setting specified clock1 port. setting this parameter must one, two, four APEX devices. Create with MegaWizard Plug-In Manager calculate value this parameter APEX 20KE devices. omitted, default one. Specifies integer division factor, which must greater than zero, clock1 port with respect input clock frequency. parameter only specified clock1 port used; however, required clock setting specified clock1 port. omitted, default one. Specifies clock setting assignment used with clock1 port. this parameter specified, CLOCK1_BOOST, CLOCK1_DIVIDE, OUTCLOCK_PHASE_SHIFT parameters required ignored. both CLOCK0_SETTINGS CLOCK1_SETTINGS specified, they both must have same phase shift. omitted, default "UNUSED".
CLOCK0_SETTINGS
String
CLOCK1_BOOST
Integer
CLOCK1_DIVIDE
Integer
CLOCK1_SETTINGS
String
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115: Using ClockLock ClockBoost Features APEX Devices
Table altclklock Parameter Descriptions (Part Name
OUTCLOCK_PHASE_SHIFT
Type
Integer
Required
Description
Specifies, output clock phase shift relative input clock. Phase shifts 0.25, 0.5, 0.75 times input period (0°, 90°, 270°) implemented precisely. allowable range phase shift between input clock period. phase shift outside this range, Compiler adjusts fall within this range. other phase shifts, Compiler chooses closest allowed value. fbin port used, programmable phase shift available. This parameter required clock settings used clock0 clock1 ports. omitted, default zero. ClockShift circuitry allows adjust clock delay phase precise timing. This parameter available only OPERATION_MODE parameter NORMAL. This parameter available only APEX 20KE devices.
Function Prototype
following sample code shows AHDL function prototype (port name order also apply Verilog HDL). FUNCTION altclklock (inclock, inclocken, fbin) WITH (INCLOCK_PERIOD, INCLOCK_SETTINGS, VALID_LOCK_CYCLES, INVALID_LOCK_CYCLES, VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER, OPERATION_MODE, CLOCK0_BOOST, CLOCK0_DIVIDE, CLOCK0_SETTINGS, CLOCK1_BOOST, CLOCK1_DIVIDE, CLOCK1_SETTINGS, OUTCLOCK_PHASE_SHIFT) RETURNS (clock0, clock1, locked);
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VHDL Component Declaration
following sample code shows VHDL component declaration altclklock megafunction. COMPONENT altclklock GENERIC (INCLOCK_PERIOD: NATURAL; INCLOCK_SETTINGS: STRING "UNUSED"; VALID_LOCK_CYCLES: NATURAL INVALID_LOCK_CYCLES: NATURAL VALID_LOCK_MULTIPLIER: NATURAL INVALID_LOCK_MULTIPLIER: NATURAL OPERATION_MODE: STRING "NORMAL"; CLOCK0_BOOST: NATURAL CLOCK0_DIVIDE: NATURAL CLOCK1_BOOST: NATURAL CLOCK1_DIVIDE: NATURAL CLOCK0_SETTINGS: STRING "UNUSED"; CLOCK1_SETTINGS: STRING "UNUSED"; OUTCLOCK_PHASE_SHIFT: NATURAL PORT (inclock, inclocken: STD_LOGIC; fbin STD_LOGIC '0'; clock0, clock1, locked STD_LOGIC); COMPONENT;
MegaWizard Interface
MegaWizard Plug-In Manager automatically sets appropriate parameters. first page, MegaWizard manager allows select between entering instance editing existing instantiation. second page MegaWizard Plug-In, choose altclklock from gates directory. this same page, choose filename AHDL, VHDL, Verilog file type. options page three MegaWizard window only apply APEX 20KE device PLLs, shown Figure Table lists options available page three altclklock MegaWizard Plug-In Manager.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Page altclklock MegaWizard Plug-In Manager
Table altclklock MegaWizard Plug-In Options Option
feedback path inside
Description
This option sets OPERATION_MODE parameter NORMAL. this mode, feedback path internal PLL, minimizing clock delay registers. This mode allows programmable phase shift. phase shift entered degrees, using drop-down list box. smallest resolution that implemented between depending other settings. clock0 clock1 signals driven off-chip this mode; however, they will phase aligned with clock input pin. This option sets which output, clock0 clock1, will driven off-chip Zero Delay Buffer External Feedback mode. This option sets OPERATION_MODE parameter ZERO_DELAY_BUFFER. this mode, clock port driven off-chip phase aligned with clock input minimized clock input external clock output delay. Phase shifting possible this mode. clock output selected cannot multiplied, divided. remaining output port that driven off-chip multiplied.
feedback through clock0/clock1 output on-chip connection feedback (zero delay buffer mode)
off-chip connection This option sets OPERATION_MODE parameter EXTERNAL_FEEDBACK. this feedback (external mode, external feedback input phase aligned with clock input pin. feedback mode) external clock output must feed external feedback input board. This same restrictions Zero Delay Buffer mode.
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115: Using ClockLock ClockBoost Features APEX Devices
Page four MegaWizard Plug-In Manager (see Figure sets megafunction's input frequency, clock multiplication, clock division. Estimated Performance displays actual multiplication, division, phase shift. circuits that constructed, actual multiplication division factors differ from values enter, ratio multiplication/division given clock output will same. circuits that cannot constructed, closest achievable multiplication division factors displayed. closest possible phase shift estimated performance ratios also given. inability achieve desired phase shift does prevent circuit construction; compiler achieves closest possible shift, shown under Actual phase shift Estimated Performance box. Figure Page altclklock MegaWizard Plug-In Manager
Page five MegaWizard Plug-In Manager (see Figure provides lock indication latency clock enable port options. lock indication options determined internal configuration parameters that affected user-desired multiplication, division, frequency. These options automatically VALID_LOCK_CYCLES, INVALID_LOCK_CYCLE, VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER parameters.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Page altclklock MegaWizard Plug-In Manager
Figures examples instantiations configurations. Figure APEX APEX 20KE altclklock Instantiation with Clocks Clock Inversion
data_a
CLRN
clock_33
inclock
clock0 clock1 locked
Input Frequency 33.0 Clock0 Frequency Clock1 Frequency data_b
CLRN
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115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX 20KE altclklock Instantiation with Clock Multiplication, Phase Shift External Clock Output
data_a
CLRN
clock_33
clock0 clock1 clk_100 locked Input Frequency 33.33 Phase Shift degrees Clock0 Frequency Ratio Clock1 Frequency Ratio inclock
clk_200
data_b
CLRN
inclock
clock1 locked
clock_100
Input Frequency 33.33 Clock1 Frequency Ratio
Reporting
ClockLock section compilation report displays information regarding device usage (i.e., altclklock megafunction usage). compilation information message displays whether requested clock_boost clock_divide factors and/or requested phase shift achieved. This information useful MegaWizard Plug-In Manager verify configuration constructed. unachievable clock_boost clock_divide factors, compilation will provide error message displaying closest achievable factors. unachievable phase shift, compilation displays closest-achievable implemented phase shift. Actual valid invalid lock cycle indication also displayed. ClockLock section omitted from compilation report design does include PLLs. more information ClockLock section, Quartus software Help.
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115: Using ClockLock ClockBoost Features APEX Devices
Timing Analysis
Multi-clock timing analysis causes timing analyzer report results using slack. input clocks output clocks different clocks that require multi-clock analysis. This condition true even case, because clock coming generated from (not clock pin), reduced clock delay output clock. Another important fact that tuned frequency specify. will function reliably when above below specified frequency (except 2.5% frequency tolerance). runs according your specified settings maximum clock frequency (fMAX). Because this multi-clock analysis, fMAX reported. fMAX calculation necessary, derive from reported slack. micro tCO, tSU, path delay given list path command Slack Report window. These delays added inverted find fMAX that path. When using external feedback input, External Input Delay option used specify amount board delay from external clock output back external feedback input. This assignment made Quartus software through Timing dialog (Tools menu Assignment Organizer).
Clock Domain Transfers
data transfer across clock domains, specific design considerations should made when using clocks with synchronous asynchronous transfers. next sections describe these considerations.
Synchronous Transfers
clocks domain transfer come from single PLL, synchronous register-to-register transfers (i.e. MHz) work across conditions special design considerations need made. clocks come from different PLLs (i.e., same clock with ClockShift), must insert least data path guarantee data transfer between registers that connected local interconnect. other register-to-register transfers (e.g., across MegaLABinterconnects) work without special design considerations. Figure shows LCELL insertion multiple clock source register-toregister transfer local interconnect.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure LCELL Insertion Multiple Clock Source Register-to-Register Transfer Local Interconnect
Registers Connected Local Interconnect
PLL1.clock0
CLRN CLRN
PLL3.clock0
Asynchronous Transfers
asynchronous register-to-register transfer (i.e., MHz), appropriate asynchronous design techniques transfer data from clock domain other. example, DCFIFO first-in first-out (FIFO) function used buffer data transfer. Figure shows DCFIFO function that used buffer data transfer.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Using DCFIFO Interface between Asynchronous Clock Domains
DCFIFO
33_MHz_data DATA
wrreq 33_MHz
WRREQ wrreq WRCLK 50_MHz_data
rdreq 50_MHz
used ClockBoost Circuitry
RDREQ (ACK) RDCLK
ClockShift feature used only some clocks register-to-register transfer, fMAX reduced hold time violation occur, depending direction, magnitude shift (any positive shift past degrees considered negative shift), whether destination source register's clock shifted.
Simulation
altclklock behavioral model used simulate both APEX APEX 20KE generating clock signal based upon reference clock. APEX APEX 20KE behavioral model's instantiation should follow same guidelines restrictions design entry. altclklock behavioral timing models simulate jitter lock acquisition time. zero time, simulation assumes lock time already occurred. latency lock indication modeled. simulate External Feedback Input pin, must External Input Delay option external feedback input pin, shown steps below. Quartus software, choose Assignment Organizer (Tools menu). Choose Node tab. Mode box, select Edit Specific Entity Node Settings for:. Select Browse (.). Node finder search external feedback input select
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115: Using ClockLock ClockBoost Features APEX Devices
Assignment Organizer, select Timing assignment categories list. Name list, select External Input Delay. Setting box, type amount board time between external clock output external feedback input pin. delay should exceed input clock period, whichever less. select
simulator model external clock output timing with external feedback. behavioral models altclklock megafunction reside \quartus\eda\sim_lib directory. apex20ke_mf.vhd file contains VHDL behavioral models used altclklock both APEX APEX 20KE devices. apex20ke_mf.v file contains Verilog behavioral models used altclklock both APEX APEX 20KE devices. behavioral model does perform parameter error checking, user must specify only valid values altclklock parameters. When targeting APEX devices, only APEX 20K-applicable parameters with appropriate values. simulate model successfully, VHDL simulator's resolution must larger resolution will result calculation rounding thus create incorrect multiplication division.
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Sample VHDL Instantiation altclklock Model Design
following shows sample VHDL instantiation altclklock model design. library ieee; ieee.std_logic_1164.all; entity pll_design port inclock std_logic; inclocken std_logic; data_in1 std_logic_vector(7 downto clock0 std_logic; r_out std_logic_vector(7 downto locked std_logic); pll_design; architecture apex pll_design component my_dff port clock data component;
STD_LOGIC; STD_LOGIC_VECTOR(7 DOWNTO STD_LOGIC_VECTOR(7 DOWNTO 0));
component altclklock generic inclock_period inclock_settings valid_lock_cycles invalid_lock_cycles valid_lock_multiplier invalid_lock_multiplier operation_mode clock0_boost clock0_divide clock1_boost clock1_divide clock0_settings clock1_settings outclock_phase_shift port (inclock inclocken fbin clock0 clock1 locked
natural; string "UNUSED"; natural natural natural natural string "NORMAL"; natural natural natural natural string "UNUSED"; string "UNUSED"; natural
std_logic; std_logic; std_logic '0'; std_logic; std_logic; std_logic);
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115: Using ClockLock ClockBoost Features APEX Devices
component; signal clock1_sig std_logic; begin altclklock generic inclock_period 40000, clock1_boost clock1_divide clock0_boost clock0_divide operation_mode "NORMAL", valid_lock_cycles invalid_lock_cycles valid_lock_multiplier invalid_lock_multiplier outclock_phase_shift 10000 port (inclock inclock, inclocken inclocken, clock0 clock0, clock1 clock1_sig, locked locked); process(clock1_sig) begin clock1_sig'event clock1_sig then r_out data_in1; process; apex;
Sample Testbench VHDL Design
following shows sample testbench VHDL design. library ieee; ieee.std_logic_1164.all; entity plltest2 plltest2;
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115: Using ClockLock ClockBoost Features APEX Devices
architecture behave2 plltest2 signal inclock std_logic '0'; signal inclocken std_logic; signal data_in1 std_logic_vector(7 downto "10101010"; signal clock0 std_logic; signal locked std_logic; signal r_out std_logic_vector(7 downto component pll_design port inclock std_logic; inclocken std_logic; data_in1 std_logic_vector(7 downto clock0 std_logic; r_out std_logic_vector(7 downto locked std_logic) component; begin inclocken after pll_design port inclock inclock, inclocken inclocken, data_in1 data_in1, clock0 clock0, r_out r_out, locked locked); process(inclock) begin loop inclock inclock after loop; process; behave2; configuration pllconfig plltest2 behave2 pll_design entity work.pll_design(apex); for; for; pllconfig;
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Example Verilog Instantiation altclklock Model Design
following shows example Verilog instantiation alkclklock model design. module pllsource (inclock, inclocken, data_in1, clock0, r_out, locked); input inclock, inclocken; input [7:0] data_in1; output clock0, locked; output [7:0] r_out; wire clock1_sig; [7:0] r_out; altclklock PLL_1 .inclock(inclock), .inclocken(inclocken), .clock0(clock0), .clock1(clock1_sig), .locked(locked)); defparam PLL_1.inclock_period 50000, PLL_1.inclock_settings "UNUSED", PLL_1.clock0_settings "UNUSED", PLL_1.clock1_settings "UNUSED", PLL_1.valid_lock_cycles PLL_1.invalid_lock_cycles PLL_1.valid_lock_multiplier PLL_1.invalid_lock_multiplier PLL_1.clock0_boost PLL_1.clock1_boost PLL_1.clock0_divide PLL_1.clock1_divide PLL_1.outclock_phase_shift PLL_1.operation_mode "NORMAL"; always @(posedge clock1_sig) begin r_out data_in1;
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Sample Testbench Verilog Design
following shows sample testbench Verilog design. timescale ns/100ps module plltest; parameter 10101010; inclock, inclocken; [7:0] data_in1; wire clock0, locked; wire [7:0] r_out; pllsource .inclock(inclock), .inclocken(inclocken), .data_in1(data_in1), .clock0(clock0), .r_out(r_out), .locked(locked)); initial data_in1 tmp; initial inclock always inclock ~inclock; initial begin inclocken inclocken initial begin #100 data_in1 11110000; #200 data_in1 00110011; endmodule
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Sample Waveform
Figure shows example waveform dual-clock outputs APEX 20KE PLL. this example, clock0 clock clock1 clock; both shifted/lag 90°. simulation, |altclklock|<instance>|pll clock0 output PLL, |altclklock|<instance>|pll~CLK1 clock1 output PLL, locked output indication. timing simulation, output clocks have slight negative shift because they output flip-flop clock ports. positive delay added they reach clock ports RAMs flip-flops. Figure Timing Simulation Output Waveform Dual-Output Clocks with Shift
Applications
This section describes some applications APEX 20KE device's ClockLock, ClockBoost, ClockShift features.
Clock Multiplication Division
ClockBoost feature allows designers low-speed clocks board, reducing effects high-speed clocks; designers lowspeed clock board then ClockBoost feature increase clock speed within device. Using lower speed clock help reduce transmission line effects allow designer simplify board layout. APEX devices, board clock multiplied within device. More complex ratios possible with APEX 20KE devices. Tables page more information.
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Clock multiplication division useful communications applications. ClockBoost feature used when transfer rates must multiplied divided. multiplication division clocks also needed maintain rates when converting between parallel data streams serial data streams. microprocessor-based systems, system clock lower rate than other system components. example, embedded processor peripheral circuits faster rate than system clock. Embedded applications also require faster internal rates operations such synchronization counting. ClockBoost feature used multiply slower system clock embedded application APEX device. multiplication division capabilities APEX device give designers ability develop SOPC designs. Figure shows clock synthesis embedded application. Figure Embedded Application Using Clock Synthesis
Clock Microprocessor System Logic Logic
Logic
Logic
ClockBoost feature used create variable-size pulse widths. using multiplied frequency counter, create pulse widths various sizes depending multiplied frequency driving counter. These pulses used interface with external SRAM DRAM. example, write enable (WE), address strobe (RAS), column address strobe (CAS) signals generated DRAM interface, meeting appropriate address data setup times. Figure
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Figure Using Multiplication Generate Pulses
ADDR
DATA
Pulse
Removing Board Delay
APEX 20KE device feedback pins allow designer reduce clock skew between several devices board. actively aligns feedback input input clock. dynamically adjusts output during operation account delay changes that occur temperature voltage. While designing board, should match return delay containing feedback input with delay each device involved. Similar delays ensure that aligned feedback input edge also aligned destination devices, eliminating delay. Figure illustrates board delay reduced using APEX 20KE device.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Reducing Board Delay Using APEX 20KE Device
CLKLK_FB CLKLK_OUT
Note
Device
APEX 20KE Device Device
Device
Note:
board design, route delay from CLKLK_OUT1 each device return route delay CLKLK_FB1 should equal.
Minimize delays between CLKLK_OUT CLKLK_FB signals APEX 20KE devices. sure clock-to-output time plus board time less than input clock period, whichever less.
LVDS
EP20K400E larger devices, general-purpose PLLs configured LVDS interfaces. These PLLs interface with APEX 20KE LVDS differential input output blocks. multiply clock input LVDS/CMOS data conversion using dedicated, built-in parallel-to-serial serial-to-parallel converters. When APEX 20KE device configured LVDS, uses multiply LVDSRXINCLK1p input. Serial-to-parallel conversion circuitry uses multiplied clock convert high-speed serial LVDS data low-speed parallel CMOS data. multiplication factor used should match multiplexer/de-multiplexer ratio desired. example, conversion 1-to-8 required 622-Mbps LVDS channel, multiplication factor needed with clock input 77.75 MHz. needed, serial-to-parallel converter bypassed lowspeed LVDS data inputs. Figure shows built-in LVDS input interface with LVDS serial input Mbps multiplexer/de-multiplexer ratio 1-to-8.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX 20KE LVDS Receiver Interface
APEX 20KE LVDS
Serial Data Mbps data[7.0] Serial-to-Parallel Converter
LVDSRXINCLK1P 77.75 Clock
77.75 Dedicated Clock
When APEX 20KE device configured LVDS, uses multiply LVDSTXINCCLK1p input. Parallel-to-serial conversion circuitry uses multiplied clock convert low-speed parallel CMOS data high-speed serial LVDS output data. multiplication factor should match multiplexer/de-multiplexer ratio desired. example, conversion 7-to-1 needed 462-Mbps LVDS output, multiplication factor needed seven with input clock MHz. needed, parallel-to-serial converter bypassed low-speed LVDS serial output. Figure shows built-in LVDS output interface that converts internal parallel data into LVDS serial data with 7-to-1 ratio Mbps. Figure APEX 20KE Transmitter Interface
APEX 20KE LVDS Interface
data[6.0] Built-in Parallel-to-Serial Converter Serial Data Mbps
66-MHz LVDSTXINCLK1p
Internal Global Clocks LVDSTXOUTCLK1
Note:
LVDS mode, LVDSTXINCLK1p three remaining internal global clocks (G1, G3). These remaining global clocks cannot used general-purpose (receiver allowed).
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115: Using ClockLock ClockBoost Features APEX Devices
Clock Domain Conversion
APEX 20KE devices, ClockBoost circuitry used convert clock frequency (1.544 MHz) clock frequency (2.048 MHz) vice versa. ClockLock circuit special mode perform T1/E1 conversions; this multiplication accomplished setting CLOCK0_BOOST CLOCK0_DIVIDE parameters 256/193 193/256. with type clock domain data transfer, appropriate asynchronous design techniques transfer data from clock domain other. example, DCFIFO FIFO function used buffer data transfer. Figure shows DCFIFO that interfaces between clock domains. example, DCFIFO with input data clocked input clock. output DCFIFO should clocked with converted clock from output. Output data synchronized output clock. This same practice used synchronization across other clock domains. Figure Using DCFIFO Interface between Clock Domains
DCFIFO
33_MHz_data DATA
wrreq 33_MHz
wrreq WRREQ WRCLK 50_MHz_data
rdreq 50_MHz
used ClockBoost Circuitry
RDREQ (ACK) RDCLK
Time-Domain Multiplexing
ClockBoost feature allows designers implement time-domain multiplexed applications which given circuit used more than once clock cycle. Depending whether circuit clocked ClockBoost circuitry APEX device, operate four times, respectively, system cycle. With time-domain multiplexing, given function implemented with fewer ESBs.
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115: Using ClockLock ClockBoost Features APEX Devices
example, circuit using multipliers, each multiplier uses total LEs. Alternatively, could implement circuit multiplier that used twice clock cycle using clock that system clock. input multiplier multiplexed switch between sets inputs; output de-multiplexed that drive multiplication results. While some needed accomplish multiplexing, cost outweighed saved using multiplier. Figure shows schematic timedomain multiplexed circuit. Figure Time-Domain Multiplexed Circuit
dataa1[15.0]
datab1[15.0] Multiplier
producta[31.0]
dataa2[15.0]
productb[31.0]
datab2[15.0]
control signal
ClockLock
ClockBoost
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115: Using ClockLock ClockBoost Features APEX Devices
same example applied circuit requiring four multipliers; circuit would clock 4-to-1 multiplexers instead 2-to-1 multiplexers shown Figure control line created using one-hot counter state machine enable output register clock cycle, permitting multiplier used four times single system clock cycle. Table shows reduction resource requirements. Table Resources Required Multipliers Design
multipliers multipliers, time-domain multiplexed with ClockBoost Four multipliers Four multipliers, time-domain multiplexed with ClockBoost
Required
1,788
ClockShift Applications
Phase time delay adjustment clock outputs have many interface applications. Delay adjustment allows designer overcome strict timing margins that would possible overcome without clock adjustment. adjusting clock output's lead lag, known clock delay between various clocks improve perceived clock-to-output timing external devices. Some high-speed devices, such SDRAMs, have access times that require fast setup times interface device given critical path. meet device-to-device timing requirements, internal clock destination chip's input register adjusted specified amount time from input clock. adding clock lag, obtain faster setup time destination device input register. Figure shows APEX 20KE ASIC device-to-device interface with timing. example, APEX 20KE device receiving data from ASIC with tCO. Assuming 133-MHz system speed board propagation delay (tPD) between ASIC APEX 20KE device, tDELAY Only left setup time into APEX 20KE device (7.5 period). Timing adjusting APEX 20KE internal clock amount (PLD) (needed).
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115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX 20KE ASIC Device-to-Device Interface with Timing
ASIC with Shift APEX 20KE
CLKIN
(APEX)
(Needed)
cases where feedback used, clock delay control used adjust clock delay other devices based their distance from clock source. Designers manually adjust external clock output APEX 20KE device compensate board delay. Phase adjustment also useful interfaces external device. input clock phase shifted with separate altclklock circuits then output external outputs. This along with input could used three-phase motor control.
Conclusion
advanced APEX ClockLock ClockBoost features PLLs provide significant improvements system performance design versatility. reduction clock delay elimination clock skew within device improves design speed, time-domain multiplexing improves area usage. ClockBoost feature simplifies board design running internal logic device faster rate than input clock frequency. advanced APEX 20KE ClockLock ClockBoost feature further enhanced with m/(n multiplication, LVDS interfaces, phase adjustment more complex clock synthesis applications.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Revision History
information contained Application Note (Using ClockLock ClockBoost Features APEX Devices) version supersedes information published previous versions.
Version Changes
following changes were made Application Note (Using ClockLock ClockBoost Features APEX Devices) version 2.2:
Updated CLKp[1.4] description Table Updated Figures Various textual changes.
Version Changes
following changes were made Application Note (Using ClockLock ClockBoost Features APEX Devices) version 2.1:
Updated Tables Added Tables Updated Figures Updated APEX 20KE Devices section.
Version 2.01 Changes
following changes were made Application Note (Using ClockLock ClockBoost Features APEX Devices) version 2.01:
Updated information Board Layout from pages Added Figures Updated Table
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Notes:
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
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Copyright 2001 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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APEX Devices Application Note October 2001, ver. Introd

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