GC2011A 3.3V DIGITAL FILTER CHIP March 2000 Information

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GC2011A 3.3V DIGITAL FILTER CHIP March 2000 Information

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SLWS129A
GC2011A
3.3V DIGITAL FILTER CHIP
March 2000
Information provided Graychip believed accurate reliable. responsibility assumed Graychip use, infringement patents other rights third parties which arise from use. license granted implication otherwise under patent rights Graychip.
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
REVISION HISTORY
Revision
Date
1999 Sept, 1999 Original
Description
Preliminary markings removed Section Electrical timing tables changed reflect production test 3.7, Table changed Hilbert Transform output register 2000 added ball grid array package changed gain equation reference MSBs input output. Page Rotated marking text PBGA package Page Snap rate invalid Page Changed test load from Page Changed Output delay threshold (Note 1.3v. Page Changed Data output delay match test.
2000
Texas Instruments Incorporated
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
FEATURES
BLOCK DIAGRAM GC2011A GC2011 COMPARISON. DATASHEET OVERVIEW
2.10 2.11 2.12 2.13 2.14
FUNCTIONAL DESCRIPTION
TRANSVERSAL FILTERS CONTROL INTERFACE COUNTER SYNCHRONIZATION CIRCUIT. INPUT INPUT NEGATION FILTER PATHS FILTER CELL ACCUMULATOR CIRCUIT SUMMER OUTPUT NEGATION GAIN OUTPUT SNAPSHOT MEMORY
3.10
FILTERING MODES
FULL RATE HALF RATE QUARTER RATE DOUBLE RATE DECIMATION INTERPOLATION HILBERT TRANSFORM FILTERS REAL COMPLEX QUADRATURE DOWN CONVERT COMPLEX REAL QUADRATURE UPCONVERT DIAGNOSTICS
PACKAGING
QUAD FLAT PACK (QFP) PACKAGE BALL GRID ARRAY (PBGA) PACKAGE.25
6.10
DESCRIPTIONS CONTROL REGISTERS
A-PATH B-PATH CONTROL REGISTER A-PATH B-PATH CONTROL REGISTER CASCADE MODE CONTROL REGISTER COUNTER REGISTER GAIN REGISTER OUTPUT MODE REGISTER SNAPSHOT MODE CONTROL REGISTERS SNAPSHOT START CONTROL REGISTER SHOT ADDRESS MODES REGISTER
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS THERMAL CHARACTERISTICS CHARACTERISTICS CHARACTERISTICS
APPLICATION NOTES
POWER GROUND CONNECTIONS STATIC SENSITIVE DEVICE OPERATION REDUCED VOLTAGE OPERATION SYNCHRONIZING MULTIPLE GC2011A CHIPS
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure GC2011a Block Diagram Basic Transversal Filters Control Timing Cell Filter Path Block Diagram Filter Cell Timing Input Timing Output Timing Processing Complex Input Data
LIST TABLES
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Default Control Register Settings Full Rate Mode Control Register Settings Half Rate Mode Control Register Settings Quarter Rate Mode Control Register Settings Double Rate Mode Control Register Settings Decimation Mode Control Register Settings Interpolation Mode Control Register Settings Hilbert Transform Mode Control Register Settings Real Complex Conversion Mode Control Register Settings Complex Real Conversion Mode Control Register Settings Diagnostic Test Configuration Expected Test Results Listing Package Listing Package Mask Revisions Absolute Maximum Ratings Recommended Operating Conditions Thermal Data Operating Conditions Characteristics
Texas Instrument Incorporated
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
GC2011A
FEATURES
Improved volt, higher speed, GC2011 replacement million samples second (MSPS) input rate Dual inputs complex, dual path double rate input processing Complement offset binary conversion data, coefficients outputs internal precision multiply-add filter cells Snapshot memory adaptive filtering taps with even symmetry decimate decimate interpolate taps rate taps rate MSPS real MSPS complex conversion mode Real complex complex real conversion modes Snapshot memory adaptive filter update calculations Gain adjust steps Microprocessor interface output, diagnostics Built diagnostics Watt MHz, volts quad flat pack package ball grid array package control,
BLOCK DIAGRAM
block diagram illustrating major functions chip shown Figure
Feedback
bits
bits
Data
ACCUMULATOR
Data A-PATH FILTER CELLS)
bits
+/-1
bits
bits
bits
bits
bits
AOUT
INPUT
+/-1
(CASCADE MODE ONLY)
COUNTER
GAIN
bits
Feedback Data B-PATH
Data
bits
ACCUMULATOR
FILTER CELLS)
bits bits
bits bits
OUTPUT
bits
bits
BOUT
+/-1 +/-1
CASCADE MODE
2-12
MODE
bits bits MODE CONTROLS
CONTROL INTERFACE
SNAPRAM READ
bits bits bits bits
SNAPSHOT
-DUAL MODE -DUAL MODE -SINGLE MODE -SINGLE MODE
AOUT BOUT
COEFFICIENT READ/WRITE
Figure GC2011A Block Diagram
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GC2011A 3.3V DIGITAL FILTER CHIP GC2011A GC2011 COMPARISON
SLWS129A
GC2011A designed functional footprint compatible replacement GC2011 chip. timing specifications GC2011A meet exceed timing specifications GC2011. Electrically GC2011A volt only part, making incompatible with GC2011's volt mode. GC2011A fully compatible with GC2011's volt mode, lower power consumption. Section timing electrical specifications. NOTE: GC2011A inputs volt tolerant; chip damage occur input voltages exceed 0.5V (3.8 volts). Designs using GC2011 volts will need volt supply voltage level translators GC2011A. function GC2011A been slightly enhanced, enhancements "backward" compatible with GC2011 that GC2011 user will need change software processing algorithms GC2011A chip. Highlights enhancements follow.
1.2.1
Offset Binary Conversion
Digital filter chips commonly used with analog digital converters (ADCs) digital analog converters (DACs) which often require offset binary data format rather than two's complement data format GC2011. Offset binary data easily converted two's compliment inverting most significant (MSB) data word. GC2011A been enhanced allow conversion between offset binary two's complement format optionally inverting input output data. Four control bits (register address have been added which, when high, invert MSBs Ain, Aout, Bout data words. These control bits cleared power that GC2011A will power GC2011's two's complement mode. Section 6.10 details.
1.2.2
Clock Loss Detect Power Down Modes
GC2011 chip draws excessive current operated without clock signal. This caused internal dynamic storage nodes being left unknown state when clock stopped. clock loss detect circuit been added GC2011A that will chip fully static mode clock stopped. fully static mode powers down chip reduces power consumption down microwatts until clock resumes. user also force power down state desired. control bits (register address used control clock loss detect power down modes. control turns clock loss detect circuit, other forces power down mode. Both bits cleared power keep GC2011 compatibility. Section 6.10 details.
1.2.3
Control Interface
control interface been enhanced either strobes original GC2011, strobes used most memory interfaces. grounded, then interface behaves mode, where becomes becomes pin. GC2011A chip ground GC2011 chip, that GC2011A chip soldered into GC2011 socket will automatically operate GC2011 mode. Section details.
1.2.4
NEW_MODES Control Register
control register address been added GC2011A control GC2011A modes. Address unused GC2011 chip that existing GC2011 control software will activate modes. This control register powers GC2011 compatible mode. Section 6.10 details.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
DATASHEET OVERVIEW
This document organized Sections:
Section provides functional description chip. Section describes configure chip implement several commonly used filters. Section describes packaging specifications Section describes signals Section describes control register contents. Section describes specifications. Section contains application notes.
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GC2011A 3.3V DIGITAL FILTER CHIP FUNCTIONAL DESCRIPTION
SLWS129A
Fabricated micron CMOS technology, GC2011A chip general purpose digital filter chip with multiply-add filter cells. chip operates rates MHz. input data size bits coefficient data size bits. output data size bits. multiply-add cells arranged arbitrary phase filter linear phase filter with even symmetry. Decimation interpolation modes double quadruple number taps filter. input ports allow filter cells shared between data paths order process signals process complex data. Each path becomes arbitrary phase filter, symmetric filter, decimate filter decimate filter. Coefficient double buffering clock synchronization logic permits user switch between coefficient sets without causing undesirable transients filter's operation. Complex coefficients handled using add/subtract cell which combines data paths. complex data complex coefficient filter requires chips, output output. number complex taps varies from depending upon symmetry desired rate. input data rate equal clock rate, half clock rate quarter clock rate. effective number taps doubles half rate data quadruples quarter rate data. input data rate extended chips used. With chips filter size taps arbitrary phase taps linear phase. decimation desired, then only chip required filter size taps. single chip used convert data between real complex formats. When converting from real complex chip mixes signal down FS/4 lowpass filters results. convert from complex real chip interpolates signal two, mixes FS/4 outputs real part result. data paths used process input data filtering upper bits path lower bits other. shift circuit merges results into output. chip includes snapshot memory which capture blocks input output data. size snapshot programmed sample snapshots, sample snapshots, sample snapshot, sample snapshot. These samples read external processor used adaptive updates filter coefficients. internal data precision bits, sufficient preserve full multiplier products prevent overflow filter's adder tree. results passed through gain circuit before they rounded bits. gain circuit adjust signal's amplitude over range steps. chip diagnostic circuits provided simplify system debug maintenance. chip receives configuration control information over microprocessor compatible consisting data port, address port, read/write bit, control select strobe. control registers, coefficient registers, snapshot memory memory mapped into word address space control port.
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GC2011A 3.3V DIGITAL FILTER CHIP TRANSVERSAL FILTERS
chip implements finite impulse response (FIR) transversal filters defined Equation (1):
SLWS129A
y(n)
where x(n) input sample time y(n) output sample time number taps filter h(k) filter coefficients. Many common filters symmetric, meaning coefficients symmetric about center tap. example, coefficients have even-length symmetry. coefficients have odd-length symmetry. Figure shows basic transversal filter structure non-symmetric filter, even symmetry filter symmetry filter (actual GC2011A filter sizes taps).
x(n)
y(n) NON-SYMMETRIC FILTER
x(n)
y(n) EVEN SYMMETRY FILTER
x(n)
y(n) SYMMETRY FILTER
Figure Basic Transversal Filters
GC2011A chip implements transversal filter structures shown Figure with addition pipeline delays increase maximum clock rate chip. pipeline delays latency chip effect operation.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
CONTROL INTERFACE
control interface performs five major functions: allows external processor configure chip, allows external processor load filter coefficients, allows external processor capture read samples from chip, allows external processor perform diagnostics, generates one-shot synchronization strobe. chip configured writing control information into control registers within chip. contents these control registers them described Section registers written read from using C[0:15], A[0:8], pins. Each control register been assigned unique address within chip. This interface designed allow GC2011A appear external processor memory mapped peripheral (the equivalent memory chip's pin). chip's control address space divided into thirteen control registers, coefficient registers, snapshot memory words. thirteen control registers APATH_REG0, APATH_REG1, BPATH_REG0, BPATH_REG1, CASCADE_REG, COUNTER_REG, OUTPUT_REG, SNAP_REGA, SNAP_REGB, SNAP_START_REG,ONE_SHOT, NEW_MODES. control registers mapped addresses Section details about contents these registers. filter coefficients stored read/write registers which accessed using addresses through 255. There filter coefficients stored filter cell. Addresses 128+4K, 128+4K+1, 128+4K+2 128+4K+3 four coefficient registers filter cell where ranges from Filter cells path-A filter cells path-B. contents snapshot memory accessed using addresses through 511. Address used generate one-shot pulse. This pulse, which clock cycle wide, output from chip pin. external processor microprocessor, computer, chip) write into register setting A[0:8] desired register address, selecting chip using pin, setting C[0:15] desired value then pulsing low. data will written into selected register when both will held when either signal goes high. read from control register processor must A[0:8] desired address, select chip with pin, then low. chip will then drive C[0:15] with contents selected register. After processor read value from C[0:15] should high. C[0:15] pins turned (high impedance) whenever high when low. chip will only drive these pins when both high. also ground read/write direction control control strobe. This mode equivalent GC2011 control interface. Figure shows timing diagrams illustrating both modes.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
A[0:8] C[0:15]
tCSU tCHD tCSU tCDLY
READ CYCLE- NORMAL MODE
A[0:8]
tCSU
tCSPW tCSU tCHD
C[0:15]
WRITE CYCLE- NORMAL MODE
A[0:8] C[0:15]
READ CYCLE- HELD
tCHD tCSU tCDLY
A[0:8]
tCSPW tCSU tCHD
C[0:15]
WRITE CYCLE- HELD
Figure Control Timing
setup, hold pulse width requirements control read write operations given Section IMPORTANT: Care should taken insure that control data stable during write cycle meets TCSU TCHD setup hold requirements. data changes during write cycle, then control modes momentarily change, adversely effecting chip's operation.
COUNTER SYNCHRONIZATION CIRCUIT
chip contains control counter which used synchronize filter chip's internal controls. counter synchronized sync input pulse, left free (see SS_OFF control description Section 6.8). period counter 16*(CNT+1) clocks, where ranges from 65535. value using control register COUNTER_REG. counter counts down from (16*CNT+15) zero starts over again. Each time counter reaches zero generates terminal count strobe (TC). pulse output used trigger snapshot memory. pulse output pin, then used synchronize multiple GC2011A chips. Application notes showing this included Section 8.5. least significant bits counter used synchronize internal operation chip. least significant bits counter used diagnostic inputs filter paths. sync output used output either delayed clock cycles, one-shot pulse terminal count
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
INPUT
input multiplexor circuit performs three functions: allows user select which data source input filter paths, sets input data rate, optionally delays data. controls input selection, input rate, data delay independent filter paths. input circuit allows user select either A-input, B-input LSBs counter filter path's input. Typically A-input will feed A-path B-input will feed B-path. counter input selected diagnostics. input rate less than clock rate, case interpolation modes, half rate modes quarter rate modes, then input circuit programmed hold every-other every-fourth input sample. input delay clock cycles. These delays typically zero, necessary real complex complex real conversion modes. control timing information input circuit described Section 6.1.
INPUT NEGATION
data from input circuit optionally negated input negate circuit. input negation circuit allows user negate samples, even time samples (i.e., every other input), time samples. This circuit used input data down FS/4 real complex conversion mode. input negation controls described Section 6.1.
FILTER PATHS
block diagram cell filter path shown Figure
Feedback Controls Cascade Mode
Delay Controls
Delay Controls
Delay Controls
Feedbacka
Feedbackb Bits Data C-Sel Sumb
Bits
Data C-Sel
Data C-Sel
Data C-sel
Data
Data
Data C-Sel Bits
FEEDBACK CIRCUIT
Bits
C-Sel C-Sel
Dataa
Bits
FILTER CELL
FILTER CELL
FILTER CELL
KEY: These signals unique A-Path circuit These signals unique B-Path circuit
Figure Cell Filter Path Block Diagram
Only data paths through filter cells shown. coefficient interfaces shown. Each filter path contains filter cells data feedback circuit. filter cell contains multiplier-adder structure described next section. feedback circuit delays feeds back data output provide reverse data used
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
symmetric filter modes. feedback circuit will also negate reverse data, desired, implement anti-symmetric filters. non-symmetric modes feedback samples cleared. There four filter coefficients stored within each filter cell. C-Sel signal control which selects which coefficient what time. C-Sel signal forced value, toggle between coefficients, rotate through four coefficients. C-Sel signal synchronized LSBs control counter when toggling between coefficients. cascade mode paths used series single path with filter cells. this mode data-out sum-out outputs path into data-in sum-in inputs path feedback-out path into feedback-in path paths independent programmed differently, example path interpolating while path decimating.
FILTER CELL
block diagram filter cell shown Figure Forward Delay Control Reverse Delay Control
NOTE: delay circuits also hold data during interpolation.
Bits
Z-(1,2,4)
Data
Z-(1,2,4)
Bits
Data
Unsigned Mode
C-Sel Coefficient Read/Write Selects
Bits
Signed unsigned Adder
Bits
C-Sel
Register
Bits
Register Register Register
LSBs
Multiplier
Bits
Bits
Bits
Adder
Figure Filter Cell
forward reverse data samples delayed then passed adder. amount delay depends upon selected filtering modes. normal mode samples delayed clock. decimate mode samples delayed cycles decimate four mode forward samples
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
delayed four cycles. interpolate modes samples held multiple clock cycles rather than delayed. Details delay control modes described Section adder operate signed unsigned mode. signed mode outputs result which sign extended bits. unsigned mode outputs signed result, where 14th (the sign bit) forced zero. adder output multiplied coefficient selected C-Sel control from four coefficient registers. coefficient taken from LSBs registers. adder adds multiplier output data outputs result next filter cell.
ACCUMULATOR
output from filter path passed accumulator shown Figure accumulator programmed accumulate blocks samples. accumulator used expand effective length filter when output rate less than clock rate. Modes that accumulator decimation, half rate, quarter rate modes.
IMPORTANT accumulator does guard against overflow. user's responsibility insure that filter's gain will cause overflow. Overflow will occur user restricts filter coefficients that their absolute values less than 220. Since maximum absolute value coefficient 213, this restriction does affect filters with less than taps. those filters with lengths greater than taps, which found decimate quarter rate modes, this restriction only applies hypothetical case where every coefficient close full scale.
CIRCUIT
circuit used when filtering input data. this mode user splits input data into upper bits lower bits. upper bits used A-path input lower bits used B-path input. paths programmed same except that A-path configured signed inputs B-path configured unsigned inputs. same filter coefficients loaded into paths. outputs from paths then added together shifting B-path down bits, rounding result (using round-to-even algorithm), adding A-path output. result passed through gain circuit, rounded bits output output pins. upper bits result output A-out pins lower bits output upper bits B-out pins.
2.10
SUMMER
summer circuit used results from paths together. This feature used input mode, double rate modes, when implementing complex filters. adder converted subtracter using input negation controls.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
2.11
OUTPUT NEGATION
output negation control allows every other output sample negated. This used complex data frequency quarter half output sample rate. This used primarily when converting complex data real.
2.12
GAIN
gain filter adjusted steps using gain circuit. output multiplied
gain value 2S(1+F/16) where range from result saturated plus minus full scale whenever product overflows word. output bits pulse high clock cycle each time overflow detected. output then rounded upper bits result. lower bits cleared. gain adjustment allows user scale filter coefficients order optimize filter's dynamic range, then readjust overall filter gain using gain circuit.
2.13
OUTPUT
output multiplexor circuit formats gain outputs output from chip. dual path mode upper each gain output word passed A-out B-out pins. output data rate half quarter rate, then user have A-path B-path outputs multiplexed onto A-out pins. cascade modes path result output value using combination A-out B-out pins. output mode upper bits output A-out pins lower bits output upper B-out pins.
2.14
SNAPSHOT MEMORY
snapshot memory used capture blocks input output samples. memory configured independent snapshots, longer snapshot. dual mode memory configured capture word snapshots, byte snapshots. single mode memory configured capture word snapshot, byte snapshot. snapshot data come from A-in, B-in, A-out, B-out samples. dual mode input selection memories made independently. mode upper bits each data source stored snapshot. mode A-in B-in samples stored upper bits snapshot. snapshot programmed store every sample, every-other sample, every third sample, every forth sample. This useful when chip's input output data rate less than clock rate. snapshot started writing configuration information control registers SNAP_REGA, SNAP_REGB SNAP_REGC, then setting START SNAP_REGC (See Section 6.8). snapshot then waits trigger condition plus optional delay before starting. trigger conditions are: start immediately after START set, trigger snapshot sync (SN) strobe, trigger sync input (SI) strobe, trigger counter's (see Section 2.3) terminal count (TC) strobe. delay from trigger multiples sample times, where sample time depends upon selected data rate. delay 128DR, where delay count ranging from rate ranging from delay setting useful when there multiple GC2011A chips running parallel user wishes capture longer snapshot. example, chip configuration could capture 1024 samples setting chip capture samples setting second chip with delay setting capture samples.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
triggering strobe user guarantee that snapshots spaced known number samples. example, user program chip capture blocks samples every clocks. blocks then coherently combined calculate accurate spectral information. Once snapshot been triggered, chip clears START control bit. When snapshot finished chip will A_DONE B_DONE bits SNAP_REGC. NOTE that delay from START being cleared DONE bits being 8192 clocks when rate every fourth clock trigger delay user accesses snapshot words using addresses chip's control address space. samples were stored bytes, results either read byte words, read sign extended bytes. user reading bytes, then control used select upper lower byte. snapshot memory read-only user.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
FILTERING MODES
This Section describes common filtering modes configure chip implement them. Unless otherwise indicated, only A-path, B-path cascade mode control register values given. counter, gain, output, snapram control registers given default values listed Table below.
Table Default Control Register Settings REGISTER
COUNTER GAIN OUTPUT SNAP_REGA SNAP_REGB SNAP_REGC default settings configure chip
DEFAULT
1030
COMMENT
Don't care Section Section Sections configure snapshot memory
A-in pins cascaded mode data input B-out pins cascaded mode data output. cascaded mode results output A-out pins setting OUTPUT register 0008HEX. Round outputs bits. Give input output gain
input output latency given each modes. latency pipeline delays defined delay from (see Figure 6-a) first filter output affected measure this delay clearing filter taps except first using impulse data input. latency then defined delay clock cycles (not data samples) from impulse impulse modes described this Section have been configured that input output timing shown Figure half rate quarter rate modes inputs must synchronized with shown. output timing shows output samples generated relative
TIME Full Rate Half Rate Quarter Rate
INPUT TIMING Full Rate Half Rate Quarter Rate OUTPUT TIMING
Figure Timing
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
FULL RATE
full rate filter implements Equation using structures shown Figure control register settings which configure chip full rate modes tabulated below:
Table Full Rate Mode Control Register Settings Symmetry
None Even
Dual Path Cascaded
Dual Cascaded Dual Cascaded Dual Cascaded
Taps
A-PATH
REG0 20D8 20D8 20D8 20D8 20D8 20D8 REG1 6000 6028 6108 6128 6181 61A8
B-PATH
REG0 00D8 00D8 00D8 00D8 00D8 00D8 REG1 6000 6000 6108 6108 6181 6181
Cascade Latency
2000 9E00 2000 9E00 2000 9E00
coefficients stored coefficient register each filter cell. Coefficient registers used full rate mode. store coefficients h(k) register each filter cell memory addresses BASE+4*k+1, where BASE A-path cascaded filters B-path filters, ranges from filters without symmetry, ranges from N/2-1 filters with even symmetry, ranges from (N-1)/2 filters with symmetry. store coefficients register each filter cell addresses BASE+4*k+3. control register settings Table assume coefficients stored coefficient register each filter cell. register each cell 0020HEX REG0 values shown Table coefficient access logic within each filter cell synchronized clock (CK) that user switch between taps stored register register without causing undesirable transients filter's operation. This useful adaptive filter applications.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
HALF RATE
number taps filter doubled data rate into chip half clock rate. this mode each filter cell stores filter coefficients performs multiplications output sample. cells' delay lines adjusted that feed-forward feedback data samples delayed within each filter cell. accumulator filter path sums products give half rate output. chip configured half rate mode using control settings shown Table
Table Half Rate Mode Control Register Settings Symmetry
None Even
Dual Path Cascaded
Dual Cascaded Dual Cascaded Dual Cascaded
Taps
A-PATH
REG0 638B 638B 638B 638B 638B 638B REG1 AE00 AE28 A218 A228 A294 A2A8
B-PATH
REG0 438B 438B 438B 438B 438B 438B REG1 AE00 AE00 A218 A218 A294 A294
Cascade Latency
2000 5E00 2000 5E00 2000 5E00
coefficients stored coefficient registers each filter cell registers store coefficients h(k) registers each filter cell memory addresses: BASE+2*k even BASE+2*k-1 odd. registers store coefficients addresses BASE+2*k+2 even BASE+2*k+1 odd. Where BASE A-path cascaded filters, B-path filters. switch from using registers registers 0020HEX REG0 values shown Table Register switching synchronized chip clock order prevent unwanted transients.
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GC2011A 3.3V DIGITAL FILTER CHIP QUARTER RATE
SLWS129A
number taps filter quadrupled data rate into chip quarter clock rate. this mode each filter cell stores four filter coefficients performs multiplications output sample. cells' delay lines adjusted that four feed-forward four feedback data samples delayed within each filter cell. accumulator filter path sums products give quarter rate output. chip configured quarter rate mode using control settings shown Table
Table Quarter Rate Mode Control Register Settings Symmetry
None Even
Dual Path Cascaded
Dual Cascaded Dual Cascaded Dual Cascaded
Taps
A-PATH
REG0 A202 A202 A202 A202 A202 A202 REG1 8E00 8E28 9018 9028 9094 90A8
B-PATH
REG0 8202 8202 8202 8202 8202 8202 REG1 8E00 8E00 9018 9018 9094 9094
Cascade Latency
2000 5E00 2000 5E00 2000 5E00
coefficients stored filter cells using formula: Store h(k) memory address BASE+k. where BASE A-path cascaded filters B-path filters. four coefficients active within each filter cell user switch between banks filter coefficients. change update coefficients quarter rate mode, user should SYNC_COEF control bit. When set, this synchronizes control write operation data clock order prevent filter transients "glitches" asynchronous coefficient changes. This allows single coefficients updated synchronously
DOUBLE RATE
chip will filter data samples which received twice clock rate. user must split data into data streams, each clock rate, containing even time samples containing time samples. even data stream then used A-in input data stream used B-in input. chips required perform filtering, even time outputs time outputs. filtered samples output A-out pins each chip. filter intended decimate filter, then only chip needed since only even time output samples need generated. double rate mode control register settings shown Table
Table Double Rate Mode Control Register Settings Output
Even Output chip Output chip
Symmetr
None None
A-PATH B-PATH Cascade Output Taps Latency REG0 REG1 REG0 REG1
60d8 60d8 00d8 00d8 6000 6108 6000 6108 00D8 00D8 20D8 20D8 6000 6181 6000 6181 2000 2000 2000 2000 0048 0048 0048 0048
filter coefficients h(k) stored addresses: 128+2*k+1 even, 192+2*k-1 odd, where ranges from h(31) center symmetry filters.
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GC2011A 3.3V DIGITAL FILTER CHIP DECIMATION
SLWS129A
common filtering operation pass filter input signal then reduce (decimate) sample rate factor four. sample rate reduction performed only calculating every other every fourth output sample. This allows number taps filter doubled quadrupled. Table shows control register settings decimation modes.
Table Decimation Mode Control Register Settings Rates
Full
Half
Symmetr
None Even
A-PATH B-PATH Cascade Dual Path Taps Latency Cascaded Storagea REG0 REG1 REG0 REG1
Dual Cascaded Dual Cascaded Dual Cascaded Dual Cascaded Dual Cascaded Dual Cascaded 208B 208B 208B 208B 208B 208B 2002 2002 2002 2002 2002 2002 2E00 2E28 2E12 2E28 2E91 2EA8 0200 0228 0214 0228 0292 02A8 008B 008B 008B 008B 008B 008B 0002 0002 0002 0002 0002 0002 2E00 2E00 2E12 2E12 2E91 2E91 0200 0200 0214 0214 0292 0292 2000 5E00 2000 5E00 2000 5E00 2000 5E00 2000 5E00 2000 5E00
Quarter
None Even
half rate coefficient storage described Section 3.2. quarter rate storage described Section 3.3.
decimate filter coefficients should designed with passband between FS/4 stopband from FS/4 FS/2, where input data rate. decimate filter (full rate quarter rate out) filter should designed with passband between FS/8 stopband above FS/8. filter coefficients decimation modes stored using registers described half rate quarter rate operation. decimation modes which result half rate output samples half rate mode coefficient registers described Section 3.2. quarter rate outputs quarter rate coefficient storage described Section 3.3.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
INTERPOLATION
Another common filtering application increase signal's sample rate through interpolation. Interpolation performed inserting zeros between input samples double quadruple sample rate, then pass filter result. interpolation modes GC2011A chip automatically zero pads input pass filters result. interpolation modes double quadruple number taps implemented each filter cell. input sample rate half fourth clock rate shown Figure output rate clock rate.
Table Interpolation Mode Control Register Settings Rates
Full Half
Double Full
Symmetr
None
A-PATH B-PATH Cascade Dual Path Taps Latency Cascaded Storagea REG0 REG1 REG0 REG1
Dual Dual Cascaded Dual Cascaded Dual Cascaded 20D8 6388 6388 6388 6388 A200 A200 6108 2E00 2E28 2E91 2EA8 0000 0028 20D8 4388 4388 4388 4388 8200 9200 6181 2E00 2E00 2E91 2E91 0000 0000 2000 2000 5E00 2000 5E00 2000 5E00 Text
Quarter
Full
None
half rate coefficient storage described Section 3.2. double full rate storage Section 3.8.
interpolate (quarter rate full rate out) mode coefficient storage reversed within each filter cell. interpolate coefficients, h(k), stored memory address BASE+k+0 modulo-4 memory address BASE+k+2 modulo-4 memory address BASE+k+0 modulo-4 memory address BASE+k-2 modulo-4 where BASE A-path cascaded filters B-path filters. example, Coefficient Memory address h(0) 128+0 h(1) 128+3 h(2) 128+2 h(3) 128+1 h(4) 128+4 h(5) 128+7 h(6) 128+6 h(7) 128+5 h(8) 128+8 h(9) 128+11 etc.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
DHILBERT TRANSFORM FILTERS
Hilbert transform filter converts real signals complex signals passing signal's positive spectral frequencies rejecting negative frequencies. example, sinewave frequency both positive frequency component ejwt negative frequency component e-jwt. Hilbert transform sinewave will just positive component ejwt. coefficients Hilbert transform generated designing linear phase pass filter with passband from FS/4 stopband from FS/4 FS/2, where signal's sample rate. pass filter's impulse response then mixed centered FS/4 multiplying coefficients sequence: example, coefficients: would become: (jh0, -h1,-jh2,
jh4, -h5,-jh6,
jh6, -h5,-jh4, -h5,
jh2, -h1,-jh0). -h1,
These coefficients then split into real coefficients: -h5, -h1, imaginary coefficients: -h2, (h0, -h6,
-h4,
-h0).
seen this example, real coefficients Hilbert transform filter have symmetry with center non-zero every other equal zero. imaginary coefficients have negative symmetry. special, important, version Hilbert transform exists when filter half-band symmetry. Half-band symmetry forces real coefficients except center zero. real half filter, half-band Hilbert Transform, therefore, just delay line. following table shows configure GC2011A chip Hilbert Transform. A-path used real part B-path imaginary part.
Table Hilbert Transform Mode Control Register Settings Dual Path Cascaded
Dual
Taps
A-PATH
REG0 60C8 REG1 2E84
B-PATH
REG0 20C8 REG1 2E78
Cascade Latency
2000
Since coefficients symmetric, only pass filter coefficients stored chip. low-pass filter coefficients h(k), where h(31) center tap, then coefficient register each filter cell loaded Store -h(4k) memory address 192+8*k Store -h(4k+1) memory address 128+8*k Store +h(4k+2) memory address 196+8*k Store +h(4k+3) memory address 132+8*k Note that coefficients stored A-path, that even coefficients stored B-path. Also note that every other every other even coefficient negated. half-band Hilbert transform only h(31) will non-zero A-path.
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SLWS129A
REAL COMPLEX QUADRATURE DOWN CONVERT
chip convert from real data complex data mixing data down FS/4, pass filtering
result then decimating factor two. control register settings this mode shown Table
Table Real Complex Conversion Mode Control Register Settings Rates
Double
Full Half Quarter
Symmetr
A-PATH B-PATH Cascade Taps Latency REG0 REG1 REG0 REG1
24D8 248B 2402 6B8B AE02 6108 2E12 0214 A218 9018 04D8 048B 0402 2B8B 6E02 6181 2E91 0292 A294 9094 2000 2000 2000 2000 2000
Full Half
Half Quarter
double rate input mode assumes even time samples A-path inputs time samples B-path inputs. real output A-out imaginary output B-out. pass filter coefficients h(k) stored that even coefficients stored A-path filter cells coefficients stored B-path filter cells. lowpass filter should designed frequencies above FS/4 double full, full half, half quarter modes, where input sample rate. frequencies FS/8 FS/16 double half double quarter modes, respectfully. double rate full rate mode coefficients stored register each filter cell. this mode store h(k) addresses: 128+2*k+1 even, 192+2*k-1 odd, where ranges from h(31) center tap. double full rate half rate modes coefficients stored registers each filter cell. this mode store h(k) addresses: 128+k modulo 192+k-1 modulo 128+k-1 modulo 192+k-2 modulo where ranges from h(63) center tap. double half rate quarter rate modes coefficients stored registers each filter cell. this mode store h(k) addresses: 128+k/2 even 192+(k-1)/2 where ranges from 127. h(127) center tap.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
COMPLEX REAL QUADRATURE UPCONVERT
Complex data converted real data doubling sample rate, mixing data FS/4 saving
real part. control settings this mode shown Table
Table Complex Real Conversion Mode Control Register Settings Rates
Full Half Quarter
Double Full Half
Symmetr
A-PATH B-PATH Cascade Output Taps Latency REG0 REG1 REG0 REG1
20D8 638B A202 6108 A218 9018 00D8 438B 8202 6181 A294 9094 2000 2000 2000 0001 0012 0033
filter interpolate pass filter with pass band from FS/4 stop band from FS/4 FS/2, where output sample rate. even coefficients filter stored A-path filter cells odd-coefficients stored B-path filter cells. real half complex samples input A-in, imaginary half input B-in. real results output A-out modes except double rate output mode. double rate output mode even time samples output A-out time samples output B-out. full rate double rate mode coefficients h(k) stored register each filter cell. this mode store h(k) addresses: 128+2*k+1 even, 192+2*k-1 odd, where ranges from h(31) center tap. half rate full rate mode coefficients stored registers each filter cell. this mode store h(k) addresses: 128+k modulo 192+k-1 modulo 128+k-1 modulo 192+k-2 modulo where ranges from h(63) center tap. quarter rate half rate mode coefficients stored registers each filter cell. this mode store h(k) addresses: 128+k/2 even 192+(k-1)/2 where ranges from 127. h(127) center tap.
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
3.10
DIAGNOSTICS
user ramp input snapshot memory perform diagnostics chip. suggested diagnostic procedure configure chip will used normal operation, select ramp data input source (see Section 6.1), counter control 0FFF (see Section 6.4), snapshot controls capture output samples (see Section 6.7). snapshot should triggered with delay blocks from trigger. delay guarantees that filter flushed settled before snapshot taken. user then read snapshot from memory compare against known snapshot save future comparison. suggested diagnostic configurations given below along with expected snapshot output. These configurations coefficient registers forward reverse delay storage registers. diagnostic procedure each test configuration table Load control registers with values shown Table Load coefficients h(k) addresses 128+k 127. start snapshot register writing 0413HEX address Wait, while reading address until register value 0463HEX. Read addresses through through compare them expected values Table
Table Diagnostic Test Configuration
Parameter
h(k)
Address
modulo modulo modulo modulo
Test
EAAA FFFF 0F0F 0001 C402 0292 D402 0214 1000 0FFF 1035 0041 004E 004F 0403 0000
Test
1555 E000 F0F0 1FFF E402 0108 E402 02F2 2F00 0FFF 103A 0041 004F 005F 0403 0000
A_PATH_REG0 A_PATH_REG1 B_PATH_REG0 B_PATH_REG1 CASCADE COUNTER GAIN OUTPUT SNAP_REGA SNAP_REGB SNAP_REGC NEW_MODES
Table Expected Test Results
Address
Test
C302 C2E2 C2C2 C2A2 C282 C262 C243 C223
Test
A635 A606 A5D7 A5A8 A578 A549 A51A A4EA
Address
Test
C621 CA1F CE1E D21D D61B DA1A DE19 E217
Test
C3D3 C8BD CDA6 D290 F692 0094 0A97 1499
Address
Test
3BC2 3BE2 3C02 3C22 3C42 3C62 3C82 3CA2
Test
4BAD 4B7E 4B4F 4B1F 4AF0 4AC1 4A91 4A62
Address
Test
3CC2 3CE2 3D02 3D22 3D41 3D61 3D81 3DA1
Test
4A33 4A04 49D4 49A5 4976 4947 4917 48E8
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SLWS129A
PACKAGING QUAD FLAT PACK (QFP) PACKAGE
AI11 (MSB) AI10 BI11 (MSB) BI10 (MSB) AO15 AO14 AO13 AO12 AO11 AO10
MODE OUTPUT WORD
MODE INPUT WORD
(0.65mm)
(MSB) BO15 BO14 B013 BO12 BO11 BO10 (MSB) GC2011A
GRAYCHIP GC2011A-PQ DIGITAL FILTER MMMMMLLL YYWW
QUAD FLAT PACK PACKAGE GC2011A-PQ Enhanced Thermal Plastic Package GC2011A-CQ Ceramic Package (special order only)
Package Markings: MMMMM Mask Code Number YYWW Date Code
DIMENSION (width pin) (width body) (pin pitch) (pin width) (leg length) (height) (pin thickness) PLASTIC 31.2 (1.228") 28.0 (1.102") 0.65 (0.026") 0.30 (0.012") 0.88 (0.035") 4.07 (0.160") 0.17 (0.007") CERAMIC 32.0 (1.260") 28.0 (1.102") 0.65 (0.026") 0.30 (0.012") 0.70 (0.028") 3.25 (0.128") (0.008")
(MSB) (GND) (R/W) (CS) CKEN
PINS: PINS: UNUSED PINS: 120, NOTE: 0.01 DECOUPLING CAPACITORS SHOULD PLACED CLOSE POSSIBLE MIDDLE EACH SIDE CHIP
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(1.1")
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
Table Listing Package
NAME
(CS) (GND) (R/W) CKEN
NAME
BI11 BI10 AI11 AI10
NAME
BO10 BO11 BO12 BO13 BO14 BO15
NAME
AO10 AO11 AO12 AO13 AO14 AO15
NOTE: names parenthesis indicate GC2011 names.
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BALL GRID ARRAY (PBGA) PACKAGE
AI11 (MSB) AI10 BI11 (MSB) BI10 (MSB) AO15 AO14 AO13 AO12 AO11 AO10
0.36
1.53
MODE OUTPUT WORD
MODE INPUT WORD
GRAYCHIP GC2011A-PB DIGITAL FILTER MMMMM YYWW
(MSB) BO15 BO14 B013 BO12 BO11 BO10 (MSB) GC2011A
VIEW
MMMMM Mask Code Number YYWW Date Code
0.53
(MSB) (GND) (R/W) (CS) CKEN (THERMAL):
BOTTOM VIEW
DIMENSION (width body) (width cover) (ball pitch) (ball width) (overhang) (overall height) (ball height) (substrate thickness) (CORE): (PAD RING): GND: 0.53 1.53 0.36 TOLERANCE
C10, D10, D12, D13, M10, N10, N11, N12, A10, B14, E11, E13, M11, N13, P10, C13,
UNUSED: NOTE: 0.01 DECOUPLING CAPACITORS SHOULD PLACED CLOSE POSSIBLE MIDDLE EACH SIDE CHIP
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Table Listing Package (Top View)
AO11 AO13 PVCC CVCC AO10 PVCC
PVCC AO12 AO15 CVCC CVCC
PVCC AO14 CVCC
BO15 PVCC
BO13 CVCC BO14 CVCC
BO10 BO11 BO12
CVCC CVCC
PVCC CVCC CVCC
CVCC AI10 CVCC
CVCC PVCC CVCC
PVCC BI11
TGND TGND
TGND TGND
AI11
CVCC
CVCC CVCC
CVCC CKEN
CVCC
CVCC
CVCC CVCC
BI10 CVCC
unused ball CVVC Core PVCC TGND Thermal Ground
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SLWS129A
DESCRIPTIONS
SIGNAL AI[0:11] DESCRIPTION A-PATH INPUT DATA. Active high two's complement input samples path samples clocked into chip rising edge clock. B-PATH INPUT DATA. Active high two's complement input samples path samples clocked into chip rising edge clock. CLOCK INPUT. Active high clock input chip. CKEN signals clocked into chip rising edge this clock. DAV, AOF, signals clocked rising edge this clock. CLOCK ENABLE INPUT. Active clock enable input chip. This signal gated with generate chip's internal clock. CKEN clocked into chip rising edge will enable disable following clock edge. level CKEN enables clock edge. SYNC INPUT. Active sync input chip. timers, accumulators, control counters are, synchronized This sync clocked into chip rising edge clock. SNAPSHOT SYNC. Active snapshot sync provided synchronously start data snapshot. This signal clocked into chip rising edge clock. A-PATH OUTPUT DATA. Active high A-path output samples output words these pins. bits clocked rising edge clock. B-PATH OUTPUT DATA. Active high B-path output samples output words these pins. bits clocked rising edge clock. A-PATH OUTPUT ENABLE. Active A[0:15] output pins into high impedance state when this high. B-PATH OUTPUT ENABLE. Active B[0:15] output pins into high impedance state when this high. DATA VALID STROBE. Programmable active high level This strobe output synchronous with data words. strobe used decimate, half rate, quarter rate output modes indicate when output words valid. high/low polarity strobe programmable. A-PATH OVERFLOW Active high This signal goes high clock cycle each time there overflow A-path gain output. B-PATH OVERFLOW Active high This signal goes high clock cycle each time there overflow B-path gain output. SYNC OUT. Active This signal either input sync delayed clock cycles, shot sync internal counter's terminal count strobe CONTROL DATA BUS. Active high This control data bus. Control register contents loaded into chip read from chip through these pins. chip will only drive these pins when high. CONTROL ADDRESS BUS. Active high These pins used address control registers, coefficient registers, snapram memory within chip. READ, WRITE, CHIP ENABLE STROBES. active These pins control reading writing control data. held chip will operate GC2011 read/write mode, where GC2011's control GC2011's control strobe. (See Section 2.2)
BI[0:11]
CKEN
AO[0:15]
BO[0:15]
C[0:15]
A[0:8]
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
CONTROL REGISTERS
chip configured controlled through sixteen control registers. These registers accessed reading writing using control pins (CE, A[0:8], C[0:15]) described previous section. register names their addresses are:
ADDRESS
NAME APATH_REG0 APATH_REG1 BPATH_REG0 BPATH_REG1 CASCADE_REG COUNTER_REG GAIN_REG OUTPUT_REG
ADDRESS
NAME SNAP_REGA SNAP_REGB SNAP_REGC ONE_SHOT NEW_MODES unused Coefficient Registers Snapram
following sections describe each these registers. type each register either indicating whether read only read/write. bits active high. APATH_REG0, APATH_REG1, BPATH_REG0, BPATH_REG1, CASCADE_REG OUTPUT_REG control register settings given Section will configure chip into most common modes operation. This Section describes meanings individual register bits used those modes.
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GC2011A 3.3V DIGITAL FILTER CHIP A-PATH B-PATH CONTROL REGISTER
Control registers APATH_REG0 BPATH_REG0 identical described here.
ADDRESS ADDRESS (LSBs) TYPE APATH_REG0 BPATH_REG0 NAME ACCUM DESCRIPTION
SLWS129A
This field controls accumulator according following table: ACCUM DESCRIPTION don't accumulate (full rate output) accumulate sums (quarter rate) accumulate sums (half rate) ACCUM control also sets output data rate shown Figure filter cell adder (See Figure unsigned mode when this set. This five field controls four coefficients used within filter cells. controls are: COEF_SEL DESCRIPTION (HEX) coefficient coefficient toggle between registers toggle between registers cycle through four registers This field sets input rate follows: (See Figure RATE DESCRIPTION full rate input quarter rate input half rate input These three bits control input sample negation follows: NEG_IN DESCRIPTION don't negate negate even time full rate samples negate time half rate samples negate even time quarter rate samples always negate negate time full rate samples negate even time half rate samples negate time quarter rate samples where definition even time samples shown Figure Select input A-in when high, B-in when low. Selects input delay counter input follows: DELAY_SEL DESCRIPTION delay clock delay clock delay counter input
UNSIGNED COEF_SEL
RATE
10-12
NEG_IN
14,15(MSB)
AB_SEL DELAY_SEL
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
operation these control bits illustrated following figures.
TIME Full Rate Half Rate Quarter Rate
even
even
even
even
even
DEL_SEL delay)
even
even
Full Rate Half Rate Quarter Rate
even
even
even
even
DEL_SEL clock delay)
even
Full Rate Half Rate Quarter Rate
even
even
even
even
DEL_SEL clock delay)
Figure Input Timing
NOTES: strobe appears clocks after every 16*(CNT+1) clocks thereafter. input delays selected DEL_SEL control clock cycle delays, sample delays. These delays occur before input rate circuit captures samples shown above.
TIME Full Rate
even
even
even
even
even
(ACCUM 0,1, output always high)
Half Rate
even
even
(ACCUM even even
Quarter Rate
(ACCUM
Figure Output Timing
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A-PATH B-PATH CONTROL REGISTER
Control registers APATH_REG1 BPATH_REG1 identical described here.
ADDRESS ADDRESS (LSBs) TYPE
APATH_REG1 BPATH_REG1 NAME FEED_BACK DESCRIPTION This field controls symmetric filter feedback mode according following table: FEED_BACK DESCRIPTION (HEX) symmetry full rate symmetry full rate even symmetry A-path cascade mode decimate interpolate symmetry decimate even symmetry decimate symmetry decimate even symmetry half quarter rate symmetry half quarter rate even symmetry NOTE: A-path FEED_BACK control must cascade mode.
ANTI_SYM
Anti-symmetric filters implemented setting this described below. This complements (bitwise inverts) feedback data. EXCEPTION: cascade mode A-PATH ANTI_SYM must filters. This carry input filter cell's adder (See Figure This create anti-symmetric filters. cascade mode this cleared both paths create symmetric filter both paths create anti-symmetric filter. This must odd-symmetry filters cleared even symmetric filters. These five bits control filter cells' reverse delays. These bits used FEED_BACK=00 symmetry) REV_DELAY DESCRIPTION (HEX) symmetry full rate filters decimate half rate filters decimate integrate filters quarter rate filters These bits control filter cells' forward delays. FOR_DELAY DESCRIPTION decimate interpolate filters decimate interpolate filters full rate filters quarter rate filters half rate filters
8-12
ODD_SYM REV_DELAY
13-15(MSB)
FOR_DELAY
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CASCADE MODE CONTROL REGISTER
This register controls cascade mode synchronous coefficient storage mode.
ADDRESS (LSB) TYPE
CASCADE_REG NAME SYNC_COEF DESCRIPTION This forces filter coefficient data synchronized system clock before they stored filter cell coefficient registers. NOTE: write cycle control strobe, when storing coefficient this mode, must active least data clock cycles. Unused. This field controls cascade mode according following table: CASCADE DESCRIPTION (HEX) Dual path mode. Cascade mode non-full rate filters Cascade mode full rate filters.
9-15(MSB)
CASCADE
enable cascade mode user must also ANTI_SYM FEED_BACK APATH_REG1. cascade mode following control bits used: APATH_REG0: ACCUM APATH_REG1: ODD_SYM BPATH_REG0: RATE,NEG_IN, AB_SEL, DELAY_SEL, COEF_SEL BPATH_REG1: REV_DELAY, FOR_DELAY These bits treated "don't cares". SYNC_COEF mode only needed when user dynamically changing filter coefficients decimate interpolate quarter rate modes. These modes four coefficient registers each filter cell. Otherwise user dynamically change filter coefficients switching between banks filter coefficients using COEF_SEL control described Section 6.1.
COUNTER REGISTER
This register sets cycle time internal counter.
ADDRESS 0-15 TYPE
COUNTER_REG NAME DESCRIPTION counter control word. counter preset (16*CNT+15) counts down zero, then starts over again.
terminal count strobe generated counter when preset every time reaches zero. delay from first strobe clocks. strobe will then repeat every 16*(CNT+1) clocks.
GAIN REGISTER
gain register controls filter's output gain rounding. Note that gain setting synchronized data clock that gain changes will cause "glitches" output when changed. gain rounding control common both paths chip.
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ADDRESS 8-14 TYPE
GAIN_REG NAME ROUND DESCRIPTION gain fraction. gain exponent. Controls output rounding according following table: ROUND DESCRIPTION (HEX) Truncate Round MSBs Round MSBs Round MSBs Round MSBs Round MSBs Round MSBs Round MSBs Unused
(MSB)
chip's output gain using according following formula: GAIN =2(S-20)(1+F/16)(DC_GAIN) Where DC_GAIN filter coefficients. Unity gain, according this formula, will the12 input data (AI11 BI11) into selected output word (AO15 BO15). filter path output rounded number most significant bits selected round control. gain circuit output saturated plus minus full scale GAIN setting causes overflow. output pins will high whenever overflow detected A-Path B-path gain circuit. example: gain filter coefficients (i.e., coefficients 215), then overall gain filter unity setting
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GC2011A 3.3V DIGITAL FILTER CHIP OUTPUT MODE REGISTER
output mode register controls output formatting.
ADDRESS (LSBs) TYPE OUTPUT_REG NAME NEG_OUT DESCRIPTION
SLWS129A
This field controls output sample negation follows: NEG_OUT DESCRIPTION don't negate negate full rate output samples negate half rate output samples negate quarter rate output samples When negation enabled circuit will negate even time A-Path outputs time B-path outputs where definition even time samples shown Figure user desires negate time A-path outputs, negate even time B-path outputs, then NEG_IN control should used negate path's input. Enables mode. PATH_ADD 24BIT_OUT must also this register. A-path B-path must configured same except for: B-path must unsigned mode, A-path must zero, A-path AB_SEL B-path AB_SEL Enables output mode. B-path output samples output A-out B-out pins follows: upper bits output A-out pins, lower bits output upper bits B-out pins. MUX_MODE A-path B-path outputs multiplexed together A-out pins. B-out pins cleared. MUX_MODE settings are: MUX_MODE DESCRIPTION mode off, half rate outputs, quarter rate outputs multiplexed half rate outputs will generate full rate output stream, multiplexed quarter rate outputs will generate half rate stream. A-path sample output first, followed B-path sample. Adds A-path B-path results. result output B-out pins unless 24BIT_OUT control enabled. Invert polarity data valid (DAV) strobe. Figure shows with DAV_POLARITY unused
24BIT_MODE
24BIT_OUT
MUX_MODE
8-15
PATH_ADD DAV_POLARITY
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GC2011A 3.3V DIGITAL FILTER CHIP SNAPSHOT MODE CONTROL REGISTERS
SLWS129A
snapshot memory divided into halves, words bits each. SNAP_REGA controls A-half snapshot memory, SNAP_REGB controls B-half.
ADDRESS ADDRESS (LSBs) TYPE SNAP_REGA SNAP_REGB NAME SEL_IN DESCRIPTION Selects snapshot source SEL_IN DESCRIPTION IB[0:11] IA[0:11] OA[0:15] OB[0:15] Determines rate which samples stored according SNAP_RATE DESCRIPTION every clock, full rate samples every other clock, half rate samples invalid SNAP_DELAY every clock, quarter rate samples. Delay from snapshot trigger blocks samples until start snapshot. delay 128*SNAP_DELAY*(SNAP_RATE+1) clock cycles where SNAP_DELAY ranges from This control allows user start B-half snapshot fixed number samples after other half's snapshot. start snapshot. This control lets user start half snapshot memory other. This control reorganizes memory half into bytes instead words. upper bits input source stored. unused
SNAP_RATE
10-15(MSB)
SNAP_HOLD BYTE_MODE
BYTE_MODE memory reorganized that first bytes byte snapshot stored least significant bytes word memory second bytes stored most significant bytes word memory.
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SNAPSHOT START CONTROL REGISTER
This register controls snapshot trigger settings, snapshot read modes chip's sync modes.
ADDRESS (LSBs) TYPE
SNAP_REGC NAME TRIGGER DESCRIPTION This control sets trigger condition which will start snapshot once ARMED set. trigger conditions start: TRIGGER DESCRIPTION immediately, when strobe received, when strobe received, when strobe received. Selects whether words bytes read from snapshot memory according READ_MODE DESCRIPTION read words, read least significant bytes read most significant bytes When reading bytes, bytes placed LSBs control word sign extended. user sets this snapshot memory that will start next trigger condition. chip clears this when trigger occurs. This goes high when A-half snapshot complete. This must cleared writing zero This goes high when B-half snapshot complete. This must cleared writing zero unused This field selects sync output (SO) source SYNC_OUT DESCRIPTION delayed clocks (SYNC_OFF=0), never This disables sync input chip. counter will free when this high unused
READ_MODE
ARMED
A_DONE B_DONE SYNC_OUT
11-15
SYNC_OFF
SHOT ADDRESS
shot pulse generated writing address This write-only address. data written irrelevant.
ADDRESS ONE_SHOT
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6.10
MODES REGISTER
This register controls modes added GC2011A chip. This address used GC2011 chip. Bits 8,9,12,13,14,and power low.
ADDRESS (LSBs) TYPE only NEW_MODES NAME REVISION POWER_DOWN DESCRIPTION These bits read back current mask revision number. Forces chip static power down mode when set.
DISABLE_CLOCK_LOSS_DETECT Turns clock loss detect circuit when set. This should kept low. POWER_DOWN_STATUS These bits when chip power down state, either because (POWER_DOWN) above set, because clock loss been detected. These bits normally high.
10,11
only
(MSB)
INV_MSB_AOUT INV_MSB_BOUT INV_MSB_AIN INV_MSB_BIN
Inverts A-output when set. Inverts B-output when set. Inverts A-input when set. Inverts B-input when set.
REVISION field used determine mask revision number GC2011A. mask revision numbers mask change descriptions shown Table below (the mask codes printed GC2011A package).
Table Mask Revisions
Mask Revision Number (bits 0-7) Mask Code Package 55585B Original
Release Date
Description
February 1999
INV_MSB control bits will invert inputs outputs order convert from offset binary two's complement formats. input data offset binary, then INV_MSB_AIN and/or INV_MSB_BIN control bits should set. output data needs converted offset binary, then INV_MSB_AOUT and/or INV_MSB_BOUT control bits should set.
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SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings PARAMETER Supply Voltage Input voltage (undershoot overshoot) Storage Temperature Lead Soldering Temperature seconds) SYMBOL TSTG -0.3
-0.5
VCC+0.5
UNITS
NOTES
RECOMMENDED OPERATING CONDITIONS
Table Recommended Operating Conditions PARAMETER Supply Voltage Temperature Ambient, flow Junction Temperature Notes:
Thermal management required keep below full rate operation. Table below.
SYMBOL
UNITS
NOTES
THERMAL CHARACTERISTICS
Table Thermal Data THERMAL CONDUCTIVITY Theta Junction Ambient Theta Junction Case GC2011A-PB SYMBOL Watts Watts
GC2011A-PQ UNITS
°C/W °C/W
Note: flow will reduce highly recommended.
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CHARACTERISTICS
parameters industrial temperature range ambient unless noted.:
Table Operating Conditions 3.3V PARAMETER
Voltage input Voltage input high Input current (VIN Voltage output (IOL 2mA) Voltage output high (IOH -2mA) Data input capacitance (All inputs except C[0:15]) Clock input capacitance input) Control data capacitance (C[0:15] pins)
SYMBOL
CCON Typical
UNITS
NOTES
Typical Typical Typical
Notes:
Controlled design process directly tested. Verified initial parts evaluation. Each part tested 85°C given specification.
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SLWS129A
CHARACTERISTICS
Table Characteristics (-40 +85oC Ambient, unless noted) 3.1V 3.5V PARAMETER SYMBOL
Note 35.0 10.0 500.0 tCKL tCKH tDLY tCSU tCHD tCSPW tCDLY ICCQ 0.01 Note 30.0
UNITS
NOTES
Clock Frequency Clock period (Below VIL) Clock high period (Above VIH) Data setup before goes high (AI, CKEN) Data hold time after goes high Data output delay from rising edge (AO, DAV, Data tristate delay (AO, from BOE) Tristate data output delay (AO, AOF, valid from BOE) Control Setup before during read, during write) Figure Control hold after CE,RE, high during read, during write) Figure Control enable pulse width (Write operation) Figure Control output delay (Read Operation) Figure Control tristate delay after high. Figure Quiescent supply current (VIN=0 VCC, POWER_DOWN=1) Supply current (FCK MHz)
Notes:
Controlled design process directly tested. Verified initial part evaluation. Each part tested given specification. chip operate properly clock frequencies below MAX. Capacitive output load 20pf. Delays measured from rising edge clock output level rising above falling below 1.3v. tCSPW must least five clock cycles wide SYNC_COEF control (See Section 6.3). Capacitive output load 80pf. Current changes linearly with voltage clock speed. (MAX) 500mA
Texas Instruments Incorporated
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
APPLICATION NOTES POWER GROUND CONNECTIONS
GC2011A chip very high performance chip which requires solid power ground connections avoid noise pins. possible GC2011A chip should mounted circuit board with dedicated power ground planes with least decoupling capacitors (0.01 adjacent each GC2011A chip. dedicated power ground planes possible, then user should place decoupling capacitors adjacent each pair.
IMPORTANT
GC2011A chip operate properly these power ground guidelines violated.
STATIC SENSITIVE DEVICE
GC2011A chip fabricated high performance CMOS process which sensitive high voltage transients caused static electricity. These parts permanently damaged static electricity should only handled static free environments.
OPERATION
Care must taken generating clock when operating GC2011A chip full clock rate. user must insure that clock above volts least nanoseconds below volt least nanoseconds.
REDUCED VOLTAGE OPERATION
power consumed GC2011A chip greatly reduced operating chip lowest
voltage which will meet application's timing requirements.
Texas Instruments Incorporated
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
SYNCHRONIZING MULTIPLE GC2011A CHIPS
system containing bank GC2011A chips will need synchronized that output data from each chip aligned. This especially important half rate quarter rate modes. synchronization achieved connecting inputs chips system sync input. system sync available, then counter within GC2011A chip used generate one. strobe counter output from "master" GC2011A used input other GC2011A chips. should also used (snap strobe) input chip, including master chip, that snapshot memories within chips synchronized. example, chips operated parallel complex filter processing complex data. suggested configuration these chips shown Figure
GC2011ABO
IOUT
"Slave"
SYNC
GC2011ABO
QOUT
"Master"
SYNC
Figure Processing Complex Input Data
this configuration slave chip generates I-outputs master chip generates Q-outputs. chips synchronized connecting signal from master chip inputs both chips input slave chip. system sync, available, used synchronize master chip rest system. system sync available, then shot strobe generated slave chip output pin, routed into input master chip. This shown dashed line Figure from master chip then used system sync rest system.
Texas Instruments Incorporated
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GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
PACKAGING QUAD FLAT PACK (QFP) PACKAGE
AI11 (MSB) AI10 BI11 (MSB) BI10 (MSB) AO15 AO14 AO13 AO12 AO11 AO10
MODE OUTPUT WORD
MODE INPUT WORD
(0.65mm)
(MSB) BO15 BO14 B013 BO12 BO11 BO10 (MSB) GC2011A
GC2011A-PQ DIGITAL FILTER MMMMMLLL YYWW
QUAD FLAT PACK PACKAGE GC2011A-PQ Enhanced Thermal Plastic Package GC2011A-CQ Ceramic Package (special order only)
Package Markings: MMMMM Mask Code Number YYWW Date Code
DIMENSION (width pin) (width body) (pin pitch) (pin width) (leg length) (height) (pin thickness) PLASTIC 31.2 (1.228") 28.0 (1.102") 0.65 (0.026") 0.30 (0.012") 0.88 (0.035") 4.07 (0.160") 0.17 (0.007") CERAMIC 32.0 (1.260") 28.0 (1.102") 0.65 (0.026") 0.30 (0.012") 0.70 (0.028") 3.25 (0.128") (0.008")
(MSB) (GND) (R/W) (CS) CKEN
PINS: PINS: UNUSED PINS: 120, NOTE: 0.01 DECOUPLING CAPACITORS SHOULD PLACED CLOSE POSSIBLE MIDDLE EACH SIDE CHIP
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(1.1")
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
BALL GRID ARRAY (PBGA) PACKAGE
AI11 (MSB) AI10 BI11 (MSB) BI10 (MSB) AO15 AO14 AO13 AO12 AO11 AO10
0.36
1.53
MODE OUTPUT WORD
MODE INPUT WORD
GC2011A-PB DIGITAL FILTER MMMMM YYWW
(MSB) BO15 BO14 B013 BO12 BO11 BO10 (MSB) GC2011A
VIEW
MMMMM Mask Code Number YYWW Date Code
0.53
(MSB) (GND) (R/W) (CS) CKEN (THERMAL):
BOTTOM VIEW
DIMENSION (width body) (width cover) (ball pitch) (ball width) (overhang) (overall height) (ball height) (substrate thickness) (CORE): (PAD RING): GND: 0.53 1.53 0.36 TOLERANCE
C10, D10, D12, D13, M10, N10, N11, N12, A10, B14, E11, E13, M11, N13, P10, C13,
UNUSED: NOTE: 0.01 DECOUPLING CAPACITORS SHOULD PLACED CLOSE POSSIBLE MIDDLE EACH SIDE CHIP
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GC2011A 3.3V DIGITAL FILTER CHIP March 2000 Information

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