Octal Flip-Flop with Reset 'AC273 'ACT273 devices octal D-type fl
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CD54AC273, CD74AC273 CD54ACT273, CD74ACT273
Octal Flip-Flop with Reset
'AC273 'ACT273 devices octal D-type flip-flops with reset that utilize advanced CMOS logic technology. Information input transferred output positive-going edge clock pulse. eight flip-flops controlled common clock (CP) common reset (MR). Resetting accomplished voltage level independent clock.
August 1998 Revised July 2002
Features
Buffered Inputs Typical Propagation Delay 6.5ns 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC273E TEMPERATURE RANGE 70oC -40oC 85oC -55oC 125oC -55oC 125oC 70oC -40oC 85oC -55oC 125oC -55oC 125oC 70oC -40oC 85oC -55oC 125oC 70oC -40oC 85oC -55oC 125oC PACKAGE PDIP
CD54AC273F3A CD74ACT273E
CDIP PDIP
CD54ACT273F3A
CDIP SOIC
Pinout
CD54AC273, CD54ACT273 (CDIP) CD74AC273, CD74ACT273 (PDIP, SOIC) VIEW
CD74AC273M
CD74ACT273M
SOIC
NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office ordering information.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright 2002, Texas Instruments Incorporated
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Functional Diagram
CLOCK DATA INPUTS DATA OUTPUTS
RESET
TRUTH TABLE INPUTS RESET (MR) CLOCK DATA OUTPUTS
High level (steady state), level (steady state), Irrelevant, Transition from High level, level before indicated steady-state input conditions were established.
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance, (Typical, Note Package 69oC/W Package. 58oC/W Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. package thermal impedance calculated accordance with JESD
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT UNIT LOAD 0.57
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Prerequisite Switching Function
-40oC 85oC PARAMETER TYPES Data Set-Up Time (Note (Note Hold Time Removal Time, tREM Pulse Width Pulse Width Frequency fMAX TYPES Data Set-Up Time Hold Time Removal Time Pulse Width Pulse Width Frequency tREM fMAX (Note SYMBOL -55oC 125oC UNITS
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, tPLH, tPHL (Note (Note 17.2 12.3 18.9 13.5 SYMBOL -55oC 125oC UNITS
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Propagation Delay, SYMBOL tPLH, tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Propagation Delay, Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption flip-flop. VCC2 VCC2 ACT: VCC2 VCC2 where input frequency, output frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL (Note (Note 12.3 12.3 13.5 13.5 (Note (Continued) -55oC 125oC 17.2 12.3 18.9 13.5 UNITS
-40oC 85oC
INPUT LEVEL INPUT LEVEL INPUT tPLH tREM
tPHL
tPLH
FIGURE PROPAGATION DELAY TIMES CLOCK PULSE WIDTH
FIGURE PREREQUISITE PROPAGATION DELAY TIMES MASTER RESET
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
OUTPUT LEVEL
FIGURE PREREQUISITE CLOCK
OUTPUT (NOTE) OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, Input Level Input Switching Voltage, Output Switching Voltage, 1.5V
FIGURE PROPAGATION DELAY TIMES
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Copyright 2002, Texas Instruments Incorporated
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