Mapping Controller Operating voltage: 2.7V~5.2V Built-in 32kHz os
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HT16274
Mapping Controller
Operating voltage: 2.7V~5.2V Built-in 32kHz oscillator External 32768Hz crystal oscillator frequency source input Standby current bias, 1/16 duty, frame frequency 64Hz Max. patterns, commons, segments Built-in internal resistor type bias generator wires interface data wire) kinds time base /WDT selection Time base overflow output
Built-in display address auto increment Built-in buzzer driver (2kHz/4kHz) Power down command reduces power consumption Software configuration feature Data mode Command mode instructions Three data accessing modes Provide VLCD adjust operating voltage
General Description
HT16274 peripheral device specially designed type used expand display capability. max. display segment device 1024 patterns also supports data bits interface, buzzer sound, watchdog timer time base timer functions. HT16274 memory mapping multifunction controller. software configuration feature HT16274 make suitable multiple applications including modules display subsystems. Only lines required interface between host controller HT16274. HT162X series have many kinds products that match various applications.
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HT16274
Assignment
Block Diagram
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HT16274
Assignment
Chip size: (mil)2 substrate should connected layout artwork.
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HT16274
Coordinates
-119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -119.43 -105.70 -96.18 -89.55 -77.56 -70.93 -58.95 -52.32 -40.33 -33.70 -21.72 -15.09 -3.10 3.53 15.51 22.14 34.13 40.76 52.74 59.37 71.36 77.99 89.97 96.60 108.59 115.22 119.21 119.21 101.92 88.95 79.14 66.17 57.76 51.13 18.57 11.90 5.18 -4.34 -16.83 -35.62 -45.26 -51.89 -58.52 -65.15 -71.78 -78.41 -85.04 -91.67 -98.30 -104.93 -112.11 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -112.88 -103.44 -96.82 119.21 119.21 119.21 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.45 118.87 118.87 118.87 117.81 111.18 104.55 97.92 85.93 79.31 67.32 60.69 48.71 42.08 30.09 23.46 11.48 4.84 -7.14 -13.77 -25.75 -32.38 -44.37 -51.00 -62.99 -69.61 -81.60 -88.23 -100.21 -109.74
Unit:
-90.18 -83.56 -76.93 -70.17 -58.18 -51.55 -39.57 -32.94 -20.95 -14.32 -2.34 4.29 16.28 22.91 34.89 41.52 53.51 60.14 72.12 78.75 88.27 94.90 101.53 113.18 113.18 113.18 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41 112.41
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HT16274
Description
Name
DD0~DD3
Description
Negative power supply, Ground OSCI OSCO connected 32768kHz crystal order generate system clock. system clock comes from external clock source, external clock source should connected OSCI pad. on-chip oscillator selected instead, OSCI OSCO pads left open. Positive power supply operating voltage input Time base Watchdog Timer overflow flag, NMOS open drain output frequency output pair (Tristate output buffer) connected common outputs segment outputs Chip selection input with pull-high resistor. When logic high, data command read from written HT16274 disabled. serial interface circuit also reset logic level input pad, data command transmission between host controller HT16274 enabled READ clock input with pull-high resistor. Data HT16274 clocked rising edge signal. clocked data will appear data line. host controller next falling edge latch clocked data WRITE clock input with pull-high resistor. Data DATA line latched into HT16274 rising edge signal
Serial data input/output with pull-high resistor
OSCI OSCO
13~16 17~32 33~96
VLCD T1~T4 COM0~COM15 SEG0~SEG63
Absolute Maximum Ratings*
Supply Voltage .-0.3V 5.5V Input Voltage. VSS-0.3V VDD+0.3V Storage Temperature. -50°C 125°C Operating Temperature. -25°C 75°C
*Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied exposure absolute maximum rating conditions extended periods affect device reliability.
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HT16274
D.C. Characteristics
Symbol
IDD1 IDD2 IDD3 IDD4 ISTB IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 (Ta=25°C)
Parameter
Operating Voltage Operating Current
Test Conditions
Conditions
load/LCD chip oscillator load/LCD Crystal oscillator load/LCD chip oscillator load/LCD Crystal oscillator load Power down mode DATA0~DATA3, DATA0~DATA3, VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V
Min. Typ. Max. Unit
-0.9 -1.7 -0.9 -1.7 -1.8 -1.8 -180 -140
Operating Current
Operating Current
Operating Current
Standby Current
Input Voltage
Input High Voltage
Sink Current
Source Current
DATA0~DATA3 Sink Current DATA0~DATA3 Source Current Common Sink Current
Common Source Current
Segment Sink Current
Segment Source Current
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HT16274
Test Conditions
Symbol
Parameter
Pull-High Resistor
Conditions
DATA0~DATA3,
Min. Typ. Max. Unit
A.C. Characteristics
Symbol
fSYS1 fSYS2 fLCD1 fLCD2 tCOM fCLK1 fCLK2
(Ta=25°C)
Parameter
System Clock
Test Conditions
Conditions
chip oscillator External clock source chip oscillator External clock source Number Duty cycle
Min. Typ. Max. Unit
3.34 6.67 1.67 3.34 n/fLCD
System Clock
Frame Frequency
Frame Frequency Common Period 4-Bit Data Clock Pin)
4-Bit Data Clock Pin) 4-Bit Interface Reset Pulse Width (Figure
Duty cycle Write mode Read mode Write mode Read mode
tCLK
Input Pulse Width (Figure Rise/Fall Time Serial Data Clock Width (Figure Setup Time DATA Clock (Figure Hold Time DATA Clock (Figure
tr/tf
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HT16274
Symbol
tsu1
Parameter
Setup Time (Figure Hold Time (Figure
Test Conditions
Conditions
Min. Typ. Max. Unit
Figure
Figure
Figure
Application Diagram
connection selected depending requirement host controller. Note: voltage must greater than VLCD PIN. (VDD VLCD)
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HT16274
System Architecture
Display memory structure Time base watchdog timer (WDT)
static display organized into bits stores display data. contents directly mapped contents driver. Data accessed READ, WRITE READ-MODIFY-WRITE commands. following mapping from patterns.
time base generator share same divided (/256) counter. TIMER DIS/EN/CLR, DIS/EN/CLR EN/DIS independent from each other. Once timeout occurs, will stay logic level until command issued.
Display memory strusture
Time base configurations
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HT16274
external clock selected source system frequency, command turns invalid power down mode fails carried until external clock source removed.
Buzzer tone output
following data mode command mode
Operation
READ WRITE READ-MODIFY-WRITE COMMAND
Mode
Data Data Data Command
X110 X101 X101 X100
simple tone generator implemented HT16274. tone generator output pair differential driving signals which used generate single tone.
Command format
HT16274 configured software setting. There mode commands configure HT16274 resource transfer display data.
successive commands have been issued, command mode omitted. While system operating non-successive command non-successive address data mode, should previous operation mode will reset also. returns "0", operation mode should issued first.
Name
TONE TONE TONE
Command Code
0000-1000-XXXX 010X-XXXX-XXXX 0110-XXXX-XXXX Turn-off tone output
Function
Turn-on tone output, tone frequency 4kHz Turn-on tone output, tone frequency 2kHz
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HT16274
Timing Diagrams
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HT16274
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HT16274
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HT16274
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HT16274
Command Summary
Name
READ WRITE Read-modifywrite TIMER TIMER TONE TIMER (XTAL) TONE TONE
Command Code
Function
Read data from Write data Read Write data Turn system oscillator Turn system oscillator Turn display Turn display Disable time base output Disable time-out flag output Enable time base output Enable time-out flag output Turn tone outputs Clear contents time base generator Clear contents stage System clock source, on-chip oscillator System clock source, external clock source crystal oscillator Tone frequency output: 4kHz Tone frequency output: 2kHz Disable output Enable output Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: 1/2s Time base clock output: 16Hz time-out flag after: 1/4s
Def.
X110 a7a6a5a4a3a2a1a0 d0d1d2d3 X101 a7a6a5a4a3a2a1a0 d0d1d2d3 X101 a7a6a5a4a3a2a1a0 d0d1d2d3 X100 0000-0000-XXXX X100 0000-0001-XXXX X100 0000-0010-XXXX X100 0000-0011-XXXX X100 0000-0100-XXXX X100 0000-0101-XXXX X100 0000-0110-XXXX X100 0000-0111-XXXX X100 0000-1000-XXXX X100 0000-1101-XXXX X100 0000-1111-XXXX X100 0001-10XX-XXXX X100 0001-11XX-XXXX X100 010X-XXXX-XXXX X100 0110-XXXX-XXXX X100 100X-0XXX-XXXX X100 100X-1XXX-XXXX X100 101X-0000-XXXX X100 101X-0001-XXXX X100 101X-0010-XXXX X100 101X-0011-XXXX X100 101X-0100-XXXX
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HT16274
Name
F128 TOPT NORMAL
Command Code
Function
Time base clock output: 32Hz time-out flag after: 1/8s Time base clock output: 64Hz time-out flag after: 1/16s Time base clock output: 128Hz time-out flag after: 1/32s Test mode Normal mode
Def.
X100 101X-0101-XXXX X100 101X-0110-XXXX X100 101X-0111-XXXX X100 1110-0000-XXXX X100 1110-0011-XXXX
Note: Don't care a7~a0: address d3~d0: data D/C: Data/Command mode Def.: Default
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