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Color Linear Image Sensor with 2592 Bits each Colors Overview


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MN3673RE
Color Linear Image Sensor with 2592 Bits each Colors
Overview
MN3673RE 2592-pixel high sensitivity linear image sensor combining photo-sites using dark output floating photodiodes analog shift registers read out. provides large output high ratio visible light inputs over wide range wavelength.
Assignments
2592 (Top View)
Features
7776 (2592 floating photodiodes n-channel buried
type shift registers read integrated single chip.
Since spacing between photodiode lines different colors
small, possible greatly reduce memory compensation between lines. line between R-B, lines between B-G) configuration signal processing circuits such preamplifier, sample hold circuit, etc., becomes simpler since separate signal output pins provided pixels each colors primary colors type on-chip color filters used color separation. dark signal output voltage been suppressed very level photodiodes with structure. (0.2mV (typ.) accumulation time 10ms.) Operation with single +12V positive power supply.
WDIP022-C-0440B
Application
Color graphic read color copying machines,
color scanners, color machines.
Block Diagram
1212
121212121212
121212121
2592 2592
121212121212
1212
121212121
BG24
2592
1212
121212121212
121212121
Black reference pixels each color) Dummy invalid pixels each color)
lines
line
MN3673RE
Absolute Maximum Ratings (Ta=25°C, VSS=0V)
Parameter Power supply voltage Input voltage Output voltage Operating temperature range Storage temperature range Symbol Topr Tstg
Rating
Unit
Operating Conditions Voltage conditions (Ta=-20 60°C, VSS=0V)
Parameter Power supply voltage shift register clock High level shift register clock level Shift gate clock High level Shift gate clock level Reset gate clock High level Reset gate clock level Symbol Condition 11.4 12.0 13.0 Unit
Timing conditions (Ta=-20 60°C)
Parameter Shift register clock frequency Reset clock frequency Shift register clock rise time Shift register clock fall time Shift clock rise time Shift clock fall time Shift clock time Shift clock pulse width Shift clock hold time Reset clock rise time Reset clock fall time Reset clock time Reset clock pulse width Reset clock hold time Symbol timing diagram timing diagram =1/2T timing diagram Condition 0.7T 1000 Unit
Electrical Characteristics Clock input capacitance (Ta=0 60°C)
Parameter Shift register clock input capacitance Shift register final stage clock input capacitance Reset clock input capacitance Shift clock input capacitance Symbol Condition =12V, f=1MHz Unit
characteristics
Parameter Power supply current Symbol +12V Condition Unit
Electrical Characteristics (continued) characteristics
Parameter Signal output delay time Symbol Condition
MN3673RE
Unit
Optical Characteristics
<Inspection conditions> Ta=25°C, VDD=12V, (pulse), fC=fR=1MHz, Tint (accumulation time)=10ms Light source: Daylight type fluorescent lamp with IR/UV cutting filter Optical system: slit with aperture dimensions 20mm 20mm used with slit sensor spacing 200mm (equivalent F=10). Load resistance 100k Ohms These specifications apply 2592 valid pixels each color excluding dummy pixels
Parameter Responsivity Photo response non-uniformity Saturation output voltage Saturation exposure Dark signal output voltage Dark signal output non-uniformity Shift register total transfer efficiency Output impedance Dynamic range Signal output level Signal output level difference Symbol PRNU VSAT VDRK DSNU STTE Note Absolute level OS1, OS2, OS3, Note Relative difference between OS1, OS2, OS3, Note Note Note Note Note Note Dark condition, Note Dark condition, Note Condition 0.69 0.35 0.50 1.20 0.60 0.86 6000 Unit
Note photo response non-uniformity (PRNU) defined following equation, where Xave average output voltage 2592 valid pixels absolute value difference between Xave voltage maximum minimum) output pixel, when surface photo-sites illuminated with light having uniform distribution over entire surface. PRNU= Xave incident light intensity shall standard saturation. Note Saturation output voltage (VSAT) defined output voltage point when linearity photoelectric characteristics cannot maintained incident light intensity increased. (The light intensity exposure this point called saturation exposure.) Note dark signal output voltage (VDRK) defined average output voltage 2592 pixels dark condition Ta=25°C Tint=10ms. Normally, dark output voltage doubles every 10°C rise proportional Tint. dark signal output non-uniformity (DSNU) defined DSNU difference between maximum output voltage among valid pixels VDRK dark condition Ta=25°C Tint=10ms. Note dynamic range defined following equation. VSAT VDRK Since dark signal voltage proportional accumulation time, dynamic range becomes wider when accumulation time shorter. Note signal output level Reset feed compensation output level (VDS) voltage through level values shown following figure. waveform
MN3673RE
Descriptions
Symbol Power supply Ground Reset clock final stage clock (Phase connection connection clock (Phase clock (Phase clock (Phase Ground Shift clock gate clock (Phase clock (Phase clock (Phase connection connection final stage clock (Phase Reset clock Ground name Signal output (Green)
Condition
Internally connected Internally connected
Signal output (Red) Signal output (Blue) Note) Connect pins externally (GND).
Construction Image Sensor
MN3673RE made three sections of-a) photo detector region, transfer region (shift register), output region. Photo detector region photoelectric conversion device consists 11µm floating photodiode channel stopper (isolation region) pixel, such 2592 pixels color arranged linear with pitch 14µm along main scanning direction with pixel rows different colors being placed parallel each other. There spacing line between sideways scanning direction (center center spacing 14µm) line spacing between sideways scanning direction (center center spacing 140µm). photo detector's windows 14µm 14µm squares light incident areas other than these windows optically shut out. photo detector provided with optically shielded pixels (black reference pixels) which serve black reference. Transfer region (shift register) light output that been photoelectrically converted transferred transfer each even pixel timing shift clock optical signal charge transferred this analog shift register successively transferred guided output. buried type that driven phase clock used analog shift register. last gate transfer region connected independent driving this independent other pins clock driver, possible speed flow signal charge into charge voltage conversion region thereby making output waveform rise sharply. This makes easy obtain margin signal processing time during high speed drive operation. Output region signal charge transferred output region first sent charge voltage conversion region where converted into voltage level corresponding amount signal charge, then output after impedance conversion stage source follower amplifier.
Timing Diagram timing
Integration Time (Tint.)
MN3673RE
2626 2622 2624 2621 2623 2625
2623 2625 2627 2622 2624 2626
2591 2592
Blank feed (for pixels)
Black reference pixels (for pixels)
Dummy Valid pixel signal Invalid pixel invalid (for 2592 pixels) signal pixels (for pixels) (for pixels)
Drive timing
Reference level
Effective signal output period
Graphs Characteristics
Spectral Response Characteristics
Relative responsivity Blue Green
Wavelength (nm)

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