Lucent Technologies Microelectronics Group's T7504 T5504 devices monol
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T7504 T5504 Quad Codecs with Filters
Lucent Technologies Microelectronics Group's T7504 T5504 devices monolithic, four-channel codecs with filters. These integrated circuits provide conversion filtering necessary interface voice telephone circuit timedivision multiplexed system using standard interface. digital strobing architecture minimizes pinout, allowing quad codec assembled small 28-pin package that requires minimal board area. Other features include full time-slot assignment, delayed (T7504) nondelayed (T5504) timing mode, pin-selectable µ-law A-law companding, low-power V-only operation, automatic adaptation master clock frequencies either 2.048 4.096 MHz. added flexibility interfacing with transmission systems, each channel also provides uncommitted that programmed transmit gain using external resistors. These devices fabricated Lucent's highperformance analog CMOS technology with doublepoly capacitors. Coding decoding performed using charge redistribution with successive approximation. Gain, termination impedance, hybrid balance external components. These quad codecs ideal high-density circuit-board applications where high integration, crosstalk, minimal cost required.
Digital Interface
digital interfacing device consists interface block, internal timing control block, powerdown control block. Figure functional block diagram this codec.
GSX0 VFXIN0 +2.4 FILTER NETWORK
ENCODER
INTERFACE
CHANNEL
FSX0 FSX1 FSX2 FSX3 FSEP GNDD
VFRO0
FILTER NETWORK
DECODER POWERDOWN CONTROL MCLK ASEL
GSX1 VFXIN1 VFRO1 GSX2 VFXIN2 VFRO2 GSX3 VFXIN3 VFRO3
CHANNEL
INTERNAL TIMING CONTROL
CHANNEL
BIAS CIRCUITRY REFERENCE
GNDA
CHANNEL
5-3579F
Figure Functional Block Diagram
T7504 T5504 Quad Codecs with Filters
Digital Interface (continued)
Interface
interface block administers transmit receive data well frame separation frame sync controlling. Data data occurs once every frame period. frame period standard doubling telephone channel bandwidth 4000 provide minimum sampling rate 8000 samples second (Nyquist criterion). codecs provide fixed data rate timing. Data clocks master clock rate (MCLK). frame period, there data time slots when 2.048 MCLK rate used data time slots when 4.096 MCLK rate used. Each time slot contains eight clock cycles. Data transmitted received serially with first (bit defined last (bit LSB. T7504 provides only half data order ensure contention with subsequent time slot. both codecs, width dependent upon when frame sync goes high. eighth into 3-state port between after eighth MCLK goes low. This could short 2.048 mode (40% duty cycle MCLK ns). sign bit, bits through chord bits, bits through interval bits. data companded µ-law A-law, programmable pin-strap. Some codecs provide mute circuit idle conversations A-law that annoying turns off. Therefore, mute been implemented these codecs. Maximum transmit receive noise levels µ-law A-law specified T7504 T5504 Quad Codecs with Filters Data Sheet. remains high-impedance state when transmitting data. This allows codec operate with single transmit port also allows with other codecs shared bus. Since CMOS nodes, these buses tied known state through pull-up resistor (approximately desired. Data transmitted from codec through received codec through remains inactive until data received. analog loopback, shorted together. using this feature, transmit receive data must aligned. Data alignment time-slot assignment discussed next. Frame Separation Synchronization Most single-channel codecs utilize separate frame sync pulses transmitting receiving data. T7504 T5504 quad codecs require once-per-frame sync pulse (FSx) data transmission frame separation pulse (FSEP) frame synchronization. There
channel, FSEP codec board. FSEP requires more than current drive codec. FSxN FSEP pulses must synchronous with MCLK. Refer Figures following discussion. presence FSEP signifies start frame. FSEP latched negative-going MCLK pulse. subsequent rising MCLK pulse defines start frame byte boundary time slot Data will transmit upon arrival FSx. determines time slot which data will transmitted. With T7504, latched same negativegoing MCLK edge FSEP time slot With regard FSx, byte boundary defined FSEP) occurs first positive-going MCLK edge after detected. must occur byte boundaries; that coincident with FSEP pulse (time slot multiples eight clock cycles thereafter (time slot etc.). Data valid MCLK cycle after detected. This referred delayed timing mode. data latched first negative-going MCLK edge following negative-going edge that latches FSx. With T5504, occurs MCLK cycle after FSEP time slot latched next negative-going MCLK edge after FSEP latched. With regard FSx, byte boundary defined FSEP occurs coincident with rising edge FSx. must occur byte boundaries; that clock cycle after FSEP (time slot multiples eight clock cycles thereafter (time slot etc.). Data valid coincident with FSx. This referred nondelayed timing mode. data latched same negative-going MCLK edge that latches FSx. width FSEP designates when data received. 2.048 MCLK operation, FSEP anywhere from clock cycle clock cycles wide. 4.096 operation, width FSEP will range from clock cycle clock cycles. FSEP widths clock pulses MCLK) clock pulses MCLK) permitted. FSEP must least clock cycle during frame. width FSEP determines delay clock cycles between when data transmitted when data received. This delay applies four channels. number MCLK cycles, minus one, defines delay. instance, Figure FSEP clock cycle long. This sets data receive coincident with data transmit. FSEP were five clock cycles wide, receive data would execute four clock cycles after data transmitted. Like transmit data, receive data latched negative-going MCLK edges. given channel occur only time frame. Unlike FSEP, falling edge relevance; therefore, width critical. digital interface will operate satisfactorily long goes least clock cycle prior going high again. edge triggered must glitch free. Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Digital Interface (continued)
TIME SLOT
MCLK
FSXN (7504)
FSXN (5504) T7504 T5504
FSEP
5-3581sF
Figure Digital Interface Timing
MCLK
MASTER CLOCK REQUIRED OVERALL OPERATION. WITH ONLY MCLK APPLIED, CODEC WILL ASSUME POWERDOWN MODE.
(2.048 MHz) (4.096 MHz)
ALLOWABLE DUTY CYCLE FSEP FRAME SEPARATION DEFINES START FRAME. WIDTH DETERMINES WHEN DATA RECEIVED. WITH MCLK FSEP APPLIED, CODEC ASSUMES STANDBY MODE. ABSENCE FRAMES POWERS DOWN CODEC.
DEFINES START FRAME TIME SLOT NEXT POSITIVE-GOING MCLK PULSE)
5-8870F
WIDTH DETERMINES DELAY MCLK PULSES MINUS UNTIL DATA RECEIVED) ALLOWABLE WIDTH: MCLK 2.048 MHz, 124.5 MCLK MCLKS) MCLK 4.096 MHz, 124.75 MCLK MCLKS)
5-8871F
FSxN (FSx0, FSx1, FSx2, FSx3)
FRAME SYNC ASSIGNS TIME SLOT. REQUIRED PER-CHANNEL OPERATION. WITH MCLK, FSEP, APPLIED, CODEC ASSUMES POWERUP MODE. ONLY NEEDS PRESENT WHEN DATA TRANSMITTED AND/OR RECEIVED. ABSENCE FRAMES POWERS DOWN CHANNEL.
DEFINES START CHANNEL TRANSMIT DATA MUST OCCUR BYTE BOUNDARY (T5504: DATA TRANSMITS IMMEDIATELY) (T7504: DATA TRANSMITS AFTER MCLK CYCLE)
ALLOWABLE WIDTH: MCLK 2.048 MHz, 124.5 MCLK MCLKS) MCLK 4.096 MHz, 124.75 MCLK MCLKS)
5-8872F
Figure User-Supplied Timing Pulses-Definition Relevance Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Digital Interface (continued)
Internal Timing Control
Master Clock T7504 T5504 configured operate MCLK rates 2.048 4.096 MHz. Internal circuitry determines master-clock frequency during powerup reset interval. MCLK used various internal circuits including filters. instance, operating higher than specified MCLK rates will affect device's filter characteristics shifting filter poles higher frequencies. Lower than specified MCLK rates recommended because there will inadequate number pulses perform normal codec operations. MCLK duty cycle should maintained between 60%. A-Law/µ-Law Select ASEL provides pin-strap programmability companding operation. Logic selects µ-law coding, logic high selects alternate inversion Alaw coding. Companding selection changed real time. ASEL monitored every change logic level will change companding state next frame sync pulse. pull-down device included within codec, thereby defaulting part µ-law companding.
When absent FSEP reappears, codec immediately powers back appropriate state without losing frame. VFRO held voltage reference potential during powerdown ensure noise free transmission upon powerup.
Analog Interface
Figure functional block diagram this codec.
Bias Circuit Reference
quad codec requires only supply operate. This eliminates necessity supply bypass capacitor codec use. also eliminates signal reference like codecs that require supplies use. With single supply, analog input output signal reference becomes +2.4 reference. This +2.4 internally generated precision band voltage reference. This voltage reference requires additional external components. single band voltage reference used throughout codec circuitry order provide very accurate gains wide dynamic range. This voltage reference heavily buffered using unity gain amps. reference used input noninverting node transmit uncommitted reference output receive amp. Each channel provided with individually buffered transmit receive voltage references order minimize interchannel intrachannel crosstalk. voltage reference powers down upon absence MCLK.
Powerdown Control
quad codec exhibits three power dissipation modes: powerup, standby, powerdown. Operation standby mode powerdown mode reduces power consumption heat dissipation when device operation required. device full powerup when MCLK, FSEP, pulses present. Under full powerup, codec typically dissipates (worst case 262.5 mW). Absence pulse institutes powerdown that given channel. When absent four frames (500 µs), channel associated with will power down. each channel powers down, each channel reduces overall power dissipation (worst case 52.5 mW). pulses absent, codec will into standby mode where entire part will typically dissipate (worst case 52.5 mW). MCLK present FSEP absent four frames (500 µs), codec will assume powerdown mode. this mode, codec typically dissipates only (worst case 5.25 mW). Powerdown guaranteed MCLK lost. Powerdown achieved removing pulse least with MCLK active, after which MCLK removed.
Transmit Operation (A-D)
transmit path consists input amp, bandpass filtering, encoder.
VFxIN
CODEC FILTERS
5-3786a(F)
GAIN
Figure Typical Analog Input Section Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
resistor input capacitor additional loss provided input network would -0.05 SLIC use, impedance transmit receive coupling capacitors becomes factor effective transhybrid balance. Coupling capacitor values should selected according component selection criteria defined SLIC. output feeds bandpass filter network. Transmit filtering consists antialiasing filter followed fifth-order elliptic low-pass filter third-order high-pass filter. filters switched capacitor filters. high-pass filter effectively attenuates low-frequency noise like ringing signals, typically provides only -0.5 attenuation (see Transmit Filter Characteristics data sheet). passband frequencies adhere ITU-T G.712 requirements. Passband frequencies then encoded quantization. analog signal sampled converted digital representation using charge redistribution with successive approximation. Companding user selectable either A-law µ-law. encoded signal presented interface block. given transmit channel used, VFxIN.
Analog Interface (continued)
quad codec supplies uncommitted channel. schematic input circuit shown Figure Inverting input (VFxIN) output leads (GSx) user accessible. input self-biasing. band voltage reference applied noninverting input. External pull-up resistors required. Passband gain simply dividing amp's feedback resistor (Rf) amp's input resistor (RI). best transmission performance, gain values should range from (gain between 10). Feedback resistance values should range from capacitance from ground should kept less than low-value picofarad capacitor used across feedback resistor increase stability reduce gain injected high-frequency noise. Maintaining these values will minimize crosstalk while still providing acceptable loading GSx. encoder milliwatt defined 0.775 Vrms this part. This convenient value into 0.775 Vrms) referenced +2.4 still allows acceptable headroom maximum signal transmission, which dBm0 (3.145 Vp-p max, A-law; 3.169 Vp-p max, µlaw). minimum transmission signal level determined signal-to-noise ratio. quad codecs measured dBm0 signal levels production test pass ITU-T quantization distortion plus noise specifications. phase inversion analog signal required transhybrid balance considerations, then external must employed. Many SLICs, like Lucent's ATTL7551 ATTL7554 Low-Power SLICs, include spare that used supply necessary phase inversion. VFxIN must capacitively coupled signal source since codec analog inputs referenced internal +2.4 Filtering within codec forms frequency spectrum shaping, input capacitor selection impact low-frequency pole. codec contains fifth-order bandpass filtering. This filtering required order prevent high frequencies from folding over distorting encoding process. Additional low-frequency loss contributed input network calculated using following equation:
Receive Operation (D-A)
decoder converts digital stream analog signal using charge redistribution sample hold capacitors. reconstructed analog signal passes through fifth-order elliptic low-pass filter compliant with ITU-T G.712 Lucent PUB43801 D3/D4 requirements. filtered analog signal provided output amplifier. output amplifier provides single-ended output capable driving load 2000 greater capacitance output signal referenced channel's analog ground. Like analog input, common-mode reference +2.4 Receive gain codec itself fixed unity. decoder milliwatt with input dBm0 0.775 Vrms. Maximum signal level output dBm0 (3.145 Vp-p max, A-law; 3.169 Vp-p max, µ-law). Receive gain attenuated external output simply employing resistive voltage divider. determining proper value capacitive coupling, follow same procedure with transmit coupling capacitor. minimize power dissipation, unused receive outputs float.
loss
Where low-frequency pole interest (e.g., Hz), input resistor input capacitor, respectively (see Figure input Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Board Layout Decoupling
Concentrating four sets analog/digital conversions integrated device places extra burden board layout. Highly sensitive analog nodes noisy digital circuits placed close proximity. high dynamic range codec, which allows noise transmission very small signal levels with minimal crosstalk, could jeopardized proper grounding decoupling practices followed. Furthermore, codec will fail distortion noise requirements proper grounding provided. best performance, multilayer board recommended. inner layer should used common, low-impedance ground plane. perfectly acceptable short SLIC AGND codec GNDA GNDD pins directly inner ground layer. codec's GNDA pins GNDD must tied together chip. individual vias each device ground pin. two-layer board used, low-impedance ground plane must established. micro-island (flooded ground plane) ground traces must used. lowest-impedance ground plane possible, GNDA GNDD leads together chip. Provide dedicated ground plane under device connect these pins together. Fill unused areas around device board with ground. Minimize vias ground planes. ground plane must transfer other layer, multiple vias better connection. Give ground planes routing priority over signal traces. Keep clock traces short guard, possible. serves both analog digital circuits. important place ceramic capacitor both these pins ground. Keep leads short placing vias close solder pads possible. individual vias each power pin. capacitors, each pin. demarcation point analog digital circuitry. Digital circuits grouped together area package. Runners analog digital circuitry should diverge from this point. following this practice could result harmonic frequencies from carrier modulation digital transitions coupling into VFXIN passband frequencies. Digital traces require continuous adjacent return path minimize emissions. Decouple power ground discontinuities. Special consideration required with regard layout analog input leads output leads. Interchannel intrachannel crosstalk into VFxIN significantly affected parasitic capacitance feeds from VFRO. layouts should arranged keep these parasitics low. T7504/T5504 Evaluation Board
used guide correct layout technique. evaluation board achieves interchannel crosstalk values general board layout, other general rules digitally controlled, audio frequency circuits apply. Digital circuitry should placed close edge connector possible. Clock leads should kept short possible. large bulk storage capacitor thereabouts) parallel with ceramics should placed distribution points located near connector.
Specifications
Specifications typical performance characteristics presented data sheet. group delay, envelope delay distortion (Table data sheet), range values given. following discussion allows user determine specific group delay value given conditions.
Group Delay
determine absolute round trip delay FSEP MCLK pulse wide, following formula Table DRTA 1600 where: DRTA absolute round trip delay microseconds. delay internal filter circuitry (times round trip) microseconds. transmit channels constant 327. transmit channels constant 392. digital delay transmit path microseconds. Obtain appropriate value given transmit channel time slot from Table digital delay receive path microseconds. Obtain appropriate value given receive channel time slot from Table absolute round trip delays single channel single time-slot assignment with FSEP MCLK pulse wide, MCLK 2.048 MHz, delays will calculate follows: Channels Channels Time Slots 0-3, 16-31 Time Slots 4-15 Time Slots 0-19 Time Slots 20-31
Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Specifications (continued)
Table Digital Delay Periods Time Slot: MCLK 2.048 4.096 (Transmit Digital Delay) 62.5 101.5 105.5 15.5 19.5 58.5 (Receive Digital Delay) 15.5 101.5 97.5 62.5 58.5 19.5 Time Slot: MCLK 2.048 4.096 (Transmit Digital Delay) 15.5 19.5 58.5 62.5 101.5 (Receive Digital Delay) 62.5 58.5 19.5 15.5 101.5
Channel
Channel
Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Applications
Time-Slot Enable Strobe
Some codecs provide time-slot enable strobe. This strobe useful enabling external 3-state buffers that could required drive heavily loaded lines. This strobe provides active-low pulse that envelops 8-bit transmit time slot. quad codec does provide time-slot enable output. time-slot enable pulse derived, however, from T5504 frame sync pulse. T5504 operates nondelayed timing mode. rising edge frame sync envelops first
time slot. Frame sync pulses anywhere from clock pulse wide clock pulses wide (2.048 4.096 operation, respectively). generate time-slot enable pulse, frame sync pulse should eight clock pulses wide. Inverting frame sync pulse generates 8-bit wide active-low pulse that used time slot enable (see Figure Please note that codec operation, FSEP pulse still needs supplied. T5504, FSEP occurs clock pulse prior timeslot byte boundary. create time-slot enable T7504, insert Dtype flip-flop clocked MCLK node Figure
MCLK
FSxN
DERIVED TIME-SLOT ENABLE STROBE
5-4713F
T5504
BUFFERED FROM OTHER CODECS 745125A FSx0 FSx1 FSx2 FSx3 FSEP 74S260
INTERFACE
INTERNAL TIMING CONTROL
MCLK
5-4714
Figure Time-Slot Enable Strobe Timing Diagram Circuit
Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
complete, channel must kept active until other channel longer use. width FSx0 determines what time slot data received. data will transmitted delayed timing mode.
Applications (continued)
Codec Without FSEP Pulse
T7504 codec used without using separate frame separation (FSEP) pulse. Operating this fashion, however, places restraints operation complicates digital interface requiring more intelligent control. operation, FSEP FSx0 FSx0 will function FSEP pulse. (Any other channel selected; this discussion, channel chosen.) FSx0 must occur every time slot will therefore become first channel last channel this codec. codec idle, lack FSx0 will power down codec. When data transmitted FSx0 reappears, channel will power time slot will become active while other three channels will into standby power mode. Other channels time slots become active their respective pulses transmitted. there activity another channel after transmission chanL8560
SLIC Interface
Interfacing codec SLIC discussed detail application materials relating SLIC. basic interface circuit resistive termination hybrid balance, with gains shown Figure transmit gain codec. value RHB1 needs appropriately selected according loop gains hybrid balance. RRCV (with parallel) provide attenuation codec receive signal. (with RRCV parallel) sets termination impedance. provide blocking codec reference level signal coupling. RGP2 added SLIC stability.
48.7
T7504
VITR
VFXIN
+2.4
RHB1
RCVN RCVP
RRCV
VFRO
48.7
RGP2 1.78
5-4716F
Figure SLIC Interface (600 Resistive)
Lucent Technologies Inc.
T7504 T5504 Quad Codecs with Filters
Applications (continued)
Speaker Driver
T7504/T5504 quad codecs have single-ended analog inputs outputs. analog output drive minimum 2000 T7502 T7503 dual codecs have differential analog inputs outputs. differential output these devices drive minimum (600 single ended). T7502 T7503 preferred choice direct connection microphones transformer drive applications.
readily interface T7504/T5504 speaker, however, using generic dual resistors capacitors. Figure shows T7504 interfacing small speaker. LM358 equivalent) unity gain push-pull drive. output codec capacitively coupled amps with large value capacitor suitable audio frequencies. This capacitor removes output's content. Another midpoint reference level provided amps R1/R2 voltage divider.
T7504
LM358 SMALL EFFICIENT SPEAKER
VFRO0
GNDA0
5-4715F
Figure Speaker Driver Circuit
additional information, contact your Microelectronics Group Account Manager following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1999 Lucent Technologies Inc. Rights Reserved
November 1999 AP00-004ALC (Replaces AP96-026ALC)
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