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DABiC-5 8-Bit Serial Input Latched Sink Drivers merged combinatio
Top Searches for this datasheetA6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers merged combination bipolar technology gives these devices interface flexibility beyond reach standard logic buffers power driver arrays. Typical applications include driving multiplexed displays incandescent lamps. A6821 eight-bit CMOS shift register CMOS control circuitry, eight CMOS data latches, eight bipolar current-sinking Darlington output drivers. CMOS inputs compatible with standard CMOS logic levels. circuits require appropriate pull-up resistors. using serial data output, drivers cascaded interface applications requiring additional drive lines. Package 16-pin Wide Body SOIC A6821SA furnished standard 16-pin plastic DIP. A6821EA 16-pin plastic DIP, capable operation from -40°C +85°C. A6821SLW 16-lead wide-body SOIC, surfacemount applications. These devices lead (Pb) free, with 100% matte plated leadframes. Data Sheet 26185.112 Package 16-pin FEATURES logic supply range Automotive capable Low-power CMOS logic latches High-voltage current-sink outputs Internal pull-up/pull down resistors ABSOLUTE MAXIMUM RATINGS Output Voltage, VOUT Logic Supply Voltage, VDD.7 Input Voltage Range, .-0.3 +0.3 Continuous Output Current (each output), IOUT Package Power Dissipation, A6821SA/A6821EA.2.1 A6821SLW. Operating Temperature Range Ambient Temperature, .-20°C +85°C Storage Temperature, .-55°C +150°C Caution: CMOS devices have input-static protection, susceptible damage when exposed extremely high static-electrical charges. Power reset (POR) data input rate CMOS, compatible APPLICATIONS Multiplexed displays Incandescent lamps following complete part numbers when ordering: Part Number A6821SA-T A6821EA-T A6821SLW-T Package 16-pin 16-pin 16-pin wide body SOIC Ambient Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers Functional Block Diagram A6821 OUND LOW) OLAR OUND IAL-P ALLE Typical Input Circuits Typical Output Driver STROBE OUTPUT ENABLE CLOCK SERIAL DATA www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: 25°C, logic supply operating voltage Characteristic Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Input Resistance Serial Data Output Voltage Maximum Clock Frequency2 Logic Supply Current A6821 Typ. 4.75 0.15 Symbol ICEX VCE(SAT) VIN(1) VIN(0) VOUT(1) VOUT(0) IDD(1) IDD(0) tdis(BQ) ten(BQ) tp(STH-QL) tp(STH-QH) tp(CH-SQX) Test Conditions VOUT IOUT IOUT IOUT Min. Typ. 3.05 0.15 Max. Min. Max. Units IOUT -200 IOUT output outputs off, through IOUT ±200 Output Enable-to-Output Delay Strobe-to-Output Delay Output Fall Time Output Rise Time Clock-to-Serial Data Delay 1Positive (negative) current defined conventional current going into (coming specified device pin. 2Operation clock frequency greater than specified minimum value possible warranteed. Truth Table Serial Data Clock Input Input Shift Register Contents Serial Data Output Logic Level High Logic Level Irrelevant Present State Previous State Output Enable Strobe Latch Contents Strobe Input Output Enable Input Output Contents www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers Timing Requirements Specifications (Logic Levels Ground) CLOCK SERIAL DATA DATA A6821 p(CH-SQX) SERIAL DATA STROBE DATA OUTPUT ENABLE OUTP NABLE tp(STH-QH) tp(STH-QL) DATA HIGH OUTP BLANKE (DIS ABLE OUTPUT ENABLE en(BQ) dis(BQ) DATA Description Data Active Time Before Clock Pulse (Data Set-Up Time) Data Active Time After Clock Pulse (Data Hold Time) Clock Pulse Width Time Between Clock Activation Strobe Strobe Pulse Width Symbol tsu(D) th(D) tw(CH) tsu(C) tw(STH) Time (ns) NOTE: Timing representative clock. Higher speeds attainable; operation high temperatures will reduce specified maximum clock frequency. Powering-on with inputs state ensures that registers latches power-on state (POR). Serial Data present input transferred shift register logical logical transition CLOCK input pulse. succeeding CLOCK pulses, registers shift data information towards SERIAL DATA OUTPUT. SERIAL DATA must appear input prior rising edge CLOCK input waveform. Information present register transferred respective latch when STROBE high (serial-to-parallel conversion). latches will continue accept data long STROBE held high. Applications where latches bypassed (STROBE tied high) will require that OUTPUT ENABLE input high during serial data entry. When OUTPUT ENABLE input high, output buffers disabled (OFF). information stored latches shift register affected OUTPUT ENABLE input. With OUTPUT ENABLE input low, outputs controlled state their respective latches. www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers Maximum Allowable Duty Cycle, IOUT Number Outputs A6821SA/A6821EA A6821 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% mbient emperature 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% A6821SLW Terminal List Table Name Description Clock Serial Data Logic Ground* OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Logic Supply Serial Data Strobe Output Enable (active low) Power Ground* Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output There indeterminate resistance between logic ground power ground. proper operation, these terminals must externally connected together. www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers A6821 Package 16-pin Package 16-pin Wide Body SOIC CLOCK SERIAL DATA LOGIC GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE POWER GROUND OUND OUND SHIFT REGISTER LATCHES www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package 16-pin Dimensions Inches (controlling dimensions) 0.014 0.008 A6821 0.430 0.280 0.240 0.300 0.070 0.045 0.100 0.775 0.735 0.005 0.210 0.015 0.150 0.115 0.022 0.014 Dwg. MA-001-16A Dimensions Millimeters (for reference only) 0.355 0.204 10.92 7.11 6.10 7.62 1.77 1.15 2.54 19.68 18.67 0.13 5.33 0.39 3.81 2.93 0.558 0.356 Dwg. MA-001-16A NOTES: Lead thickness measured seating plane below. Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown. www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers 16-pin Wide Body SOIC Dimensions Inches (for reference only) 0.0125 0.0091 A6821 Package 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 0.4133 0.3977 0.050 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-16A Dimensions Millimeters (controlling dimensions) 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 10.50 10.10 1.27 2.65 2.35 0.10 MIN. Dwg. MA-008-16A NOTES: Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown. www.allegromicro.com Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Data Sheet 26185.112 DABiC-5 8-Bit Serial Input Latched Sink Drivers A6821 products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro products authorized critical components life-support devices systems without express written approval. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use. 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