W986432DH high-speed synchronous dynamic random access memory (SDRAM),
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PRELIMINARY W986432DH 512K BANKS BITS SDRAM
W986432DH high-speed synchronous dynamic random access memory (SDRAM), organized 512K words banks bits. Using pipelined architecture 0.175 process technology, W986432DH delivers data bandwidth 800M bytes second (5). different application, W986432DH sorted into four speed grades: -55, -7,-8. Accesses SDRAM burst oriented. Consecutive memory location page accessed burst length full page when bank selected ACTIVE command. Column addresses automatically generated SDRAM internal counter burst operation. Random column read also possible providing address each clock cycle. multiple bank nature enables interleaving among internal banks hide precharging time. having programmable Mode Register, system change burst length, latency cycle, interleave sequential burst maximize performance. W986432DH ideal main memory high performance applications.
3.3V ±0.3V power supply 524288 words banks bits organization Auto Refresh Self Refresh latency: Burst Length: full page Sequential Interleave burst Burst read, single write operation Byte data controlled Power-down Mode Auto-precharge controlled precharge refresh cycles/64 Interface: LVTTL Packaged 86-pin TSOP 0.50
Publication Release Date: 2000 Revision
PRELIMINARY W986432DH 512K BANKS BITS SDRAM
CONFIGURATION
DQM1 DQM3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ VSSQ VSSQ
A10/AP
VSSQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQM0
DQM2
VCCQ
VCCQ
DQ22
VCCQ
DESCRIPTION
NAME A0-A10 FUNCTION Address DESCRIPTION Multiplexed pins column address. address: A0-A10. Column address: A0-A7. sampled during precharge command determine banks precharged bank selected BS0, BS1. BS0, DQ0-DQ31
Bank Select Data Input/ Output Chip Select
Select bank activate during address latch time, bank read/write during address latch time. Multiplexed pins data output input. Disable enable command decoder. When command decoder disabled, command ignored previous operation continues. Command input. When sampled rising edge clock define operation executed. Referred Referred
Address Strobe Column Address Strobe Write Enable
Publication Release Date: 2000 Revision
VCCQ
W986432DH
DQM0- DQM3 Input/output mask output buffer placed Hi-Z (with latency when sampled high read cycle. write cycle, sampling high will block write operation with zero latency. Clock Inputs Clock Enable System clock used sample inputs rising edge clock. controls clock activation deactivation. When low, Power Down mode, Suspend mode, Self Refresh mode entered. Power input buffers logic circuit inside DRAM. Ground input buffers logic circuit inside DRAM.
VCCQ VSSQ
Power (+3.3V) Ground
Power (+3.3V) Separated power from VCC, improve noise immunity. buffer Ground buffer Connection Separated ground from VSS, improve noise immunity. connection
Publication Release Date: 2000 Revision
W986432DH
BLOCK DIAGRAM
CLOCK BUFFER
CONTROL
SIGNAL
GENERATOR
COMMAND
DECODER DECODER COLUMN DECODER COLUMN DECODER DECODER
CELL ARRAY BANK
CELL ARRAY BANK
ADDRESS BUFFER
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DATA CONTROL CIRCUIT COLUMN COUNTER
BUFFER
DQ31
REFRESH COUNTER
DQM0~3
COLUMN DECODER DECODER DECODER
COLUMN DECODER
CELL ARRAY BANK
CELL ARRAY BANK
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: cell array configuration 2048
W986432DH
CHARACTERISTICS
Absolute Maximum Rating
PARAMETER Input, Column Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYM. VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER IOUT RATING -0.3 +0.3 -0.3 UNIT NOTES
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
RECOMMENDED OPERATING CONDITIONS
70°C)
PARAMETER Power Supply Voltage Power Supply Voltage (for Buffer) Input High Voltage Input Voltage
SYM. VCCQ
MIN. -0.3
TYP.
MAX. +0.3
UNIT
NOTE
Note: (max.) VCC/VCCQ+1.2V pulse width (min.) VSS/VSSQ-1.2V pulse width
CAPACITANCE
(VDD 3.3V, MHz)
PARAMETER Input Capacitance A11, BS0, BS1,
SYM.
MIN.
MAX.
UNIT
DQM, CKE) CCLK
Input Capacitance (CLK) Input/Output capacitance (DQ0-DQ31)
Note: These parameters periodically sampled 100% tested
Publication Release Date: 2000 Revision
W986432DH
CHARACTERISTICS
(VCC 3.3V ±0.3V, 0°~70°C) PARAMETER SYM. MAX. Operating Current min., min. Active precharge command cycling without burst operation Standby Current min., VIH/L (min.)/VIL (max.) Bank: inactive state (Power Down mode) ICC2P ICC2 bank operation ICC1 MAX. MAX. MAX. MAX. UNIT NOTES
Standby Current VIL, VIH/L=VIH (min.)/VIL (max.) BANK: inactive state
ICC2S
(Power Down mode)
ICC2P
Operating Current min., (min.) BANK: active state banks)
ICC3
(Power Down mode) (tCK min.)
ICC3P
Burst Operating Current Read/Write command cycling Auto Refresh Current Auto refresh command cycling Self Refresh Current Self refresh mode
ICC4
(tCK min.)
ICC5
(CKE 0.2V)
ICC6
PARAMETER Input Leakage Current VCC, other pins under test Output Leakage Current 7(Output disable, VOUT VCCQ) LVTTL Output Level Voltage (IOUT LVTTL Output Level Voltage (IOUT
SYMBOL II(L)
MIN.
MAX.
UNIT
NOTES
VO(L)
W986432DH
CHARACTERISTICS
(VCC 3.3V 0.3V, (Notes: PARAMETER Symbol Ref/Active Ref/Active Command Period Active precharge Command Period tRAS Active Read/Write Command Delay Time tRCD Read/Write(a) Read/Write(b)Command tCCD Period Precharge Active(b) Command Period Active(a) Active(b) Command Period Write Recovery Time Cycle Time High Level Level Access Time from Output Data Hold Time Output Data High Impedance Time Output Data Impedance Time Power Down Mode Entry Time Transition Time (Rise Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time Set-up Time Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Cycle Time tCKS tCKH tCMS tCMH tREF tRSC 2.75 2.75 10.8 tRRD 2.75 2.75 1000 1000 100000 10.8 2.75 2.75 1000 1000 100000 1000 1000 Cycle 100000 UNIT NOTE
Publication Release Date: 2000 Revision
W986432DH
CHARACTERISTICS
(VCC 3.3V 0.3V, (Notes: PARAMETER Ref/Active Ref/Active Command Period Active precharge Command Period Read/Write(a) Read/Write(b)Command Period Precharge Active(b) Command Period Active(a) Active(b) Command Period Write Recovery Time Cycle Time High Level Level Access Time from Output Data Hold Time Output Data High Impedance Time Output Data Impedance Time Power Down Mode Entry Time Transition Time (Rise Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time Set-up Time Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Cycle Time tCKS tCKH tCMS tCMH tREF tRSC Symbol tRAS tCCD tRRD 1000 1000 100000 1000 1000 Cycle 100000 UNIT NOTE
Active Read/Write Command Delay Time tRCD
W986432DH
PACKAGE DIMENSIONS
TSOP (II)-400
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION (MM)
SYM.
DIMENSION (INCH) MAX.
1.20 0.15
MIN.
0.40 0.05
NOM.
MIN.
0.002
NOM.
MAX.
0.047 0.006
1.00 0.17 0.12 22.12 10.06 11.56 22.22 10.16 11.76 0.50 0.50 0.80 0.10 0.61 0.60 0.016 0.27 0.21 22.62 10.26 11.96 0.007 0.005 0.871 0.396 0.455
0.039 0.011 0.008 0.875 0.400 0.463 0.020 0.020 0.032 0.004 0.024 0.024 0.905 0.404 0.471
Publication Release Date: 2000 Revision
W986432DH
Headquarters
Winbond Electronics (H.K.) Ltd.
803, World Trade Square, Tower Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change without notice.
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