W89C926 PENTIC+ CMOS device designed easy implementation PCMCIA R2.1 c

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W89C926 PENTIC+ CMOS device designed easy implementation PCMCIA R2.1 c

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Preliminary W89C926 PENTIC+ PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
W89C926 PENTIC+ CMOS device designed easy implementation PCMCIA R2.1 compatible CSMA/CD local area networks. W89C926 combines W89C902 Serial Coprocessor Twisted-pair (SLCT) with PCMCIA Interface (PBI), thus integrating into single chip registers logic necessary connect SLCT buffer SRAMs, flash memories EEPROM), PCMCIA system bus. PCMCIA Interface (PBI) designed provide switchless setting architecture that allows card setting configured software. implements full PCMCIA registers PCMCIA R2.1 compatibility configuration registers switchless card setting. card configured quickly easily modifying contents configuration registers. PENTIC+ with shared memory mode NE2000I/O mode drivers 16-bit interface. extra effort needed ensure software compatibility. PENTIC+ provides flexible flash memory KB)/EEPROM bytes) architecture PCMCIA nonvolatile storage ID/Configuration auto-load architecture power-on initialization. Vendors store Ethernet configuration, flash memory EEPROM. PENTIC+ will auto-load necessary information when power switched
Runs with NE2000 shared memory drivers Supports flash memory (8K/112K attribute/common memory) bytes EEPROM (for attribute memory only) nonvolatile memory Uses SRAM SRAM EEPROM used) Ethernet ring buffer Auto-load algorithm provided power-on initialization Supports necessary PCMCIA registers Configuration registers allow switchless card setting UTP/BNC auto media-switching function provided Drives necessary LEDs network status display Single power supply with power consumption 100-pin thin package (TQFP) fits into PCMCIA Type profile
Ethernet registered trademark Xerox Corporation. NE2000is trademark Novell, Inc.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
CONFIGURATION
MSA9 MSA8 MSA13 MSWR MSD2 MSD1 MSD0 MSA0 MSA1 MSA2 MSA3 MSA4 MSA5 MSA6 MSA7 MSA12 MSA14 IOS16
HD11 HD12 HD13 HD14 HD15 HA10 HA11 IORD IOWR
W89C926 PENTIC+
DESCRIPTION
NAME NUMBER TYPE DESCRIPTION PCMCIA Interface HA0-2 HA3, HA5-7 HA8-10 HA11-13 HA14-16 HD0-2 HD3-5 HD6-8 HD9-11 HD12-15 IREQ 20-22 23,29 O/TTL Interrupt Request: IREQ asserted PENTIC+ request host service. During auto-loading, which caused reset, IREQ will assert until auto-loading complete. This signaling used Rdy/-Bsy Memory Only Interface during initialization, according PCMCIA R2.1. Read: IORD asserted system read data from card's space. internal 100K pull-high resistor. IOWR I/TTL Write: IOWR asserted system write data card's space. internal 100K pull-high resistor. I/TTL Write Enable: input asserted system strobe memory write data into card memory. internal 100K pull-high resistor. IO/3SH Host Data Bus: Bidirectional host data bus. I/TTL Host Address Bus: Host address lines used decode access card's memory spaces.
IORD
I/TTL
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Description, continued
NAME
NUMBER
TYPE I/TTL Output Enable:
DESCRIPTION
line asserted system obtain memory read data from card memory. internal 100K pull-high resistor.
I/TTL
Card Enable:
asserted system data width control shown below. These pins have internal 100K pull-high resistor.
I/TTL
HD15-HD8 Valid Valid High-Z High-Z
HD7-HD0 Valid High-Z Valid High-Z
Register selection: asserted system access attribute memory space. remains high inactive common memory accesses. internal 100K pull-high resistor.
IOIS16
O/TTL
16-bit access: Asserted PENTIC+ inform system that current operation 16-bit access.
INPACK
O/TTL
Input Acknowledge: Asserted PENTIC+ when been selected respond read cycle.
WAIT
O/TTL
Wait State: Asserted PENTIC+ insert wait states into current memory access cycles.
RESET
I/TTL
Card Reset: RESET pulse will initiate PENTIC+'s initialization procedure, including auto-ID/configuration loading, register initialization, state machine initialization. pulse width should least recognized valid reset. This internal 100K pull-up resistor.
W89C926 PENTIC+
Description, continued
NAME
NUMBER
TYPE
DESCRIPTION
Memory Support Interface MSA0-7 MSA8-10 MSA11-13 MSA14-16 MSD0-2 MSD3-7 90-97 89-87 71-75 I/O/3SH IO/3SH Memory Support Data Bus: Bidirectional on-board memory data bus. EEPROM Interface: During EEPROM auto-load read/write sequence, MSD0 used serial data input/output from/to EEPROM, MSD1 outputs EEPROM commands EEPROM, MSD2 sends clock with period microseconds. This function available only when EECS/ during reset. O/TTL SRAM Chip Select:
asserted PENTIC+ SRAM chip enable during buffer memory access.
O/TTL
Memory Support Address: Latched address used decode accesses onboard memory.
EECS/
O/3SH
Nonvolatile Memory Chip Select: EECS/ asserted PENTIC+ chip enable during nonvolatile memory access. active flash memory enable active high EEPROM chip enable.
I/3SH
Nonvolatile Memory Detection: During reset, PENTIC+ will determine existing nonvolatile memory type sampling voltage level this pin. this externally pulled high with 470K resistor, PENTIC+ will determine that memory flash memory; pulled with 470K resistor, will determine that memory EEPROM.
MSRD
O/TTL
Memory Support Read:
MSRD asserted PENTIC+ strobe read data from on-board memory. Both SRAM flash memory MSRD read command strobe.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Description, continued
NAME MSWR
NUMBER
TYPE O/TTL
DESCRIPTION Memory Support Write: MSWR asserted PENTIC+ strobe write data into on-board memory. Both SRAM flash memory MSWR write command strobe.
Network Interface TXO+, O/DIF Twisted Pair Transmit Outputs: differential output pair. 1.21 precision resistor should shunted across these pins signal preequalization. Twisted Pair Receive Inputs: These inputs into differential amplifier which passes valid data core. precision resistor should shunted across these pins impedance matching. Transmit Outputs: Differential transmit outputs. These pins should connected external pull-down resistors. Receive Inputs: Differential receive input pair from interface. Collision Inputs: Differential collision input pair from interface. Crystal Input: Master clock input. Crystal Feedback Output: This should connected crystal when crystal used should left unconnected when oscillator used. Thin Cable Select: This high when PENTIC+ configured thin cable media. used switch DC-DC converter network media selection. Activity: This output asserts approximately whenever PENTIC+ transmits receives data without collisions. This output also controlled power-down state machine; refer descriptions registers more details.
RXI+,
I/DIF
TX+,
O/DIF
RX+, CD+,
I/DIF I/DIF I/XTAL O/XTAL
THIN
O/TTL
ACTLED
O/TTL
W89C926 PENTIC+
Description, continued
NAME GDLNK
NUMBER
TYPE O/TTL GoodLink:
DESCRIPTION This output asserts PENTIC+ mode, link checking enabled, link integrity good link checking disabled; otherwise, asserted. This output also controlled power down state machine; refer description registers more details.
Power Pins AVCC Analog Power Supply Pins: These pins supply PENTIC+'s analog circuitry network interface. Analog layout rules decoupling methods must applied between this AGND. AGND Analog Ground Pins: These pins ground analog circuitry. Digital Power Supply Pins: These pins supply PENTIC+'s digital circuitry. Digital Ground Pins: These pins ground digital circuitry.
Note: input pin; output pin; bidirectional input/output pin; TTL: level buffer stage; ODH: open drain buffer stage; MOS: level buffer stage; 3SH: Tri-state buffer stage; DIF: differential buffer stage, XTAL: crystal.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
BLOCK DIAGRAM
Registers
EEPROM Control
Flash Memory Control
Buffer Memory Control
W89C902 Core
Local
Config. Registers Control
Interrupt Control
Local Arbiter
PCMCIA Interface Logic Drivers
HA0-16
HD0-15
PCMCIA slot
W89C926 PENTIC+
SYSTEM DIAGRAM
SRAM 32KB (EECS/FCS pull low) OSC/XTAL
MSD0-7 EEPROM 93C56/66 (EECS/FCS pull low) MSA0-16 W89C926
TP/IF LEDs W89C92 optional
FLASH 128KB (EECS/FCS pull high) PCMCIA slot HA0-16 HD0-15
combinations used hardware structure: Combination EECS/FCS pull high/128 flash memory/16 SRAM Combination EECS/FCS pull low/256 512B EEPROM/32 SRAM
FUNCTIONAL DESCRIPTION
ADDRESS MAPPING
EEPROM MAPPING EEPROM ADDRESS 06H-08H 0AH-nH (n+1) H-FFH HIGH BYTE ID-1 ID-3 ID-5 Check BYTE Word Count ID-0 ID-2 ID-4 Board Type (05H)
Notes: fifth (05H) word used shared memory mode ninth (09H) word used NE2000 mode. Word Count should zero value, zero value will cause unpredicted error).
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
ATTRIBUTE MEMORY MAPPING EECS/FCS Pull High (Flash Memory) ATTRIBUTE MEMORY OFFSET (HA0-16) 00000H 00F9EH 00FA0H 00FA2H 00FA4H 00FA6H 00FA8H 00FAAH 00FACH 00FAEH 00FB0H 00FB2H 00FB4H 00FB6H 00FB8H 00FBAH 00FBCH 00FBEH 00FC0H 00FC2H 00FD0H 00FD2H 00FD4H 00FD6H 00FF0H 00FF2H 00FF4H 00FF6H 00FFEH 01000H 03FFEH Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Register Register Register Register Register Register Register Register Register Flash ID-0 ID-1 ID-2 ID-3 ID-4 ID-5 Board Type (05H) Check CCSR Reserved (see note) Reserved TYPE CONTENTS
W89C926 PENTIC+
EECS/FCS Pull (EEPROM) ATTRIBUTE MEMORY OFFSET (HA0-16) 00000H 003D6H 00FD0H 00FD2H 00FD4H 00FD6H 00FF0H 00FF2H 00FF4H 00FF6H 00FFEH 01000H 03FFEH TYPE Memory (SRAM) Unsued Register Register Register Register Register Register Register Register Register Unused CONTENTS CCSR Reserved (see note) Reserved
Notes: 1.The reserved register space attribute space left future extension. Users should place their application this area. When EECS/ pulled high, address 00FA0H 00FFEH used Ethernet configuration, registers. Vendors should this region. When EECS/ pulled low, Address 00000H 003D6H read-only. PENTIC+ will ignore write accesses this area.
NE2000 Mode Mapping
Mapping SYSTEM OFFSET (HA0-4) NAME Core Registers Remote Port Reset Port OPERATION Register Read/Write Remote Read/Write Software Reset
Notes: PENTIC+ decodes only HA0-4 access, IOBase address left host adapter socket service determine. issue reset, simply issue read Reset Port. PENTIC+ will assert internal reset pulse reset core state machine. host tries access PENTIC+, WAIT will asserted until reset completed.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Buffer Memory Mapping CORE MEMORY 0000H 001FH 0020H 00FFH 0100H 3FFFH 4000H 7FFFH 8000H BFFFH C000H FFFFH Nonvolatile Memory Mapping (flash memory used) SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 1FFFFH Attribute/ Flash Common/ Flash (112K CIS/ID/PCMCIA Register MEMORY TYPE NAME NE2000 COMPATIBLE Registers Aliased Registers Buffer SRAM (16K Aliased Registers Aliased Buffer SRAM
(EEPROM used) SYSTEM OFFSET (HA0-16) 00000H 003D6H Attribute/ (Note) (492 MEMORY TYPE NAME
Notes: This attribute memory image from EEPROM. actually resident upper half SRAM after power-on autoloading. Refer "Attribute Memory Mapping" detailed locations. PENTIC+ decodes HA0-16 memory access. (common attribute) MEMBase addresses left host adapter socket service determine.
W89C926 PENTIC+
Shared Memory Mode Mapping
Mapping SYSTEM OFFSET (HA0-4)
Notes: PENTIC+ decodes only HA0-4 access, IOBase address left host adapter socket service determine. used shared memory mapping control. Since PENTIC+ decodes only 0000H 03FFFH shared memory that shared memory base address PENTIC+ 00000H, should Since PENTIC+ supports 16-bit mode only, Word/-Byte will read 01H.
NAME Word/-Byte Registers Core Registers
OPERATION Write Read Write Read Register Read/Write
Buffer Memory Mapping SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 07FFFH
Notes: This region occupied flash memory. PENTIC+ decodes HA0-16 memory access. (common attribute) MEMBase addresses left host adapter socket service determine.
MEMORY TYPE Common/SRAM Common/(Note)
SHARED MEMORY MODE Buffer SRAM (16K Unused
Nonvolatile Memory Mapping (flash memory used) SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 1FFFFH Attribute/ Flash Common/ Flash CIS/ID/PCMCIA Register (112K MEMORY TYPE NAME
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
(EEPROM used) SYSTEM OFFSET (HA0-16) 00000H 003D6H
Notes: This attribute memory image from EEPROM. physically resident upper half SRAM after power-on autoloading. Refer "Attribute Memory Mapping" detailed locations. PENTIC+ decodes HA0-16 memory access. (common attribute) MEMBase addresses left host adapter socket service determine.
MEMORY TYPE Attribute/ (Note)
NAME (492x
REGISTER FILE
W89C926 PENTIC+ four register sets: core register set, PCMCIA configuration register set, configuration register set, special control register set. core register same that W89C90 will discussed here. other three register sets described below.
PCMCIA Configuration Register
PENTIC+ provides three PCMCIA configuration registers needed ensure compatibility with various operating systems. (Configuration Option Register) Access Address: AMBase 00FD0H Access Type: Attribute Memory Read/Write SYMBOL IDX0-5 DESCRIPTION Configuration Index These bits used indicate entry card configuration table located (Card Information Structure; refer PCMCIA R2.1). These bits power-on. Reserved, must (level mode interrupt) when read. Reset software reset issued when written this bit. This same reset except that this necessary information (CFA, CFB, CIS, Ethernet cleared, auto-load procedure performed. Returning this will leave PENTIC+ post-reset state same that following hardware reset. value this power-on
SRESET
W89C926 PENTIC+
CCSR (Card Configuration Status Register) Access Address: AMBase 00FD2H Access Type: Attribute Memory Read/Write SYMBOL Intr DESCRIPTION Reserved, must Interrupt Status This indicates internal status interrupt request. remains high until condition that caused interrupt request been serviced. This power-on. Reserved, must
(Socket Copy Register) used enable PENTIC+ distinguish between similar cards installed same system. Access Address: AMBase 00FD6H Access Type: Attribute Memory Read/Write SYMBOL SocNum Socket Number these bits indicate PENTIC+ that located n'th socket. first socket numbered This permits cards designed share common ports while remaining uniquely identifiable. These bits power-on. CopNum Copy Number these bits indicate PENTIC+ that n'th copy another card installed system that configured identically. first identical card should assigned value copy number. This permits cards designed share common ports while remaining uniquely identifiable consecutively ordered. These bits power-on. Reserved, must DESCRIPTION
Configuration Register
These registers used configuration control. (Configuration Register This register used select PENTIC+'s operating mode control. Access Address: AMBase 00FF0H Access Type: Attribute Memory Read/Write
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
SYMBOL M/-IO DESCRIPTION Share Memory/IO Mode Select PENTIC+ will operate shared memory mode this high; otherwise, will mode. Reserved, must Flash EEPROM Select. This directly reflects sampled value EECS/FCS during reset. This will high EECS/FCS pulled high low. This read-only. Disable. Setting this high disables indicators order save power.
(Configuration Register Access Address: AMBase 00FF2H Access Type: Attribute Memory Read/Write SYMBOL PHY01 DESCRIPTION Physical Media Select These bits determine which type medium PENTIC+ attached. THIN will output 10BASE5 mode high 10BASE2 mode, according PHY0,1. This used control DC-DC converter electrical isolation. PHY1 PHY0 Attached Medium Type (10BASE-T Compatible Squelch Level) Thin Ethernet (10BASE2) Thick Ethernet (10BASE5) (Reduced Squelch Level)
PENTIC+ also provides UTP/BNC auto media-switching function. physical interface will jump from when PENTIC+ configured UTP, link checking enabled, path broken. will jump back immediately path been reconnected. When physical interface configured link checking disabled, auto media-switching function will disabled.
W89C926 PENTIC+
(Configuration Register continued
SYMBOL LNKEN
LNKSTS
IO16CON
DESCRIPTION Link Enable Writing this will disable link pulse generation, auto mediaswitching function, link integrity check function. Writing this will enable these functions. Link Status This indicates present link status. high PENTIC+ mode, link checking enabled, link integrity good link checking disabled; otherwise, low. IOIS16 Timing Control. this high, IOIS16 signal will decode CE1,2 otherwise, IOIS16 decoded according (default). Flash Write Enable. default setting flash memory write-protected. FWEN PENTIC+ allows flash written write command chip select signal prohibited FWEN SRAM Speed Select. SRAMSEL SRAM-15 selected. Otherwise, SRAM-70 used. default SRAM-70. Reserved.
FWEN
SRAMSEL
Special Control Register
These registers used special checking EEPROM access control. Signature Register (SR) signature register used identification that software driver easily distinguish between different chips. content read toggled order follows: Access Address: AMBase 00FF4H Access Type: Attribute Memory Read (2N)th time: (2N-1)th time: 10001000 00000000 where (after reset)
EEPROM Access Register (EEAR) This register located page used EEPROM read/write access control. inhibited when EECS/FCS pulled high. Access Address: IOBase Access Type: Read/Write
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
SYMBOL Reserved. Must EEPROM Write/Read Select. This selects EEPROM read/write sequence. EW/ER write sequence selected. EW/ER read sequence selected. EEPROM Operation Select. This enables EEPROM read/write sequence. EEPROM read/write sequence will started. reset read/write sequence finished aborted. DESCRIPTION
EEPROM Address/Data Register (ADR) This register located page used EEPROM address data transfer during EEPROM access. Access Address: IOBase Access Type: Read/Write
POWER-ON INITIALIZATION AUTO-LOADING PROCESS
When powered system should reset card first, required PCMCIA specifications. reset signal will trigger number internal operations: First, PENTIC+ monitors EECS/FCS determined where configurations stored. this pulled high, configurations stored flash memory; pulled low, they stored EEPROM. Then, within 10ms after reset pulse negated, PENTIC+ will automatically load configurations, data into configuration registers upper half SRAM EEPROM used). During this auto-load procedure PENTIC+ will assert IREQ Rdy/Bsy signaling, since socket configured memory-only interface during initialization. Note that this auto-load operation occurs only after hardware reset pulse. software reset (including setting COR.SRESET will invoke this operation.
EECS/FCS Pulled High
EECS/ pulled high, this indicates that configurations stored flash memory. Accordingly, after power-on reset PENTIC+ will automatically load configuration registers from flash memory. Ethernet stored flash memory will mapped into registers automatically when they read.
W89C926 PENTIC+
RESET
IREQ (Rdy/Bsy) CE1,2 F/EE sampling MSRD MSD0-7 MSAn TAUTO
MSAn flash address
TFOZ
flash address
TFOZ
MSRD
MSD0-7
EECS/FCS Pulled
EECS/ pulled low, this indicates that configurations, Ethernet stored EEPROM. this case, after power-on reset PENTIC+ will load configurations into configuration registers Ethernet into higher half SRAM memory (with auto-mapping registers attribute memory space, respectively). Since EEPROM used 93C66, serial EEPROM storage device, access time quite long system wait loading sequence (refer PCMCIA R2.1). Loading word EEPROM typically takes exact time EEPROM loading depends length must exceed
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
RESET
IREQ (Rdy/Bsy) TAUTO F/EE sampling EECS, MSWR MSD0-7 MSAn
CE1,2
TEEOZ TEER MSAn even address
TSOZ address
TSOZ
EECS
MSD0-2 EEload MSD0-7 byte high byte
MSWR
EEPROM Contents Load Back
When EEPROM used store CIS, PENTIC+ allows contents EEPROM modified means following sequence: write (EEAR, EW/ER write (ADR, address); write (ADR, word_data); wait repeat read(EEAR, EOS); until (EOS entire sequence should consecutive process will aborted.
W89C926 PENTIC+
register located page3 core controller used temporary register EEPROM read/write. When EEPROM load-back sequence specified above performed, content specified address will overwritten data. Note that since EEPROM word-aligned, each time sequence performed word data modified. address range available from ffH. make sure that EEPROM written correctly, programmer following read-check process read word from specified address EEPROM. write (EEAR, EW/ER write (ADR, address); wait repeat read(EEAR, EOS); until (EOS read(ADR); read word data entire sequence should consecutive process will aborted. Note that data will kept until they updated. That data read time afterwards unless data have been written.
SRAM Physical
When EEPROM used attribute memory storage, byte SRAM roles PENTIC+ design: first bytes SRAM serve Ethernet buffer ring, while remainder used temporary storage Ethernet storage EECS/FCS pulled low). detailed physical mapping SRAM memory shown table below. When flash memory used, only byte SRAM needed serve Ethernet ring buffer. SRAM Physical Address 0000H3FFFH 4000H 4001H 4002H 4003H 4004H 4005H 4006H 4007H 4008H400DH 400EH 400FH 4010H41FBH 41FCH7FFFH EECS/ pull Ethernet Buffer Board Type (05H) Checksum EECS/ pull high Ethernet Buffer
Unused
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Note that EECS/FCS pulled low, stored SRAM starting address 4010H. length depends word count specified first byte EEPROM. During poweron reset, PENTIC+ will load exact word count specified EEPROM rather than read bytes EEPROM. PENTIC+ will automatically translate address from host host tries read CIS. will translate attribute memory address assuming that first byte stored attribute memory, second byte stored 02H, forth. Users should assign accordingly, else lost. Also note that auto-load information write protection, PENTIC+ will ignore write operation above 4000H SRAM. necessary change settings, users should writing flash memory EEPROM. Minimal System Design low-cost, dedicated card designed using PENTIC+ chip, SRAM, serial EEPROM (93C66/93CS66), tail network interface MAU, along with certain other peripheral components. following sample table that used with this minimal system design: 'WinICard'
FLASH MEMORY ACCESS
flash access buffer SRAM share same memory support bus. address pins flash memory directly connected data accessed through bus. EECS/FCS active pulled high attribute memory accessed range 00000H 03FFFH common memory accessed range 04000H 1FFFFH. Note that CFB.FWE should before flash write command issued.
MODE OPERATION
mode provides channels system access. remote moves data between system memory space local memory space. local moves data between FIFO SLCT local memory space. However, since SLCT handle local operations without system intervention (refer data sheet SLCT), system perform only remote reads/writes. transmit operation, data should first moved from system local buffer memory. This simply "OUT" command Then system orders SLCT start transmission, local starts move data from buffer memory transmit FIFO transmission. receive operation, local moves received data from receive FIFO buffer asserts IREQ system when buffer ring needs serviced. system must move data
W89C926 PENTIC+
before buffer ring overflows. This done through remote read operation, which simply "IN" command
SHARED MEMORY MODE OPERATION
this mode, local memory mapped part system memory. When requires data transmission, host fills transmit buffer SRAM memory move operation then issues transmit command PENTIC+. When receives data, PENTIC+ will generate interrupt host asserting IREQ when more packets have been received. PENTIC+ will then place packets into shared memory. host should check shared memory remove data before buffer ring overflows. arbitration performed between host core shared memory usage. When memory accesses issued, arbiter will grant master acknowledge signal, which BACK WAIT signal host. There predefined priority PENTIC+; arbitration performed first-come, first-served basis. implement shared memory mode, PENTIC+ uses memory mapping register (MMA) memory mapping register (MMB) memory mapping control. Since PENTIC+ will operate 16-bit shared memory operation shared memory base address 00000H only, should written MMA. contents described below. (Memory Mapping Register used memory enable software reset. located space, 00H, accessed only shared memory mode. Access Address: IOBASE Access Type: write-only SYMBOL DESCRIPTION Reserved. Should this high, buffer memory accessed system; low, buffer memory access disabled. This power-on. shared memory mode software reset issued when written this bit. Writing this will clear software reset. This power-on.
SRESET
AUTO MEDIA-SWITCHING FUNCTION
PENTIC+ also provides user-friendly auto media-switching function. PENTIC+ configured TPI, link checking enabled, link broken, PENTIC+ will detect link status switch port immediately. After link repaired, PENTIC+ will detect good link switch back again. however, PENTIC+ configured link checking disabled, auto mediaswitching function will disabled.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
ARBITRATION STATE DIAGRAM
PENTIC+ handles arbitration automatically. operate four modes: idle state, slave read/write mode, mode, shared memory mode. PENTIC+ controls on-board devices decoding these modes. power-on, PENTIC+ idle mode. register read/write command issued, PENTIC+ enters slave read/write mode. local remote (I/O mode only) initiated PENTIC+ core coprocessor, PENTIC+ enters mode. memory command will place PENTIC+ memory mode. given time, PENTIC+ only state. PENTIC+ handles state changes automatically. However, events, such command memory command, requested same time; this case, PENTIC+ allocates firstcome, first-served basis. predefined priority within PENTIC+.
Register access Core Power-on Reset Idle access operation Slave read/ write
Memory Memory operation access
cases where system authority requested bus, PENTIC+ will drive WAIT that system insert wait states. After PENTIC+ released authority, WAIT deasserted instruct system stop inserting wait states.
SLCT CORE FUNCTION
SLCT core coprocessor five major logic blocks that control Ethernet operations: register files, transmit logic, receive logic, FIFO logic, logic. relationship between these blocks depicted following block diagram.
PCMCIA Slot Interface
Interface Logic
Transmit Logic 16-byte FIFO Receive Logic
TX/RX Logic
Register File
W89C926 PENTIC+
Core Register Files
register files SLCT accessed means commands. PENTIC+ should slave mode when system accesses register files. command register (CR) determines page number register file, while system address HA<0:4> selects register address from (I/O mode) from (shared memory mode). PCMCIA IORD IOWR read/write commands used activate operations. Refer W89C90 data sheet more detailed information registers. Interface Logic mapping mode, SLCT provides types operations, local remote DMA. shared memory mode, only local available. Local local transfers data from/to on-board buffers. perform data reception transmission from/to remote nodes network, data must moved from/to FIFO. enhance efficiency transmission, local transfers data batches: data first collected then moved batch. bytes data moved each transfer. This scheme reduces time wasted requesting bus. local begins requesting local bus. local available SLCT core, arbiter inside PENTIC+ responds once asserting acknowledge (BACK, refer LCE); other hand, currently authorized another device, arbiter will assert acknowledge SLCT must wait. Note that this sequence will affect host system system signals. After each batch data transferred, SLCT checks FIFO threshold levels determine another batch transfer should requested. Remote remote performed only mode. remote moves data between host local buffers. Unlike local DMA, remote word-wide: remote operation transfers word each time. Since remote simply system operation, sometimes affects system bus. remote interleaved with other devices, WAIT asserted force system insert wait states. PENTIC+ will automatically handle arbitration necessary.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
FIFO Logic SLCT 16-byte FIFO, which acts internal buffer compensate differences transmission/reception speed different DMAs. FIFO FIFO threshold pointers determine level which should initiate local DMA. threshold levels, Which different reception transmission, defined register. FIFO logic also provides FIFO overrun underrun signals network management purposes. received packets flooding into FIFO SLCT still does have authority, FIFO overrun. other hand, transmission begins before data into FIFO, underrun. Either case results network error. FIFO overruns underruns prevented changing values FIFO thresholds. Normally, data FIFO cannot read; reading FIFO data during normal operation cause WAIT asserted system hang. loopback mode, however, SLCT allows FIFO data read byte order check correctness loopback operation. Receive Logic receive logic responsible receiving serial network data packing data byte/word sequence. receive logic thus serial-to-parallel logic addition network detection capability. PENTIC+ accepts both physical addresses group addresses (multicast broadcast addresses). SLCT extracts address field from serial input data. then determines address acceptable according configurations defined Receive Configuration Register (RCR). address acceptable, packet reception aborted. address acceptable, data packet sent serial-to-parallel logic before being into FIFO. After receiving data packet, SLCT automatically adds four bytes data receive status, next packet pointer, bytes receive byte count into FIFO network management purposes. receive status contains status incoming packet, that system determine packet desired. next packet pointer points starting address next packet local receive ring. receive byte count length packet received SLCT. Note that receive byte count different from "length" field specified Ethernet packet format. These four bytes data will transferred local buffer with last batch local DMA. However, these four bytes stored first four addresses packet. Transmit Logic SLCT must filled before transmission begin. That local read must begin before SLCT starts transmission. SLCT first transmits bits preamble, then bits SFD, then data packet. parallel-to-serial logic serializes data from FIFO into data packet. After data packet, SLCT optionally adds four bytes cyclic redundancy code (CRC) tail packet. protocol determines network operations PENTIC+. Collision detection, random backoff, auto retransmit implemented transmit logic. protocol ensures that PENTIC+ follows IEEE 802.3 protocol. Module PENTIC+ also contains serial network adaptor (SNA), which adapts non-return-to-zero (NRZ) used core processor host system Manchester coded network symbols. kinds interfacing signals provided PENTIC+: interface Ethernet coaxial
W89C926 PENTIC+
interface Cheapernet. contains three blocks: phase locked loop (PLL), Manchester encoder/decoder, collision decoder well crystal/oscillator logic.
Coax
Interface
Transmit Logic
Osc/ Crystal
Receive Logic
Manchester encoder/decoder handles code interpretation between signals Manchester coded signals. locks receiving signals with internal voltage control oscillator (VCO) that network noise eliminated before signals enter core coprocessor. collision decoder detects whether collision occurred network. oscillator logic supplies PENTIC+ with required clock. This clock also supplies clocking system.
TWISTED PAIR INTERFACE MODULE FUNCTION
Transmit Driver There signals data transmission: true complement Manchester differential data (TXO+/-). These signals resistively combined form pre-equalized differential pair, which then passed twisted-pair cable transmitter filter optional common mode choke. Smart Squelch main function this block determine when valid data present differential receiving inputs (RXI+/-). ensure that impulse noise medium will taken valid data, this circuit adopts combination amplitude timing measurements determine validity input signals. qualify incoming data, smart squelch circuitry monitors signals three peaks alternating polarity that occur within window. Once this condition been satisfied, squelch level reduced minimize noise effect chances causing premature Start Idle (SOI) pulse detection. receiver detects activity receive line while packets being transmitted, incoming data qualified five peaks alternating polarity prevent false collisions caused impulse noise. squelch function returns squelch state under following conditions:
normal signal inverted signal missing signal
missing signal assumed when transitions have occurred receiver after packet arrived. this case, normal signal generated appended data.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Collision Detection collision detection logic determines when transmit receive signals occur simultaneously twisted pair cable. Collisions will reported when device link-fail state. collision signal also generated when transceiver detected jabber condition when test being performed. Test Signal Quality Error (SQE) test used test collision signaling circuitry twisted-pair transceiver module. After each packet transmission, signal sent SLCT. SLCT expects this signal will flag error does exist. Jabber jabber timer monitors transmitter disables transmission transmitter active greater than 26.2 jabber will re-enable transmitter after SLCT been idle least Link Integrity During periods inactivity, link pulses generated received both MAUs either twisted pair ensure that cable been broken shorted. positive, link integrity signal generated twisted-pair transceiver transmitted twisted pair cable every during periods transmission activity. PENTIC+ assumes link-good state detects valid link pulse activity twisted-pair transceiver receive circuit. neither receive data link pulse (positive negative) detected within PENTIC+ enters link-fail state. When link-fail condition occurs, four consecutive positive link pulses eight negative link pulses) must received before link-good condition assumed.
CORE REGISTERS
This section lists access addresses access types core registers. Refer W89C90 W89C901 data sheet more detailed information. Page Address Assignments (PS1 RA0-3 Command (CR) Current Local Address (CLDA0) Current Local Address (CLDA1) Boundary Pointer (BNRY) Transmit Status Register (TSR) Number Collisions Register (NCR) FIFO (FIFO) Interrupt Status Register (ISR) Current Remote Address (CRDA0) READ Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register (TBCR0) Transmit Byte Count Register (TBCR1) Interrupt Status Register (ISR) Remote Start Address Register (RSAR0) WRITE
W89C926 PENTIC+
Page Address Assignments (PS1 continued
RA0-3
READ Current Remote Address (CRDA1) Reserved Reserved Received Status Register (RSR) Tally Counter (Frame Alignment Errors) (CNTR0) Tally Counter (CRC Errors)(CNTR1) Tally Counter (Missed Packet Errors) (CNRT2)
WRITE Remote Start Address Register (RSAR1) Remote Byte Count Register (RBCR0) Remote Byte Count Register (RBCR1) Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR)
Page Address Assignments (PS1 RA0-3 Command (CR) Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Current Page Register (CURR) Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR READ Command (CR) Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Physical Address Register (PAR Current Page Register (CURR) Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR Multicast Address (MAR WRITE
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Page Address Assignments (PS1 RA0-3 READ Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address (TPSR) Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR) WRITE Command (CR) Current Local Address (CLDA0) Current Local Address (CLDA1) Remote Next Package Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Transmit Configuration Reserved Reserved
Note: Page registers should accessed only diagnostic purposes. They should modified during operation. Page should never modified.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering seconds maximum) Tolerance SYMBOL VOUT MIN. -0.5 VSS-0.5 VSS-0.5 MAX. VDD+0.5 VDD+0.5 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
W89C926 PENTIC+
CHARACTERISTICS
Power Supply:
(VDD 4.75V 5.25V,
PARAMETER Average Idle Supply Current Average Transmit Supply Current
Notes: MHz, GND. MHz, normal transmitting operation.
Note Note
SYM. IAVI IAVT
CONDITIONS 5.25V 5.25V
MIN.
MAX.
UNIT
Digital:
(VDD 4.75V 5.25V,
PARAMETER Input Voltage High Input Voltage Output Voltage High Output Voltage Output Sink Current High Output Drive Current Output Sink Current* High Output Drive Current* Output 3-State Leakage Current
SYM. IOL1 IOH1 IOL2
IOH2 IOTR
CONDITIONS
MIN. VSS-0.5
MAX. VDD+0.5
UNIT
4.75V, IOL-MIN 4.75V, IOL-MAX
5.25V
These parameteres MSD0-7 MSA0-15.
AUI:
(VDD 4.75V 5.25V,
PARAMETER Differential Output Voltage (TX+/) Differential Output Voltage Imbalance (TX+/-) Undershoot Voltage (TX+/-) Differential Squelch Threshold (CD+/-, RX+/-) Differential Input Common Mode Voltage (CD+/-, RX+/-)
SYM.
CONDITIONS With test load With test load With test load
MIN. +/-550 -175
MAX. +/-1200 -300
UNIT
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Twisted Pair:
(VDD 4.75V 5.25V,
PARAMETER RXI+/- Differential Input Resistance RXI+/- Open Circuit Input Voltage (bias) RXI+/- Differential Input Voltage Range RXI+/- Positive Squelched Threshold RXI+/- Negative Squelched Threshold RXI+/- Positive Unsquelched Threshold RXI+/- Negative Unsquelched Threshold TXO+/- Differential Output Voltage
SYM. VTIB VTIV VTPS VTNS VTPU VTNU
CONDITIONS
MIN. -2.75
MAX. VDD-1.0 -300 -200
UNIT
-3.1 -585 -350
With test load
SWITCHING CHARACTERISTICS
Memory Support Access (SRAM Access)
Address MSRD
MSAn Even Address
MSDn (Read) MSWR MSDn (Write) Valid Valid
Valid
Valid
W89C926 PENTIC+
SRAM (upper lower values SRAMs, respectively)
SYMBOL Read cycle time. MSA0-15 valid MSD0-7 read data valid. MSD0-7 read data hold valid from MSA0-15 change. MSD0-7 read data hold from MSRD deasserted. held valid after MSRD deasserted. MSA0-15 held valid after MSRD deasserted. asserted MSWR asserted MSWR pulse width asserted MSWR deasserted. MSA0-15 held valid after MSWR deasserted. MSD0-7 write data setup before MSWR asserted. MSD0-7 write data hold after MSWR deasserted. Even byte MSWR deasserted byte MSWR asserted. (see note) held valid after MSWR deasserted. Even byte address invalid byte address valid. (see note) Command recovery time. DESCRIPTION MIN.
Note: This timing invalid byte access, e.g, attribute memory reading SRAM image.
MAX.
UNIT
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Flash Memory Memory Support Access (Flash Access)
MSAn
MSRD MSWR
MSDn (Read)
Valid
MSDn (Write)
Valid
SYMBOL T12a T12b T12c
DESCRIPTION MSA0-16 valid asserted. asserted MSRD MSWR asserted. MSA0-16 held valid after MSRD MSWR deasserted. held valid after MSRD deasserted. held valid after MSWR deasserted. MSRD asserted read data valid. Read data hold from MSRD deasserted. Write data setup MSWR deasserted. Write data hold from MSWR deasserted. Access cycle time Write pulse width asserted MSWR deasserted Write recovery time before read Read recovery time before write Consecutive same commands interval
MIN.
MAX.
UNIT
W89C926 PENTIC+
Attribute Memory Access
HA0-16 CE1,2 WAIT HD0-7 (even) (Read) HD0-7 (even) (Write)
Valid Valid
SYMBOL
DESCRIPTION HA0-16, valid asserted
asserted asserted
MIN.
MAX.
UNIT
asserted WAIT asserted asserted HD0-7 read data valid (see note) HD0-7 write data setup before deasserted HD0-7 write data hold from deasserted HD0-7 read data disable from deasserted Read data setup before WAIT deasserted WAIT deasserted deasserted
hold valid from deasserted
HA0-16, hold valid from deasserted HA0-16, setup deasserted
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Attribute Memory Access, continued
SYMBOL T18a T18b T19a T19b
DESCRIPTION
asserted deasserted
MIN.
MAX.
UNIT
pulse width HA0-16, valid read data valid (see note)
asserted read data valid (see note)
WAIT pulse width deasserted next asserted deasserted next asserted Read cycle time Write cycle time
Note: These timings specified when PENTIC+ does assert WAIT
Common Memory Access
HA0-16
high
CE1,2 WAIT HD0-15 (Read) HD0-15 (Write) Valid Valid
W89C926 PENTIC+
Common Memory Access, continued
SYMBOL T15a T15b T16a T16b
DESCRIPTION HA0-16, valid assert.
assert assert.
MIN.
MAX.
UNIT
assert WAIT asserts. HD0-15 write data setup before deasserts. HD0-15 write data hold from deasserts. HD0-15 read data disable from deasserts. Read data setup before WAIT deasserts. WAIT deasserts deassert.
hold valid from deassert
HA0-16, hold valid from deassert HA0-16, setup deassert
assert deassert
pulse width WAIT pulse width deassert next assert deassert next assert Read cycle time Write cycle time
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
PCMCIA Slave Access
IORD IOWR
IOIS16
WAIT INPACK (Read) (Write)
MSAn Even Address Address
MSRD
MSDn (Read) MSWR MSDn (Write)
W89C926 PENTIC+
PCMCIA Slave Access
SYMBOL T13a T13b T14a T14b T15a T15b T16a DESCRIPTION HA0-16 valid asserted
Note
MIN.
MAX.
UNIT
HA0-16 valid IORD, IOWR asserted.
Note
asserted asserted. asserted IORD, IOWR asserted.
HA0-16 valid asserted. HA0-16 valid IORD, IOWR asserted. HA0-16 valid IOIS16 asserted.
Note
IORD, IOWR asserted WAIT asserted.
Note
IORD asserted INPACK asserted. IORD asserted HD0-15 read data valid. asserted HD0-15 read data valid. IORD, IOWR minimum width time.
Note Note Note
WAIT deasserted HD0-15 memory read data Note valid. WAIT deasserted HD0-15 read data valid.
Note
HD0-15 read data hold after IORD deasserted. HD0-15 write data setup before deasserted. HD0-15 write data setup befor IOWR assert. HD0-15 write data hold after deasserted. HD0-15 write data hold after IOWR deasserted. deasserted deasserted.
Note
IORD, IOWR deasserted deasserted.
Note
deasserted deasserted. IORD, IOWR deasserted deasserted. deasserted HA0-16 deasserted.
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
PCMCIA slave access, continued
SYMBOL T16b T23a T23b T26a T26b T27a T27b
DESCRIPTION IORD, IOWR deasserted HA0-16 deasserted. HA0-16 deasserted IOIS16 deasserted. IORD deasserted INPACK deasserted. MSA0-14 asserted WAITdeasserted.
asserted asserted.
Note Note
MIN.
MAX.
UNIT
asserted asserted.
Note
byte read data valid HD0-15 read data valid. byte read data hold after MSRD deasserted. byte read data hold after MSRD deasserted. MSA0-14 valid MSWR asserted. second MSWR asserted before WAIT deasserted.
Note Note.10
write data setup before MSWR deasserted. write data setup before MSWR deasserted.
Note.10
write data hold after MSWR deasserted. write data hold after MSWR deasserted. Note.10 Command deasserted next command asserted
Notes: This timing insert wait states. WAIT asserted core cannot service access immediately; will hold asserted until core ready, causing system insert wait states. This timing shared memory access. This timing access. IOIS16 asserted 16-bit transfers. Read data valid referenced WAIT when wait states inserted. wait states inserted, read data valid referenced from IORD. asserted access deasserted common memory access. INPACK asserted only read operation. This shared memory access without contention. This timing SRAM-15.
W89C926 PENTIC+
Reset Auto-Initialization Timing
RESET
IREQ
EECS/FCS sampling
EECS/FCS MSRD MSWR MSD0-7 MSAn
EECS/FCS floating
Auto-Loading
Flash Memory Loading Flash Auto-Loading EECS/FCS pulled high)
Flash Memory Loading
Serial EEPROM loading EEPROM Auto-Loading EECS/FCS pulled low)
SRAM Write even byte
SRAM Write byte
SYMBOL
DESCRIPTION Reset pulse width Reset deasserted EECS/FCS sampling Reset deasserted asserted Nonvolatile memory auto-load time Flash memory auto-reading recovery time SRAM image auto-writing recovery time EEPROM auto-reading recovery time
MIN.
MAX.
UNIT
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Serial EEPROM Timing
EECS
MSD2 (SCK) MSD1 (DI)
MSD0 (DO)
Serial EEPROM Timing
SYMBOL DESCRIPTION EECS asserted EECS hold from MSD2 time MSD2 time MSD2 clock period MSD1 time MSD2 high MSD1 hold time from MSD2 high MSD0 valid from MSD2 high MIN. MAX. UNIT
Transmit Timing (End Transmit)
TTOI TX+/1 TX+/0 TTOH
W89C926 PENTIC+
SYMBOL TTOH TTOI
DESCRIPTION Transmit Output High Before Idle Transmit Output Idle Time
MIN.
MAX. 8000
UNIT
Receive Timing (End Receive)
RX+/RXI+ TEOP1 RX-/RXI1
TEOP0
RX+/RXI+ RX-/RXI-
SYMBOL TEOP1 TEOP0
DESCRIPTION Packet Received Hold Time after Logic Packet Received Hold Time after Logic
MIN.
MAX.
UNIT
Note: These parameters specified design tested.
Link Pulse Timing
TXO+
TXO-
SYMBOL TLPI TLPW
DESCRIPTION Link Output Pulse Interval Link Output Pulse Width
MIN.
MAX.
UNIT
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Transmit Timing (End Transmit)
TXO+
TETH1
TXO-
TXO+
TETH1
TXO-
SYMBOL TETH1
DESCRIPTION Packet Transmitted Hold Time (TXP/N)
MIN.
MAX.
UNIT
Note: This parameter specified design tested.
TIMING TEST CONDITIONS
PARAMETER Supply Voltage (VDD/VSS) Temperature Input Test Pattern Levels (TTL/CMOS) Input Rise Fall Times (TTL/CMOS) Input Output Pattern Reference Level (TTL/CMOS) Input Waveform Level (Diff) Input Output Waveform Reference Levels (Diff) 3-State Reference Levels TEST CONDITIONS 0.25V C/70° 3.0V 1.3V -350 -1315 Point Differential Float 0.5V
Note: above specifications valid only mandatory isolations properly employed differential signals taken pulse transformer.
W89C926 PENTIC+
Output Load
(Note
DEVICE UNDER Input TEST
2.2K Output
(Note
Notes: Load capacitance employed depends output type: 3SL, MOS, TPI, AUI: 3SH, OCH: Specifications which measure delays from active state High-Z state guaranteed production testing, characterized using correlated determine true driver turn-off time eliminating inherent delay times measurements. Open push-pull outputs during timing test. test. test. High-Z active active High-Z measurements. High-Z active high active high High-Z measurements.
Capacitance
SYMBOL COUT
PARAMETER Input Capacitance Output Capacitance
UNIT
Derating Factor
Output timing measured with purely capacitive load following correction factor used other loads (this factor preliminary): Derating 3SL, -0.05 nS/pF Derating 3SH, OCL, -0.03 nS/pF
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Transmit Test Load
Note: above diagram, signals taken from side pulse transformer. pulse transformer used testing 100µH +/-0.1% Pulse Engineering PE64103.
Transmit Test Load
TXO+
1.21K
FILTER
TXO-
Note: above diagram, filter used testing Valor FL1012.
W89C926 PENTIC+
PACKAGE DIMENSIONS
PENTIC+ packaged 100-pin TQFP type card applications. Detailed dimensions shown below.
W89C926F
Symbol
Dimensions inches Dimensions 0.004 0.002 0.055 0.002 0.013 0.002 0.004 0.008 0.004 0.551 0.004 0.787 0.004 0.026 0.630 0.004 0.866 0.004 0.024 0.006 0.039 0.003 0.10 0.05 1.40 0.05 0.32 0.06 0.10 0.20 0.09 14.00 0.10 20.00 0.10 0.65 16.00 0.10 22.00 0.10 0.60 0.15 1.00 0.08
Publication Release Date: January 1996 Revision
W89C926 PENTIC+
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
803, World Trade Square, Tower Winbond Memory Lab. Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 First Street, Jose, FAX: 852-27552064 FAX: 886-3-5792668 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: data specifications subject change without notice.

W89C926 PENTIC+ CMOS device designed easy implementation PCMCIA R2.1 c

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