Intel Chipset Family: 82815G/82815EG Graphics Memory Controller (GMCH)
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Intel Chipset Family: 82815G/82815EG Graphics Memory Controller (GMCH)
with Universal Socket Datasheet
September 2001
Document Number: 290714-001
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two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation.
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Copyright 2001, Intel Corporation
82815G GMCH Datasheet
Contents
Introduction 1.10 Related Documents Intel 815G Chipset Intel 82815G GMCH Overview.16 Host Interface.17 System Memory Interface Display Cache Interface.17 Interface Intel 82815G GMCH Integrated Graphics Support 1.8.1 Display, Digital Video Out, LCD/Flat Panel/Digital System Clocking GMCH Power Delivery
Signal Description.21 2.10 2.11 2.12 Host Interface Signals.22 System Memory Interface Signals Display Cache Interface Signals Interface Signals.26 Display Interface Signals.26 Digital Video Output Signals/TV-Out Pins.27 Power Signals Clock Signals GMCH Power-Up/Reset Strap Options.29 Intel 815G Display Cache Intel Signal Mapping.30 Display Cache Mapping Connector Intel Intel 815G Signal Name Changes
Configuration Registers Register Nomenclature Access Attributes Configuration Space Access.36 3.2.1 Configuration Mechanism 3.2.2 Logical Configuration Mechanism 3.2.3 Primary (PCI0) Downstream Configuration Mechanism 3.2.4 Internal Graphics Device Configuration Mechanism 3.2.5 GMCH Register Introduction Mapped Registers 3.3.1 CONF_ADDRConfiguration Address Register 3.3.2 CONF_DATAConfiguration Data Register.40 Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 3.4.1 VID-Vendor Identification Register (Device 3.4.2 DID-Device Identification Register (Device 0).43 3.4.3 PCICMD-PCI Command Register (Device 3.4.4 PCISTS-PCI Status Register (Device 0).45
82815G GMCH Datasheet
RID-Revision Identification Register (Device 0).46 SUBC-Sub-Class Code Register (Device 0).46 BCC-Base Class Code Register (Device 0).47 MLT-Master Latency Timer Register (Device HDR-Header Type Register (Device APBASE-Aperture Base Configuration Register (Device Mode Only) 3.4.11 SVID-Subsystem Vendor Identification Register (Device 3.4.12 SID-Subsystem Identification Register (Device 3.4.13 CAPPTR-Capabilities Pointer (Device 3.4.14 GMCHCFG-GMCH Configuration Register (Device 3.4.15 APCONT-Aperture Control (Device 3.4.16 DRP-DRAM Population Register (Device 0).54 3.4.17 DRAMT-DRAM Timing Register (Device 0).55 3.4.18 DRP2-DRAM Population Register (Device 0).56 3.4.19 FDHC-Fixed DRAM Hole Control Register (Device 0).57 3.4.20 PAM-Programmable Attributes Registers (Device 3.4.21 SMRAM-System Management Control Register (Device 3.4.22 MISCC-Miscellaneous Control Register (Device 3.4.23 CAPID-Capability Identification (Device Mode Only).66 3.4.24 BUFF_SC-System Memory Buffer Strength Control Register (Device 3.4.25 BUFF_SC2-System Memory Buffer Strength Control Register (Device 3.4.26 SM_RCOMP-System Memory Compensation Control Register (Device 3.4.27 SM-System Memory Control Register 3.4.28 ACAPID-AGP Capability Identifier Register (Device Mode Only) 3.4.29 AGPSTAT-AGP Status Register (Device Mode Only) 3.4.30 AGPCMD-AGP Command Register (Device Mode Only) 3.4.31 AGPCTRL-AGP Control Register (Device Mode Only).76 3.4.32 APSIZE-Aperture Size (Device Mode Only) 3.4.33 ATTBASE-Aperture Translation Table Base Register (Device Mode Only) 3.4.34 AMTT-AGP Multi-Transaction Timer (Device Mode Only) 3.4.35 LPTT-AGP Priority Transaction Timer Register (Device Mode Only) 3.4.36 GMCHCFG-GMCH Configuration Register (Device Mode Only) 3.4.37 ERRCMD-Error Command Register (Device Mode Only) AGP/PCI Bridge Registers (Device Visible Mode Only) 3.5.1 VID1-Vendor Identification Register (Device 3.5.2 DID1-Device Identification Register (Device 1).85 3.5.3 PCICMD1-PCI-PCI Command Register (Device 1).85 3.5.4 PCISTS1-PCI-PCI Status Register (Device 1).87 3.5.5 RID1-Revision Identification Register (Device 1).88 3.5.6 SUBC1-Sub-Class Code Register (Device 1).88 3.5.7 BCC1-Base Class Code Register (Device 1).88 3.5.8 MLT1-Master Latency Timer Register (Device 3.5.9 HDR1-Header Type Register (Device 3.5.10 PBUSN-Primary Number Register (Device 3.5.11 SBUSN-Secondary Number Register (Device 3.5.12 SUBUSN-Subordinate Number Register (Device 1).90
3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 3.4.10
82815G GMCH Datasheet
3.5.13 SMLT-Secondary Master Latency Timer Register Device 3.5.14 IOBASE-I/O Base Address Register (Device 3.5.15 IOLIMIT-I/O Limit Address Register (Device 3.5.16 SSTS-Secondary PCI-PCI Status Register (Device 3.5.17 MBASE-Memory Base Address Register (Device 3.5.18 MLIMIT-Memory Limit Address Register (Device 3.5.19 PMBASE-Prefetchable Memory Base Address Register (Device 3.5.20 PMLIMIT-Prefetchable Memory Limit Address Register (Device 3.5.21 BCTRL-PCI-PCI Bridge Control Register (Device 3.5.22 ERRCMD1-Error Command Register (Device .101 Graphics Device Registers (Device Visible Mode Only).102 3.6.1 VID2-Vendor Identification Register (Device .103 3.6.2 DID2-Device Identification Register (Device 2).103 3.6.3 PCICMD2-PCI Command Register (Device .104 3.6.4 PCISTS2-PCI Status Register (Device 2).105 3.6.5 RID2-Revision Identification Register (Device 2).106 3.6.6 PI-Programming Interface Register (Device 2).106 3.6.7 SUBC2-Sub-Class Code Register (Device 2).106 3.6.8 BCC2-Base Class Code Register (Device 2).107 3.6.9 CLS-Cache Line Size Register (Device .107 3.6.10 MLT2-Master Latency Timer Register (Device .107 3.6.11 HDR2-Header Type Register (Device .108 3.6.12 BIST-BIST Register (Device .108 3.6.13 GMADR-Graphics Memory Range Address Register (Device .109 3.6.14 MMADR-Memory Mapped Range Address Register (Device 2).110 3.6.15 SVID-Subsystem Vendor Identification Register (Device .110 3.6.16 SID-Subsystem Identification Register (Device .111 3.6.17 ROMADR-Video BIOS Base Address Register (Device .111 3.6.18 CAPPOINT-Capabilities Pointer Register (Device 2).112 3.6.19 INTRLINE-Interrupt Line Register (Device .112 3.6.20 INTRPIN-Interrupt Register (Device .112 3.6.21 MINGNT-Minimum Grant Register (Device .112 3.6.22 MAXLAT-Maximum Latency Register (Device .113 3.6.23 PM_CAPID-Power Management Capabilities Register (Device .113 3.6.24 PM_CAP-Power Management Capabilities Register (Device .114 3.6.25 PM_CS-Power Management Control/Status Register (Device 2).115 Display Cache Interface.116 3.7.1 DRT-DRAM Type.116 3.7.2 DRAMCL-DRAM Control Low.117 3.7.3 DRAMCH-DRAM Control High .118 Display Cache Detect Diagnostic Registers .119 3.8.1 GRX-GRX Graphics Controller Index Register.119 3.8.2 MSRMiscellaneous Output .120 3.8.3 GR06Miscellaneous Register .120 3.8.4 GR10Address Mapping .121 3.8.5 GR11Page Selector .121 System Address Map.123 4.1.1 Memory Address Ranges.124 4.1.2 Compatibility Area .125 4.1.3 Extended Memory Area.127
Functional Description .123
82815G GMCH Datasheet
4.10 4.11
4.1.3.1 System Management Mode (SMM) Memory Range.130 Memory Shadowing .131 Address Space.131 4.3.1 GMCH Decode Rules Cross-Bridge Address Mapping.131 4.3.2 Address Decode Rules.131 4.3.2.1 Interface Decode Rules.132 4.3.2.2 Legacy Ranges.133 Host Interface.135 4.4.1 Host Device Support .135 4.4.2 Special Cycles .137 System Memory DRAM Interface .138 4.5.1 DRAM Organization Configuration .138 4.5.1.1 Configuration Mechanism DIMMs .139 4.5.1.2 DRAM Register Programming .140 4.5.2 DRAM Address Translation Decoding.140 4.5.3 DRAM Array Connectivity.141 4.5.4 SDRAMT Register Programming .142 4.5.5 SDRAM Paging Policy.142 Intel Dynamic Video Memory Technology (D.V.M.T.) .142 Display Cache Interface.143 4.7.1 Supported DRAM Types Display Cache Memory .143 4.7.2 Memory Configurations .144 4.7.3 Address Translation .145 4.7.4 Display Cache Interface Timing .145 Internal Graphics Device.146 4.8.1 3D/2D Instruction Processing.146 4.8.2 Engine.147 4.8.3 Buffers .147 4.8.4 Setup .148 4.8.5 Texturing .148 4.8.6 Operation .150 4.8.7 Fixed Blitter (BLT) Stretch Blitter (STRBLT) Engines .150 4.8.7.1 Fixed Engine .151 4.8.7.2 Arithmetic Stretch Engine.151 4.8.8 Hardware Motion Compensation.151 4.8.9 Hardware Cursor .152 4.8.10 Overlay Engine .152 4.8.11 Display.153 4.8.12 Flat Panel/Digital Interface/1.8 TV-Out Interface.154 4.8.13 (Display Data Channel).155 System Reset GMCH .156 System Clock Description .156 Power Management.156 4.11.1 Specifications Supported.156 Intel 82815G GMCH Ballout.157 Package Information.165
Ballout Package Information.157
Testability.167 Tree Testability Algorithm Example .168 6.1.1 Test Pattern Consideration Chains .168
82815G GMCH Datasheet
Tree Initialization .169 6.2.1 Chain [1:6] Initialization .169 6.2.2 Chain [7:8] Initialization .169 Chain.170 .174
82815G GMCH Datasheet
Figures
Figure Intel 815G Chipset Universal Platform System Block Diagram Figure Intel 82815G GMCH Block Diagram.16 Figure Registers.59 Figure System Memory Address .124 Figure Detailed Memory System Address .124 Figure DRAM Array Sockets.141 Figure GMCH Display Cache Interface .144 Figure 3D/2D Pipeline Preprocessor .146 Figure Data Flow Pipeline.147 Figure 815G GMCH Ballout (Top View-Left Side) .158 Figure 815G GMCH Ballout (Top View-Right Side).159 Figure GMCH Package Dimensions (Top Side Views) .165 Figure GMCH Package Dimensions (Bottom View) .166 Figure Tree Implementation .167
Tables
Table Supported System System Memory Frequencies.19 Table Intel 82815 Intel 82815G Name Change Table GMCH Configuration Space (Device 0).41 Table Supported System Memory DIMM Configurations Table Attribute Assignments Table Registers Associated Memory Segments.59 Table Summary GMCH Error Sources, Enables Status Flags.83 Table GMCH Configuration Space (Device 1).84 Table Device Configuration Space Address (Internal Graphics) .102 Table Memory Segments Their Attributes .125 Table Combinations .134 Table Summary Transactions Supported GMCH.135 Table Host Responses Supported GMCH.136 Table Special Cycles .137 Table Sample Possible Match Options Row/2-DIMM Configurations .139 Table Data Bytes DIMM Used Programming DRAM Registers .140 Table GMCH DRAM Address Function .141 Table Programmable SDRAM Timing Parameters .142 Table Memory Size Each Configuration: .144 Table GMCH Local Memory Address Mapping .145 Table Partial List Display Modes Supported.153 Table Partial List Flat Panel Modes Supported .154 Table Partial List TV-Out Modes Supported.155 Table Alphabetical Ball Assignment .160 Table Package Dimensions (see Figure Figure .166 Table Test Pattern Example (Pin from Figure .168 Table Chain Inputs Output: SMAA5 (A12).170 Table Chain Inputs Output: SMAA2 (F12).170 Table Chain Inputs Output: SMAA0 (D13) .171 Table Chain Inputs Output: SMAA9 (D13) .171 Table Chain Inputs Output: SMD31 (K5).172 Table Chain Inputs Output: SMAA11 (A13).173 Table Chain Inputs Output: SMAA8 (D12) .173 Table Chain Inputs Output: SMAA4 (B12).174
82815G GMCH Datasheet
Revision History
Revision -001 Initial Release Description Date September 2001
82815G GMCH Datasheet
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82815G GMCH Datasheet
Intel® 82815G GMCH Features
Processor/Host Support
Optimized Intel® Celeronprocessors using 0.13 micron
technology Support Intel® Pentium® processors using 0.13 micron technology system frequency Supports Processor 370-Pin Socket (FC-PGA/FC-PGA2) Supports 32-Bit System Addressing deep in-order queue; deep request queue Supports single-processor systems only In-order Dynamic Deferred Transaction Support 66/100/133MHz System Frequency AGTL/AGTL+ Buffer Support universal motherboard design
Graphics Visual Enhancements
Flat Gouraud Shading Maps with Trilinear Anisotropic Filtering Full Color Specular Fogging Atmospheric Effects Buffering Pipe Clipping Backface Culling
Graphics Texturing Enhancements Digital Video Output Display
Pixel Perspective Correction Texture Mapping Texture Compositing Texture Color Keying/Chroma Keying Flat Panel Monitor/Digital Interface Digital Video Output with external encoder Integrated 24-bit RAMDAC Gamma Corrected Video DDC2B Compliant 1600x1200 8-bit Color Refresh Hardware Accelerated Functions Operand Raster BitBLTs 64x64x3 Color Transparent Cursor Motion Compensation Assistance MPEG2 Decode Software Digital Video Port NTSC Support Overlay Engine with Bilinear Filtering Independent gamma correction, saturation, brightness contrast overlay
Integrated SDRAM Controller
using 16-, 64-, 128-, 256-Mb technology double-sided DIMMs system memory double-sided single-sided DIMMs system memory bus. 64-bit data interface 100/133 system memory frequency Support Asymmetrical SDRAM addressing only Support SDRAM device width Unbuffered, Non-ECC SDRAM only supported Refresh Mechanism: only supported Enhanced Open page arbitration SDRAM paging scheme Suspend support Intelligent Centralized Arbitration Model Optimum Concurrency Support Concurrent operations processor System busses supported dedicated arbitration data buffering Distributed Data Buffering Model optimum concurrency SDRAM Write Buffer with read-around-write capability Dedicated processor-SDRAM, interface-SDRAM Graphics-SDRAM Read Buffers SMRAM space remapping A0000h (128 Optional Extended SMRAM space above additional TSEG from Memory, cacheable Stop Clock Grant Halt special cycle translation from host interface ACPI Compliant power management APIC Buffer Management SMI, SCI, SERR error indication Hyper Pipelined Architecture Parallel Data Processing (PDP) Precise Pixel Interpolation (PPI) Full Acceleration Motion Video Acceleration Supports System Memory while running non-CPC mode
Graphics
Arbitration Scheme Concurrency
Arithmetic Stretch Blitter Video
Data Buffering
Integrated Graphics Memory Controller
Intel D.V.M. Technology
Power Management Functions
Display Cache Interface
32-bit data interface SDRAM interface only. Flexible In-Line Memory Module (AIMM) Implementation Support 1Mx16, 2Mx32 AIMM card maximum addressable
Supporting Bridge Packaging/Power
82801BA Controller (ICH2) with 82815EG 82801AA Controller (ICH) with 82815G 544-pin 1.85 core with CMOS
Integrated Graphics Controller
82815G GMCH Datasheet
Intel 82815G GMCH Simplified Block Diagram
HA[31:3]# HD[63:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# CPURST# GTLREF[1:0] SMAA[12:0] SMAB[7:4]# SMAC[7:4]# SBS[1:0] SMD[63:0] SDQM[7:0] SCSA[5:0]# SCSB[5:0]# SRAS# SCAS# SWE# SCKE[5:0] SRCOMP HCLK SCLK LTCLK[1:0] LOCLK LRCLK DCLKREF HLCLK RESET# HLREF HL[10:0] HLSTRB HLSTRB# HLZCOMP
Display Interface Host Interface
VSYNC HSYNC IREF GREEN BLUE DDCK DDDA
Digital Video
LTVCL LTVDA TVCLKIN/INT# LTVCLKOUT[1:0] LTVBLANK# LTVDATA[11:0] LTVSYNC LTVHSYNC LCS# LDQM[3:0] LSRAS# LSCAS# LMA[11:0] LWE# LMD[31:0]
System Memory Interface
Display Cache Interface
Clock Reset Signals
Interface
82815G GMCH Datasheet
Introduction
Introduction
Intel 82815G chipset with universal socket high-flexibility chipset designed extend from basic graphics/multimedia platform mainstream performance desktop platform. chipset consists Intel 82815G Graphics Memory Controller (GMCH) Controller (ICH ICH2) subsystem. GMCH integrates system memory SDRAM controller that supports 64-bit 100/133 SDRAM array. 82815G GMCH integrates Display Cache SDRAM controller that supports 32-bit SDRAM array enhanced integrated graphics performance. There port capability 82815G GMCH. 82815G GMCH uses internal graphics only. port populated with display cache support internal graphics. This datasheet provides overview Intel chipset with universal socket (see Section 1.2). remainder document describes 82815G Graphics Memory Controller (GMCH). There chipsets chipset family: Intel® 82815 chipset: This chipset contains 82815 Intel® 82801AA (ICH). Intel® 82815E chipset: This chipset contains 82815E Intel® 82801BA (ICH2). Intel® 82815P chipset: This chipset contains 82815P 82801AA. There internal graphics capability. This GMCH uses port only. Intel® 82815EP chipset: This chipset contains 82815EP 82801BA. There internal graphics capability. This GMCH uses port only. Intel® 82815G chipset: This chipset contains 82815G GMCH 82801AA. There port capability. This GMCH uses internal graphics only. Intel® 82815EG chipset. This chipset contains 82815EG GMCH 82801BA. There port capability. This GMCH uses internal graphics only. only component difference between 82815 GMCH 82815E GMCH Controller Hub. only component difference between 82815P GMCH 82815EP GMCH Controller only component difference between 82815G GMCH 82815EG GMCH Controller Hub. 815G chipset with universal socket supports following processors: Intel® Celeronprocessor based 0.18 micron technology (CPUID 068xh). This applies Celeron 533A processors. These processors support AGTL+ interface. Intel® Pentium® processor based 0.18 micron technology (CPUID 068xh). These processors support AGTL+ interface. Future 0.13 micron socket processors. These processors support AGTL interface.
82815G GMCH Datasheet
Introduction
Note: 815G chipset with universal socket compatible with Intel® Pentium® processor (CPUID 066xh) 370-pin socket. Note: 815G chipset contain design defects errors known errata, which cause product deviate from published specifications. Current characterized errata available request.
Related Documents
Document Intel® 82801BA Controller (ICH2) Intel® 82801BAM Controller (ICH2-M) Datasheet Intel® 82801AA (ICH) 82801AB (ICH0) Controller Datasheet Intel® 82802AB/82802AC Firmware (FWH) Datasheet Intel 815G Chipset Platform with Universal Socket Design Guide Intel 815EG Chipset Platform with Universal Socket Design Guide Local Specification, Revision AGTL+ Specification: Contained AP-585 Intel Pentium Processor AGTL+ Guidelines
Document Number Location 290687 290655 290658 298253 298301 www.pcisig.com 243330
Intel 815G Chipset
Figure shows typical system block diagram based 815G chipset with universal socket 370. chipset uses architecture with GMCH host bridge Controller hub. GMCH supports processor frequencies 66/100/133 MHz. Controller highly integrated providing many functions needed today's platforms; also provides interface Bus. GMCH Controller communicate over dedicated interface. Intel® 82801AA (ICH) Intel® 82801BA (ICH2) functions include: Local Specification, Revision compliant with support operations Supports Req/Gnt pairs (PCI Slots) Power management logic support Enhanced controller, interrupt controller, timer functions Integrated controller Ultra ATA/66/33 (ICH) Ultra ATA/100/66/33 (ICH2) host interface host controller supports ports (ICH) host controllers supports ports (ICH2) Integrated controller (ICH2 only) System Management (SMBus) compatible with most devices master capability ICH2 both master slave capability
82815G GMCH Datasheet
Introduction
Component Specification, Revision compliant link audio telephony codecs channels (ICH) channels (ICH2) Count (LPC) interface Firmware (FWH) interface support Alert LAN* (ICH ICH2) AOL2 (ICH2 only) Figure Intel 815G Chipset Universal Platform System Block Diagram
Intel® Pentium® Processor Intel® CeleronProcessor System (66/100/133 MHz) Digital Video Encoder
Intel® Chipset family Digital Video 82815G GMCH (Graphics Memory Controller Hub) Memory Controller
Analog Display
100/133 Only
System Memory
Connector
Display Cache SDRAM, Only)
Graphcs Controller Engine Engine Video Engine
Interface
Drives UltraATA/66/33 (ICH) UltraATA/100/66/33 (ICH2) Ports; (ICH) Ports; (ICH2) AC'97 Codec(s) (optional) AC'97 (ICH ICH2) Controller (82801AA 82801BA ICH2) (ICH ICH2)
Slots
Bridge (optional)
Slots
Keyboard, Mouse,
Super
(ICH ICH2) Agent
Connect (ICH2 only) (ICH ICH2)
GPIO
815_SysBlk
82815G GMCH Datasheet
Introduction
Intel® 82815G GMCH Overview
Figure block diagram GMCH illustrating various interfaces integrated functions. functions capabilities include: Support Single Processor Configuration 64-bit AGTL/AGTL+ based System Interface 66/100/133 32-bit Host Address Support 64-bit System Memory Interface with optimized support SDRAM 100/133 Integrated Graphics Engines Integrated Motion Compensation Engine Integrated
Integrated Digital Video Port
Display Cache
Figure Intel 82815G GMCH Block Diagram
System Interface
Display Engine
Motion Comp
Engine Engine Engine
Buffer
Analog Display
Overlay
Cursor
Digital Video DDC/ Display Cache Pins
Stretch
Memory Interface
System Memory
Digital Video Port
Local Memory Interface
Buffer
Interface
gmch_blk2.vsd
82815G GMCH Datasheet
Introduction
Host Interface
host interface GMCH optimized support Celeron processor (CPUID=068xh), Pentium processor (CPUID=068xh), future 0.13 micron socket processors. GMCH implements host address, control, data interfaces within single device. GMCH supports 4-deep in-order queue (i.e., supports pipelining four outstanding transaction requests host bus). Host addresses decoded GMCH accesses system memory, memory (via interface), configuration space Graphics memory. GMCH takes advantage pipelined addressing capability processor improve overall system performance. 82815G GMCH supports 370-pin socket processor. 370-pin socket (PGA370). PGA370 zero insertion force (ZIF) socket that processor FC-PGA FC-PGA2 package will interface with system board. Note: 815G chipset with universal socket compatible with Pentium processor (CPUID 066xh) 370-pin socket.
System Memory Interface
GMCH integrates system memory controller that supports 64-bit 100/133 SDRAM array. only DRAM type supported industry standard Synchronous DRAM (SDRAM). SDRAM controller interface fully configurable through control registers. GMCH supports industry standard 64-bit wide DIMMs with SDRAM devices. thirteen multiplexed address lines (SMAA[12:0]), along with bank select lines (SBS[1:0]), allow GMCH support 16M, DIMMs. Only asymmetric addressing supported. GMCH SCS# lines copies each electrical loading), enabling support six, 64-bit rows SDRAM. GMCH targets SDRAM with CL3, supports both single double-sided DIMMs. Additionally, GMCH also provides 1024deep refresh queue. GMCH configured keep four pages open within memory array. Pages kept open bank memory. 815G chipset supports DIMM connectors system. maximum doublesided three single-sided DIMMs populated when SDRAM interface operating MHz. Upon detection that additional rows populated beyond these configurations, BIOS must down-shift SDRAM clocks through two-wire interface system clock generator. SCKE[5:0] used configurations requiring power-down mode SDRAM.
Display Cache Interface
GMCH supports Display Cache SDRAM controller with 32-bit SDRAM array. DRAM type supported industry standard Synchronous DRAM (SDRAM) like that system memory. local memory SDRAM controller interface fully configurable through control registers.
82815G GMCH Datasheet
Introduction
Interface
interface private interconnect between GMCH Controller Hub.
Intel® 82815G GMCH Integrated Graphics Support
GMCH includes highly integrated graphics accelerator. architecture consists dedicated multi-media engines executing parallel deliver high performance motion compensation video capabilities. engines managed 3D/2D pipeline preprocessor allowing sustained flow graphics data rendered displayed. deeply pipelined accelerator engine provides graphics quality performance per-pixel rendering parallel data paths which allow each pipeline stage simultaneously operate different primitives portions same primitive. GMCH graphics accelerator engine supports perspective-correct texture mapping, trilinear anisotropic Mip-Map filtering, Gouraud shading, alpha blending, fogging Z-buffering. rich instructions permit these features independently enabled disabled. GMCH, Display Cache (DC) used Z-buffer (textures display buffer(s) located only system memory). display cache used, Z-buffer located system memory. GMCH integrated graphics accelerator's capabilities include arithmetic STRBLT engines, hardware cursor extensive registers instructions. high performance 64-bit BitBLT engine provides hardware acceleration many common Windows operations. addition 2D/3D capabilities, GMCH integrated graphics accelerator also supports full MPEG-2 motion compensation software-assisted video playback, VESA DDC2B compliant display interface digital video port which support (via external video encoder) NTSC broadcast standards (via external TMDS transmitter) digital Flat Panel Digital displays.
1.8.1
Display, Digital Video Out, LCD/Flat Panel/Digital
GMCH provides interfaces standard progressive scan monitor, TV-Out device, TMDS transmitter. These interfaces only active when running internal graphics mode. GMCH directly drives standard progressive scan monitor resolution 1600x1200 pixels. GMCH provides Digital Video interface connect external device drive 1280x1024 resolution non-scalar digital Flat Panel with appropriate EDID data digital CRTs. interface signaling allow operate higher frequencies. This interface also connect TV-Out encoder.
82815G GMCH Datasheet
Introduction
System Clocking
82815G GMCH integrated SDRAM buffers that either MHz, independent system frequency. Table lists supported system system memory frequencies. system frequency selectable between MHz, MHz, MHz. GMCH uses copy clock Clock input graphics pixel clock PLL.
Table Supported System System Memory Frequencies
Front Side Frequency System Memory Frequency Display Cache Interface Frequency DVMT DVMT DVMT DVMT
1.10
GMCH Power Delivery
82815G GMCH core voltage 1.85 System memory operates from supply. Display cache memory operates from Display Cache buffer supply power.
82815G GMCH Datasheet
Introduction
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82815G GMCH Datasheet
Signal Description
Signal Description
This section provides detailed description GMCH signals. signals arranged functional groups according their associated interface. states signals during reset provided System Reset section. symbol signal name indicates that active, asserted state occurs when signal voltage level. When present after signal name signal asserted when high voltage level. following notations used describe signal type: I/OD s/t/s As/t/s Input Output Input Open Drain Output pin. This requires pull-up Bi-directional Input/Output Sustained Tri-state. This driven inactive state prior tri-stating. Active Sustained Tri-state. This applies some interface signals. This weakly driven last driven value.
signal description also includes type buffer used particular signal: AGTL/AGTL+ CMOS LVTTL Analog Open Drain AGTL AGTL+ interface signal. Refer AGTL Specification AGTL+ Specification complete details. CMOS buffers voltage compatible signals. These only. Voltage compatible signals. There only. signals digital video interface Analog Signals
Note that processor address data signals (Host Interface) logically inverted signals (i.e., actual values inverted what appears processor bus). This must taken into account addresses data signals must inverted inside GMCH. processor control signals follow normal convention. indicates active level (low voltage) signal followed symbol indicates active level (high voltage) signal suffix.
82815G GMCH Datasheet
Signal Description
Host Interface Signals
Signal Name CPURST# Type AGTL/ AGTL+ Description Reset. GMCH asserts CPURST# while RESET# (PCIRST# from Controller Hub) asserted approximately after RESET# deasserted. GMCH also pulses CPURST# approximately when requested interface special cycle. CPURST# allows processor begin execution known state. Host Address Bus. HA[31:3]# connect processor address bus. During processor cycles, HA[31:3]# inputs. GMCH drives HA[31:3]# during snoop cycles behalf Primary PCI. Note that address inverted processor bus. Host Data. These signals connected processor data bus. Note that data signals inverted processor bus. Address Strobe. processor owner asserts ADS# indicate first cycles request phase. Block Next Request. Used block current request owner from issuing request. This signal used dynamically control processor pipeline depth. Priority Agent Request. GMCH only priority agent processor bus. asserts this signal obtain ownership address bus. This signal priority over symmetric requests will cause current symmetric owner stop issuing transactions unless HLOCK# signal asserted. Data Busy. Used data owner hold data transfers requiring more than cycle. Defer. GMCH will generate deferred response defined rules GMCH dynamic defer policy. GMCH will also DEFER# signal indicate processor retry response. Data Ready. Asserted each cycle that data transferred.
HA[31:3]#
AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+ AGTL/ AGTL+
DEFER#
DRDY#
HIT#
Hit. Indicates that caching agent holds unmodified version requested line. Also driven conjunction with HITM# target extend snoop window. Modified. Indicates that caching agent holds modified version requested line that this agent assumes responsibility providing line. HITM# also driven conjunction with HIT# extend snoop window. Host Lock. processor cycles sampled with assertion HLOCK# ADS#, until negation HLOCK# must atomic (i.e., interface GMCH graphics snoopable access SDRAM allowed when HLOCK# asserted processor).
HITM#
HLOCK#
82815G GMCH Datasheet
Signal Description
Signal Name HREQ[4:0]#
Type AGTL/ AGTL+
Description Host Request Command. Asserted during both clocks request phase. first clock, signals define transaction type level detail that sufficient begin snoop request. second clock, signals carry additional information define complete transaction type. transactions supported GMCH defined Host Interface section this document.
HTRDY#
AGTL/ AGTL+ AGTL/ AGTL+
Host Target Ready. Indicates that target processor transaction able enter data transfer phase. Response Signals. Indicates type response shown below: Idle state Retry response Deferred response Reserved (not driven GMCH) Hard Failure (not driven GMCH) data response Implicit Writeback Normal data response
RS[2:0]#
GTLREF[1:0]
Reference. Reference voltage input Host interface. GTLREF VTT. nominally 1.25 AGTL, AGTL+.
82815G GMCH Datasheet
Signal Description
System Memory Interface Signals
Signal Name SMAA[12:0] SMAB[7:4]# SMAC[7:4]# SBS[1:0] Type CMOS CMOS Description Memory Address. SMAA[12:0], SMAB[7:4]#, SMAC[7:4]# used provide multiplexed column address SDRAM. Memory Bank Select. These signals define banks that selected within each DRAM row. SMAx signals combine address every possible location within DRAM device. SBS[1:0] heavily loaded require SDRAM clock cycles setup time SDRAMs. this reason, chip select signals (SCSA[5:0]# SCSB[5:0]#) must deasserted SDRAM clock cycle that these signals change. SMD[63:0] SDQM[7:0] SCSA[5:0]# SCSB[5:0]# SRAS# SCAS# SWE# SCKE[5:0] CMOS CMOS CMOS CMOS CMOS CMOS CMOS Memory Data. These signals used interface SDRAM data bus. Input/Output Data Mask. These pins synchronized output enables during read cycles byte enables during write cycles. Chip Select. memory configured with SDRAM, these pins perform function selecting particular SDRAM components during active state. SDRAM Address Strobe. These signals drive SDRAM array directly without external buffers. SDRAM Column Address Strobe. These signals drive SDRAM array directly without external buffers. Write Enable Signal. SWE# asserted during writes SDRAM. System Memory Clock Enable. SCKE SDRAM Clock Enable used signal self-refresh power-down command SDRAM array when entering system suspend. System Memory RCOMP. Used calibrate System memory buffers. This should connected resistor tied (VSUS3.3).
SRCOMP
82815G GMCH Datasheet
Signal Description
Display Cache Interface Signals
Display Cache interface signals only function documented this section when GMCH integrated graphics enabled (GMCH interface disabled). Refer Section 2.10 multiplexing Display Cache interface signals.
Signal Name LCS#
Type CMOS CMOS
Description Chip Select. memory configured with SDRAM, this performs function selecting particular SDRAM components during active state. Input/Output Data Mask. These pins control memory array synchronized output enables during read cycles byte enables during write cycles. SDRAM Address Strobe. LRAS# signal used generate SDRAM Command encoded LRAS#/LCAS#/LWE# signals. When LRAS# sampled active rising edge SDRAM clock, address latched into SDRAMs. SDRAM Column Address Strobe. LSCAS# signal used generate SDRAM Command encoded LSRAS#/LSCAS#/LWE# signals. When LSCAS# sampled active rising edge SDRAM clock, column address latched into SDRAMs. Memory Address. LMA[11:0] used provide multiplexed column address SDRAM. Write Enable Signal. LWE# asserted during writes SDRAM. Memory Data. These signals used interface SDRAM data SDRAM array. Display Cache Frequency Select. This signal indicates whether display cache operates MHz. value this sampled deassertion CPURST# determine display cache frequency. HIGH (Default) Note: L_FSEL weak internal pull-up enabled during reset. Note: display cache non-validated feature should implemented only performs validation specifically this feature.
LDQM[3:0]
LRAS#
LCAS#
CMOS
LMA[11:0] LWE# LMD[31:0] L_FSEL
CMOS CMOS
82815G GMCH Datasheet
Signal Description
Interface Signals
Signal Name HL[10:0] HLSTRB HLSTRB# HCOMP HLREF Type Description Interface Signals. Signals used interface. Packet Strobe. differential strobe signals used transmit receive packet data. Packet Strobe Compliment. differential strobe signals used transmit receive packet data. Compensation Pad. Used calibrate interface buffers. This should connected resistor tied (VSUS_1.8) Reference. Sets differential voltage reference interface.
Display Interface Signals
Signal Name VSYNC HSYNC IWASTE IREF Type Analog Analog Analog CMOS Description Vertical Synchronization. This signal used vertical sync (polarity programmable) Vsync Interval". Horizontal Synchronization. This signal used horizontal sync (polarity programmable) Hsync Interval". Waste Reference. This signal must tied ground. Reference. pointer resistor internal color palette DAC. Analog Video Output from internal color palette DAC. designed 37.5 equivalent load each (e.g., resistor board, parallel with load) Analog video output from internal color palette DAC. designed 37.5 equivalent load each (e.g., resistor board, parallel with load) Analog video output from internal color palette DAC. designed 37.5 equivalent load each (e.g., resistor board, parallel with load) Monitor Interface Clock. (Also referred VESA* "Display Data Channel", also referred "Monitor Plug-n-Play" interface.) DDC1, DDCK DDDA provide unidirectional channel Extended Display DDC2, DDCK DDDA used establish bidirectional channel based protocol. host request Extended Display Video Display Interface information over DDC2 channel. Monitor Interface Data. DDCK Description
GREEN
BLUE
DDCK
DDDA
CMOS
82815G GMCH Datasheet
Signal Description
Digital Video Output Signals/TV-Out Pins
Signal Name TVCLKIN/INT# Type Description Voltage Clock (TV-Out Mode). TV-Out usage, TVCLKIN functions pixel clock input GMCH from encoder. TVCLKIN frequency ranges from depending mode (e.g., NTSC PAL) overscan compensation values Encoder. CLKIN worse case duty cycle 60%/40% coming GMCH. Flat Panel Interrupt (LCD Mode). Flat Panel usage, INT# asserted cause interrupt (typically, indicate plug unplug flat panel). Flat Panel usage, this connected internally pull-up resistor. LTVCLKOUT[1:0] LCD/TV Port Clock Out: These pins provide differential pair reference clock that MHz. Note: always recommended that these pins used differential pair. Devices running frequencies less than operate single-ended clock mode LTVCLKOUT[0] clock. When operating single-ended clock mode, LTVCLKOUT[1] used. LTVBLANK# Flicker Blank Border Period Indication. BLANK# programmable output driven graphics control. When programmed blank period indication, this indicates active pixels excluding border. When programmed border period indication, this indicates active pixel including border pixels. LCD/TV Data. These signals used interface LCD/TV-Out data bus. Vertical Sync. VSYNC signal interface. active polarity signal programmable. Horizontal Sync. HSYNC signal interface. active polarity signal programmable. LCD/TV Clock. Clock 2-wire interface. LCD/TV Data. Data 2-wire interface.
LTVDATA[11:0] LTVVSYNC LTVHSYNC LTVCK LTVDA
I/OD CMOS I/OD CMOS
82815G GMCH Datasheet
Signal Description
Power Signals
Signal Name V1.8 VDDQ VSUS3.3 VCCDA VCCDACA1 VCCBA VCCDACA2 VCCDPLL VSSDA VSSDACA VSSDPLL VSSBA Type Power Power Power Power Power Power Power Power Power Power Power Power Power Core Power (1.85 Display Cache Buffer Supply Power System Memory Buffer Power (Separate power plane power-down modes) Display Power Signal (Connect isolated 1.85 plane with VCCDACA1 VCCDACA2) Display Power Signal Power (1.85 Display Power Signal System Memory Power (1.85 Display Ground Signal Display Ground Signal Core Ground System Memory Ground AGP/Hub Ground Description
Clock Signals
Signal Name HCLK SCLK LTCLK[1:0] LOCLK LRCLK DCLKREF HLCLK RESET# Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS Description Host Clock Input. Clock used host interface. Externally generated 66/100/133 clock. System Memory Clock. Clock used output buffers system memory. Externally generated 100/133 clock. Display Cache Transmit Clocks. LTCLK[1:0] internally generated display cache clocks used clock input buffers SDRAM devices. Output Clock. LOCLK internally generated clock used drive LRCLK. Receive Clock. LRCLK display cache clock used clock input buffers GMCH. Display Interface Clock. DCLKREF clock generated external clock synthesizer GMCH. Interface Clock. interface clock generated external clock synthesizer. Global Reset. Driven Controller when PCIRST# active.
82815G GMCH Datasheet
Signal Description
GMCH Power-Up/Reset Strap Options
Name SBA[7] Strap Description Local Memory Frequency Select Host Frequency Host Frequency Processor Select Configuration High (default) High (default) High (default) High Intel® Pentium® processor (CPUID=068xh) Intel® Celeronprocessor (CPUID=068xh) (default) Low= future 0.13 micron socket processors SMAA[11] SMAA[10] SMAA[9] Depth P-MOS Kicker Enable High (default) High Normal (default) High enabled (future 0.13 micron socket processors) (default) disabled (Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh)) SRAS# Test mode High Normal (default) test mode System Memory Bi-directional System Memory System Memory System Memory Bi-directional Bi-directional Bi-directional Interface Type AGP/LM Buffer Type Input
SCAS# SWE# SMAA[12]
System Memory System Memory System Memory
Bi-directional Bi-directional Bi-directional
NOTES: normal operation, strap pins must high (except Depth, Host Frequency, Processor Select straps, P-MOS Kicker Enable which should appropriately). External reset signal used sample straps RESET#. system memory reset straps have internal pull-ups during reset. Refer Intel® Chipset Platform with Universal Socket Design Guide more details processor select.
82815G GMCH Datasheet
Signal Description
2.10
Intel® 815G Display Cache Intel® Signal Mapping
following list provided show local memory signal name 815G signal name devices. With disabled 815G, there longer signal MUXing between display cache signals signals. GMCH pinout figure Alphabetical Assignment, Table Chapter this document will continue signal name rather than 815G local memory signal name, since that other documentation refers names
Local Memory Signal Name 815G LCAS# LCS# LDQM0 LDQM1 LDQM2 LDQM3 L_FSEL LMA0 LMA1 LMA10 LMA11/LBA LMA2 LMA3 LMA4 LMA5 LMA6 LMA7 LMA8 LMA9 LMD0 LMD1 LMD10 LMD11 LMD12 LMD13 LMD14 LMD15 LMD16 LMD17
Signal Name G_AD26 G_STOP# G_AD0 G_AD10 SBA2 SBA7 G_AD22 G_AD15 G_FRAME# G_AD18 G_AD11 G_BE0# G_AD9 G_AD13 G_PAR G_TRDY# G_AD16 G_AD20 G_AD8 G_AD7 G_C/BE1# G_DEVSEL# G_IRDY# G_C/BE2# G_AD17 G_AD19 G_AD21 G_AD23
Local Memory Signal Name 815G LMD18 LMD19 LMD2 LMD20 LMD21 LMD22 LMD23 LMD24 LMD25 LMD26 LMD27 LMD28 LMD29 LMD3 LMD30 LMD31 LMD4 LMD5 LMD6 LMD7 LMD8 LMD9 LRAS# LTCLK0 LTCLK1 LWE#
Signal Name G_AD25 G_AD27 G_AD5 G_AD29 G_AD31 SBA6 SBA4 PIPE# SBA1 SBA3 G_REQ# G_AD3 RBF# SBA0 G_AD1 G_AD6 G_AD4 G_AD2 G_AD12 G_AD14 G_C/BE3# G_AD30 G_AD28 SBA5
82815G GMCH Datasheet
Signal Description
2.11
Display Cache Mapping Connector
mapping assignments were made with primary goal optimizing layout AIMM card (Display Cache add-in card that fits connector). This done based signals they exist standard connector. Care taken avoid special types signals such strobes open-drain signals. Some signals that exist connector that exist GMCH's interface could used Display Cache signals.
OVRCNT# USB+ INTB# REQ# LGM_OK VCC3.3 LGM_OK LGM_OK RBF# LGM_OK Reserved SBA0 LGM_OK VCC3.3 SBA2 LGM_OK SB_STB SBA4 LGM_OK SBA6 LGM_OK Reserved 3.3Vaux VCC3.3 AD31 LGM_OK AD29 LGM_OK VCC3.3 AD27 LGM_OK LMD19 LMD21 LMD20 LMD23 LMD22 LDQM2 LMD31 LMD28 LMD29 LMD30 LMD27 Display Cache Signal TYPEDET# Reserved USBGND INTA# RST# GNT# VCC3.3 LGM_OK Reserved PIPE# LGM_OK WBF# SBA1 LGM_OK VCC3.3 SBA3 LGM_OK SB_STB# SBA5 LGM_OK SBA7 LGM_OK Reserved Reserved VCC3.3 AD30 LGM_OK AD28 LGM_OK VCC3.3 AD26 LGM_OK LCAS# LTCLK0 LTCLK1 LWE# L_FSEL LMD26 LMD25 LMD24 LDQM3 Display Cache Signal
82815G GMCH Datasheet
Signal Description
AD25 LGM_OK AD_STB1 AD23 LGM_OK VDDQ AD21 LGM_OK AD19 LGM_OK AD17 LGM_OK C/BE2# LGM_OK VDDQ IRDY# LGM_OK 3.3Vaux Reserved VCC3.3 DEVSEL# LGM_OK VDDQ PERR# SERR# C/BE1# LGM_OK VDDQ AD14 LGM_OK AD12 LGM_OK AD10 LGM_OK LGM_OK VDDQ AD_STB0 LGM_OK LGM_OK LGM_OK VDDQ LGM_OK Vrefcg
Display Cache Signal LMD18
AD24 LGM_OK
Display Cache Signal LCKE
LMD17 LMD16 LMD15 LMD14 LMD13 LMD12 LMD11 LMD10 LMD9 LMD8 LDQM1 LMD0 LMD1 LMD2 LMD3 LMD4
AD_STB1# C/BE3# LGM_OK VDDQ AD22 LGM_OK AD20 LGM_OK AD18 LGM_OK AD16 LGM_OK VDDQ FRAME# LGM_OK Reserved Reserved VCC3.3 TRDY# LGM_OK STOP# LGM_OK PME# LGM_OK AD15 LGM_OK VDDQ AD13 LGM_OK AD11 LGM_OK LGM_OK C/BE0# LGM_OK VDDQ AD_STB0# LGM_OK LGM_OK LGM_OK VDDQ LGM_OK Vrefgc
LRAS# LMA0 LMA9 LMA11 LMA8 LMA10 LMA7 LCS# LMA6 LMA1 LMA5 LMA2 LMA4 LMA3 LMD5 LMD6 LMD7 LDQM0
82815G GMCH Datasheet
Signal Description
2.12
Intel® Intel® 815G Signal Name Changes
Intel 82815G pins associated with signals have name changes. following table shows 82815 signal name, ball number, 82815G signal name. designs 815G boards should pull-ups pull-downs indicated 815G signal name. boards using 815G devices leave associated pins original configuration.
Table Intel 82815 Intel 82815G Name Change
Intel® Signal Name WBF# AD_STB0 AD_STB0# AD_STB1 AD_STB1# SB_STB SB_STB# GRCOMP AGPREF G_GNT# G_AD[24] Ball# AB24 AA24 AD25 Intel® 815G Signal Name PD40 0.5VDDQ
NOTES: Connect. These pins should float Pull through weak pull-up resistor. (8.2 resistor.) Pull-Down. These pins should pulled down ground through weak pull-down resistor. (8.2 resistor.) PD40 Pull-Down using resistor. 0.5VDDQ VDDQ voltage supply level.
82815G GMCH Datasheet
Signal Description
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82815G GMCH Datasheet
Configuration Registers
Configuration Registers
This chapter describes following register sets: Configuration Registers. GMCH contains configuration registers Device (Host-hub interface Bridge/DRAM Controller), Device (AGP Bridge), Device (GMCH internal graphics device). Note: functionality been removed from 82815G GMCH. Display Cache Interface Registers. This register used configuration Display Cache (DC) interface. registers located memory space. memory space addresses listed offsets from base memory address programmed into MMADR register (Device configuration offset 14h). Note: functionality been removed from 82815G GMCH. Display Cache Detect Diagnostic Registers. This register used memory detection testing. These registers accessed either space memory space. memory space addresses listed offsets from base memory address programmed into MMADR register (Device configuration offset 14h). Note: functionality been removed from 82815G GMCH. Note that GMCH also contains extensive registers instructions controlling graphics operations. Intel graphics drivers provide software interface this architectural level. register/instruction interface transparent Application Programmers Interface (API) level thus, beyond scope this document.
Register Nomenclature Access Attributes
Mnemonic R/WC R/WO Reserved Bits Description Read-Only. register read-only, writes this register have effect. Read/Write. register with this attribute read written Read/Write Clear. register with this attribute read written. However, write clears (sets corresponding write effect. Read/Write-Once. register with this attribute written only once after power After first write, becomes read-only. Some GMCH registers described this section contain reserved bits. These bits labeled "Reserved" "Intel Reserved". Software must deal correctly with fields that reserved. reads, software must appropriate masks extract defined bits rely reserved bits being particular value. writes, software must ensure that values reserved positions preserved. That values reserved positions must first read, merged with values other positions then written back. Note that software does need perform read, merge, write operations configuration address register. addition reserved bits within register, GMCH contains address locations configuration space Host-hub interface Bridge/DRAM Controller internal graphics device entities that marked either "Reserved" Intel Reserved". When "Reserved" register location read, random value returned. ("Reserved" registers 16-, 32-bit size). Registers that marked "Reserved" must modified system software. Writes "Reserved" registers cause system failure.
Reserved Registers
82815G GMCH Datasheet
Configuration Registers
Mnemonic Default Value Upon Reset
Description Upon Full Reset, GMCH sets internal configuration registers predetermined default states. Some register values reset determined external strapping options. default state represents minimum functionality feature required successfully bring system. Hence, does represent optimal system configuration. responsibility system initialization software (usually BIOS) properly determine DRAM configurations, operating parameters, optional system features that applicable, program GMCH registers accordingly.
Configuration Space Access
GMCH Controller physically connected interface. From configuration standpoint, interface connecting GMCH Controller logically devices internal GMCH Controller appear system primary expansion physically attached Controller and, from configuration standpoint, appears hierarchical behind PCI-to-PCI bridge. primary expansion connected Controller programmable number. Note: Even though primary expansion referred PCI0 this document from configuration standpoint. GMCH contains three devices within single physical component. configuration registers Devices mapped devices residing Device Host-hub interface Bridge/DRAM Controller. Logically this appears device residing Physically, Device contains registers, DRAM registers, other GMCH specific registers. Device Bridge supporting 1X/2X/4X transactions. Logically this appears device residing Note: functionality been removed from 82815G GMCH. Device GMCH internal graphics device. These registers contain registers GMCH internal graphics device. Logically this appears device residing Note: physical does exist. interface internal devices GMCH Controller logically constitute configuration software.
3.2.1
Configuration Mechanism
defines slot based "configuration space" that allows each device contain eight functions with each function containing 256, 8-bit configuration registers. specification defines cycles access configuration space: Configuration Read Configuration Write. Memory spaces supported directly processor. Configuration space supported mapping mechanism implemented within GMCH. specification defines mechanisms access configuration space, Mechanism Mechanism
82815G GMCH Datasheet
Configuration Registers
GMCH Supports Only Mechanism
configuration access mechanism makes CONF_ADDR Register CONF_DATA Register. reference configuration register DWord write cycle used place value into CONF_ADDR that specifies bus, device that bus, function within device, specific configuration register device function being accessed. CONF_ADDR[31] must enable configuration cycle. CONF_DATA then becomes window into four bytes configuration space specified contents CONF_ADDR. read write CONF_DATA results GMCH translating CONF_ADDR into appropriate configuration cycle. GMCH responsible translating routing processor accesses CONF_ADDR CONF_DATA registers internal GMCH configuration registers, internal graphic device, interface.
3.2.2
Logical Configuration Mechanism
GMCH decodes Number (bits 23:16) Device Number fields CONF_ADDR register. Number field CONF_ADDR configuration cycle targeting device. Device Host-hub interface Bridge/DRAM Controller entity within GMCH hardwired Device Device interface entity within GMCH hardwired Device Note: functionality been removed from 82815G GMCH. Device internal graphics device entity within GMCH hardwired Device Note: Configuration cycles GMCH internal devices confined GMCH sent over interface. Note that accesses devices forwarded over interface.
3.2.3
Primary (PCI0) Downstream Configuration Mechanism
Number CONF_ADDR non-zero, GMCH generates configuration cycle over interface. Controller compares non-zero Number with Secondary Number Subordinate Number registers bridges determine configuration cycle meant Primary expansion (PCI0), downstream bus.
3.2.4
Internal Graphics Device Configuration Mechanism
From chipset configuration perspective, internal graphics device seen device (device Configuration cycles that target device claimed internal graphics device forwarded interface Controller Hub.
82815G GMCH Datasheet
Configuration Registers
3.2.5
GMCH Register Introduction
GMCH contains sets software accessible registers, accessed Host address space: Control registers mapped into host space that control access configuration space (see section entitled Mapped Registers) Internal configuration registers residing within GMCH partitioned into three logical device register sets ("logical" since they reside within single physical device). first register dedicated Host-hub interface Bridge/DRAM Controller functionality (controls such DRAM configuration, other chip-set operating parameters, optional features). second register block dedicated interface third block dedicated internal graphics device GMCH. Note: functionality been removed from 82815G GMCH. GMCH supports configuration space accesses using mechanism denoted Configuration Mechanism specification. GMCH internal registers (both Mapped Configuration registers) accessible host. registers accessed Byte, Word (16-bit), DWord (32-bit) quantities, with exception CONF_ADDR, which only accessed DWord. multi-byte numeric fields "little-endian" ordering (i.e., lower addresses contain least significant parts field).
Mapped Registers
GMCH contains registers that reside processor address space Configuration Address (CONF_ADDR) Register Configuration Data (CONF_DATA) Register. Configuration Address Register enables/disables configuration space determines what portion configuration space visible through Configuration Data window.
3.3.1
CONF_ADDR-Configuration Address Register
Address: Default Value: Access: Size: 0CF8h Accessed DWord 00000000h Read/Write bits
CONF_ADDR 32-bit register accessed only when referenced DWord. Byte Word reference will "pass through" Configuration Address Register onto PCI0 cycle. CONF_ADDR register contains Number, Device Number, Function Number, Register Number which subsequent configuration access intended.
82815G GMCH Datasheet
Configuration Registers
CFGE
Reserved Function Number
Number
Register Number
Reserved
Device Number
Descriptions Configuration Enable (CFGE). This enables/disables accesses configuration space. Disable. Enabled.
30:24 23:16
Reserved. These bits read-only have value Number. When Number programmed target Configuration Cycle three devices GMCH (the interface logically bus) that directly connected GMCH, depending Device Number field. type Configuration Cycle generated interface Number programmed GMCH target. Number non-zero matches value programmed into Secondary Number Register Type configuration cycle will generated bridge. Number non-zero, greater than value Secondary Number Register (Device less than equal value programmed into Subordinate Number Register (Device Type configuration cycle will generated bridge. Number non-zero, less than value programmed into Secondary Number greater than value programmed into Subordinate Number Register Type interface configuration cycle generated.
15:11
Device Number. This field selects agent selected Number. During Type Configuration cycle, this field mapped AD[15:11]. During Type Configuration Cycle, this field decoded among AD[31:11] driven GMCH always Device Number Host bridge (GMCH) entity, Device Number bridge entity, Device Number Internal Graphics Device entity. Number non-zero matches value programmed into Secondary Number Register, Type configuration cycle generated bridge. Device Number field decoded GMCH asserts only GADxx signal IDSEL. GAD16 asserted access Device GAD17 Device GAD18 Device forth Device which asserts AD31. device numbers higher than cause type configuration access with IDSEL asserted, which results Master Abort reported GMCH's "virtual" PCI-PCI bridge registers. Numbers resulting interface configuration cycles GMCH propagates Device Number field A[15:11]. Numbers resulting bridge Type Configuration cycles Device Number propagated GAD[15:11].
10:8
Function Number. This field mapped AD[10:8] during PCIx configuration cycles. This allows configuration registers particular function multi-function device accessed. GMCH only responds configuration cycles with function number 000b; other function number values attempting access GMCH (Device Number Number will generate master abort. Register Number. This field selects register within particular Bus, Device, Function specified other fields Configuration Address Register. This field mapped AD[7:2] during configuration cycles. Reserved.
82815G GMCH Datasheet
Configuration Registers
3.3.2
CONF_DATA-Configuration Data Register
Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write bits
CONF_DATA 32-bit read/write window into configuration space. portion configuration space that referenced CONF_DATA determined contents CONF_ADDR.
31:0 Descriptions Configuration Data Window (CDW). CONF_ADDR reference that falls CONF_DATA space mapped configuration space using contents CONF_ADDR.
82815G GMCH Datasheet
Configuration Registers
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device
Table shows GMCH configuration space device Note: functionality been removed from 82815G GMCH.
Table GMCH Configuration Space (Device
Address Offset 00-01h 02-03h 04-05h 06-07h 10-13h Mnemonic PCICMD PCISTS SUBC APBASE Register Name Vendor Identification Device Identification Command Status Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Reserved Aperture Base Configuration Default Value 8086h 1130h 0006h 0090h (AGP) 0080h (GFX) 00000008h (AGP) 00000000h (GFX) 0000h 0000h (GFX) (AGP) Access R/WC R/W,
14-2Bh 2C-2Dh 2E-2Fh 30-33h 35-4Fh
SVID CAPPTR GMCHCFG APCONT DRAMT DRP2
Reserved Subsystem Vendor Identification Subsystem Identification Reserved Capabilities Pointer Reserved GMCH Configuration Aperture Control DRAM Population DRAM Timing Register DRAM Population Register
R/WO R/WO R/WO/RO
82815G GMCH Datasheet
Configuration Registers
Address Offset 55-57h 59-5Fh 60-6Fh 72-73h 74-87h 88-8Bh 8C-91h 92-93h 94-95h 96-9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B5-B7h B8-BBh BF-CAh CC-FFh
Mnemonic FDHC SMRAM MISCC CAPID BUFF_SC BUFF_SC2 ACAPID AGPSTAT AGPCMD AGPCTRL APSIZE ATTBASE AMTT LPTT MCHCFG ERRCMD
Register Name Reserved Fixed DRAM Hole Control Programmable Attributes Registers Reserved System Management Control Reserved Miscellaneous Control Register Reserved Capability Identification Reserved Buffer Strength Control Buffer Strength Control Reserved Capability Identifier Status Command Reserved Control Aperture Size Reserved Aperture Translation Table Base Multi-Transaction Timer Priority Transaction Timer Configuration Reserved Error Command Reserved
Default Value 0000h F104A009h FFFFh FFFFh 00200002h 1F000207h 00000000h 00000000h 00000000h 0000 x000b
Access R/W, R/W,
82815G GMCH Datasheet
Configuration Registers
3.4.1
VID-Vendor Identification Register (Device
Address Offset: Default Value: Attribute: Size: 00-01h 8086h Read-Only bits
Register contains vendor identification number. This 16-bit register combined with Device Identification Register uniquely identifies device. Writes this register have effect.
15:0 Description Vendor Identification Number. This 16-bit value assigned Intel. Intel 8086h.
3.4.2
DID-Device Identification Register (Device
Address Offset: Default Value: Attribute: Size: 02-03h 1130h Read-Only bits
This 16-bit register combined with Vendor Identification register uniquely identifies device. Writes this register have effect.
15:0 Description Device Identification Number. This value assigned GMCH Host-Hub Interface Bridge DRAM Controller Device 1130h Device Device
82815G GMCH Datasheet
Configuration Registers
3.4.3
PCICMD-PCI Command Register (Device
Address Offset: Default: Access: Size: 04-05h 0006h Read/Write bits
This register provides basic control over PCI0 interface (hub interface) ability respond cycles. PCICMD Register enables disables SERR# signal, parity checking (PERR# signal), GMCH's response special cycles, enables disables PCI0 master accesses main memory.
Reserved FB2B (Not Impl) SERR
Addr/Data Stepping (Not Impl)
Parity Error (Not Impl)
(Not Impl)
Inval (Not Impl)
Special Cycle (Not Impl)
Master (Not Impl)
(Not Impl)
(Not Impl)
15:10 Reserved.
Descriptions
Fast Back-to-Back. (Not implemented). Hardwired Selects whether GMCH generate fast back-to-back transactions different targets. SERR Enable (SERRE). This global enable Device SERR messaging. GMCH does have SERR# signal. GMCH communicates SERR# condition sending SERR message Controller Hub. Disable. SERR message generated GMCH Device Enable. GMCH enabled generate SERR messages over interface specific Device error conditions Note: This only controls SERR messaging Device Device SERRE control error reporting error conditions occurring Device control bits used logical manner enable SERR interface message mechanism. Address/Data Stepping. (Not implemented). Hardwired Parity Error Enable (PERRE). (Not implemented). Hardwired PERR# implemented GMCH. Writes this position have affect. Palette Snoop. (Not implemented). Hardwired Writes this position have affect. Memory Write Invalidate Enable. GMCH will never this command this hardwired Writes this position will have affects. Special Cycle Enable. (Not implemented). Hardwired GMCH ignores special cycles generated PCI. Master Enable (BME). (Not implemented). Hardwired GMCH always allowed Master. Writes this position have affect. Memory Access Enable (MAE). (Not implemented). Hardwired GMCH always allows access main memory. Writes this position have affect. Access Enable (IOAE). (Not implemented). Hardwired Writes this position have affect.
82815G GMCH Datasheet
Configuration Registers
3.4.4
PCISTS-PCI Status Register (Device
Address Offset: Default Value: Access: Size: 06-07h 0090h Read-Only, Read/Write Clear bits
PCISTS 16-bit status register that reports occurrence master abort target abort PCI0 bus. PCISTS also indicates DEVSEL# timing that been GMCH hardware target responses PCI0 bus. Bits [15:12] read/write clear bits [10:9] read-only.
Detected Error (HW=0) Error Recog Mast Abort Target Abort Target Abort (HW=0) DEVSEL# Timing (HW=00) Data Detected (HW=0)
FB2B (HW=1)
Reserved
List (HW=1)
Reserved
Descriptions Detected Parity Error (DPE). This hardwired Writes this position have affect. Signaled System Error (SSE). Software sets writing this bit. GMCH Device generates SERR message over interface enabled Device error condition. Device error conditions enabled PCICMD register. Device error flags read/reset from PCISTS register.
Received Master Abort Status (RMAS). Software clears this writing GMCH generates interface request that receives Master Abort completion packet.
Received Target Abort Status (RTAS). Software clears this writing GMCH generates interface request that receives Target Abort completion packet.
10:9
Signaled Target Abort Status (STAS). (Not implemented). Hardwired Writes this position have affect. DEVSEL# Timing (DEVT). These bits hardwired Writes these positions have affect. Device does physically connect PCI0. These bits (fast decode) that optimum DEVSEL timing PCI0 limited GMCH. Data Parity Detected (DPD). This hardwired Writes this position have affect. Fast Back-to-Back (FB2B). This hardwired Writes these positions have affect. Device does physically connect PCI. This (indicating fast back-toback capability) that optimum setting limited GMCH. Reserved.
82815G GMCH Datasheet
Configuration Registers
Descriptions Capability List (CLIST). This hardwired indicate that GMCH always capability list. list capabilities accessed register CAPPTR configuration address offset 34h. Register CAPPTR contains offset pointing address first linked list capability registers. Writes this position have affect. Reserved.
3.4.5
RID-Revision Identification Register (Device
Address Offset: Default Value: Access: Size: Read-Only bits
This register contains revision number Device These bits read-only writes this register have effect.
Description Revision Identification Number. This 8-bit value that indicates revision identification number Device Stepping
3.4.6
SUBC-Sub-Class Code Register (Device
Address Offset: Default Value: Access: Size: Read-Only bits
This register contains Sub-Class Code GMCH Function register read-only.
Description Sub-Class Code (SUBC). This 8-bit value that indicates category Bridge into which GMCH falls. Host Bridge.
82815G GMCH Datasheet
Configuration Registers
3.4.7
BCC-Base Class Code Register (Device
Address Offset: Default Value: Access: Size: Read-Only bits
This register contains Base Class Code GMCH Function This register read-only.
Description Base Class Code (BASEC). This 8-bit value that indicates Base Class Code GMCH. Bridge device.
3.4.8
MLT-Master Latency Timer Register (Device
Address Offset: Default Value: Access: Size: Read-Only bits
Device master; therefore, this register implemented.
Descriptions Master Latency Timer Value. This read-only field always returns when read writes have affect.
3.4.9
HDR-Header Type Register (Device
Address Offset: Default: Access: Size: Read-Only bits
This register identifies header layout configuration space. physical register exists this location.
Descriptions Header Type. This read-only field always returns when read writes have affect.
82815G GMCH Datasheet
Configuration Registers
3.4.10
APBASE-Aperture Base Configuration Register (Device Mode Only)
Address Offset: Default Value (AGP Mode): Default Value (GFX Mode): Access: Size: 10-3h 00000008h 00000000h Read/Write, Read-Only bits
APBASE standard Base Address register that used base aperture. standard Configuration mechanism defines base address configuration register such that only fixed amount space requested (dependent which bits hardwired behave hardwired "0"). allow flexibility aperture) additional register called APSIZE used "back-end" register control which bits APBASE will behave hardwired "0". This register programmed GMCH specific BIOS code that runs before generic configuration software run. Note: APCONT register used prevent accesses aperture range before configuration software initializes this register appropriate translation table structure been established main memory.
82815G GMCH Datasheet
Configuration Registers
Upper Prog. Base Address Bits
Lower "HW"/Prog Base Address
Hardwired
Hardwired
Prefetch able
Type
Space Indicator
31:26
Description Upper Programmable Base Address bits-R/W. These bits used locate range size selected lower bits 25:4. Default 0000
Lower "Hardwired"/Programmable Base Address bit. This behaves "hardwired" programmable depending contents APSIZE register defined below: Aperture Size Aperture Size (default) controlled APSIZE register following manner: APSIZE[3]=0 (indicating 64-MB aperture size), then APBASE[25]=0. APSIZE[3]=1, then APBASE[25]=r/w (read/write) allowing 32-MB aperture size desired. Default APSIZE[3]=0b forces default APBASE[25] (bit responds "hardwired" This provides default maximum aperture size GMCH specific BIOS responsible selecting smaller size required) before configuration software runs establishes system address map.
24:4
Hardwired This forces minimum aperture size selected this register Prefetchable-RO. This hardwired identify Graphics Aperture range prefetchable (i.e., There side effects reads, device returns bytes reads regardless byte enables, GMCH merge processor writes into this range without causing errors). Type-RO. These bits determine addressing type they hardwired indicate that address range defined upper bits this register located anywhere 32-bit address space. Memory Space Indicator-RO. Hardwired identify aperture range memory range.
82815G GMCH Datasheet
Configuration Registers
3.4.11
SVID-Subsystem Vendor Identification Register (Device
Address Offset: Default: Access: Size:
15:0
2C-2Dh 0000h Read/Write-Once bits
Description
Subsystem Vendor ID-R/WO. This value used identify vendor subsystem. default value 0000h. This field should programmed BIOS during boot-up. Once written, this register becomes read-only. This Register only cleared Reset.
3.4.12
SID-Subsystem Identification Register (Device
Address Offset: Default: Access: Size:
15:0
2E-2Fh 0000h Read/Write-Once bits
Description
Subsystem ID-R/WO. This value used identify particular subsystem. default value 0000h. This field should programmed BIOS during boot-up. Once written, this register becomes read-only. This Register only cleared Reset.
3.4.13
CAPPTR-Capabilities Pointer (Device
Address Offset: Default Value: Access: Size: Read-Only bits
CAPPTR provides offset that pointer location where capability identification register located.
Pointer Start CAPPTR Linked List. Points CAPID register that provides capability information regarding GMCH. capabilities determined which fuses blown. Description
82815G GMCH Datasheet
Configuration Registers
3.4.14
GMCHCFG-GMCH Configuration Register (Device
Address Offset: Default: Access: Size:
Enable Latency Timer Reserved
01ss0s00 Read/Write, Read-Only bits
Local Memory Frequency Select DRAM Page Closing Policy System Memory Frequency Select Reserved
Description Memory Arbiter Grant Window Enable (MAGWE). This controls Host Priority Graphics timeslice regulation arbiter System DRAM. pre-arbitration (a.k.a., stage Disabled. Enforce fixed priority. Limit grant host-to-graphics stream consecutive packets. main-arbitration (a.k.a., stage Disabled. Enforce fixed priority. clocks limiting host, clocks guaranteed priority graphics stream. fixed mode arbitration (MAGWE=0) host stream always higher priority over priority graphics stream accesses system memory. timeslice mode, host stream priority graphics stream both regulated time window provide fairness graphics stream. Fixed priority mode, where host stream always favored, recommended mode operation; this setting gives highest system performance without adversely affecting graphics performance under real life applications workload.
(CPU Latency Timer). Deferrable processor cycle will Deferred immediately after receiving another ADS# Deferrable processor cycle will only Deferred after been held "Snoop Stall" clocks another ADS# arrived (default).
Reserved. Local Memory Frequency Select (LMFS). This selects operating frequency Local Memory Controller. Default sampling LM_FREQ_SEL strap (AGP SBA[7] pin) reset. weak internal pull-up enabled during reset. This reserved Only Internal Graphics SKUs. read back these SKUs. output register these SKUs also forced such that customer cannot effectively program part local memory. Fully-Featured SKUs, either programmed customer. MHz. This reflection LM_FREQ_SEL strap being pulled down. MHz, (default). This reflection LM_FREQ_SEL strap being pulled (default). Note: value this should only changed when Internal Graphics device disabled (i.e., 00).
82815G GMCH Datasheet
Configuration Registers
Description DRAM Page Closing Policy (DPCP). When this GMCH will tend leave DRAM pages open. this mode only times that GMCH will close memory pages are: Precharge Bank during service "Page Miss" access. Precharge when changing from another Pages open. Precharge leadin Refresh operation When this GMCH will tend leave DRAM pages closed. this GMCH will: Precharge during service "Page Miss" access. Precharge when changing from another Pages open. Precharge leadin Refresh operation.
System Memory Frequency Select (SMFS). This selects operating frequency main system memory. Default sampling SBS0# reset. MHz. MHz. default determined SBS0# reset strap.
Reserved.
82815G GMCH Datasheet
Configuration Registers
3.4.15
APCONT-Aperture Control (Device
Address Offset: Default Value: Access: Size: Read/Write, Write-Once, Read-Only bits
Aperture Control Register controls selection access aperture space. Note: functionality been removed from 82815G GMCH.
Reserved Select Lock Aperture Access Global Select
Reserved.
Description
Select Lock-WO. This Select (bit made read-only this bit. This write-once bit. After written, this cannot changed without system reset. Select remains writeable. Select read-only.
Aperture Access Global Enable-R/W. This used prevent access aperture from port (processor, PCI0, AGP/PCI1) before aperture range established configuration software, appropriate translation table main DRAM been initialized. must after system fully configured aperture accesses. Default Select-R/W. This field selects graphics device either Internal Graphics (GFX). Mode. interface device enabled. registers device device visible. device registers visible; reads from those addresses return Mode. Internal Graphics device enabled. non-AGP related device registers device registers visible. device registers visible; reads from those addresses return Reads from related device registers return internal graphics device does respond configuration cycles unless SMRAM[7:6] 70h) APCONT[0] 51h) R/W, Select Lock (bit Select must programmed before other access made configuration space. possible modes mutually exclusive. This determines whether other configuration registers enabled disabled. This must part initialization sequence.
82815G GMCH Datasheet
Configuration Registers
3.4.16
DRP-DRAM Population Register (Device
Address Offset: Default Value: Access: Size: Read/Write (Read-Only D_LCK bits
GMCH supports physical rows DRAM DIMMs. width bits. DRAM Population Register defines population each side each DIMM. Note that this entire register becomes read-only when D_LCK D_LCK description, SMRAM register (Device address offset 70h). system memory interface configured MHz, system BIOS must register (offset 52h) along with DRP2 register (offset 52h) detect whether memory configuration exceeds double-sided DIMMs three single-sided DIMMs. system BIOS must down-shift clock generator guarantee electrical integrity timings.
DIMM Population Description DIMM Population. This field indicates population DIMM (See Table DIMM Population. This field indicates population DIMM (See Table DIMM Population
Table Supported System Memory DIMM Configurations
Register Code DIMM Capacity Devices DIMM Sides DRAM Tech. Front Side Population Count 64/16 128/64 128/64 844484848484888488Config Empty 8Back Side Population Count Config Empty 44844 48848 10/9 10/9 Bank Column
82815G GMCH Datasheet
Configuration Registers
3.4.17
DRAMT-DRAM Timing Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This register controls operating mode timing DRAM Controller.
SDRAM Mode Select DRAM Cycle Time Host Aperture Cycle Queue Slot CAS# Latency SDRAM RAS# CAS# SDRAM RAS# Precharge
Description SDRAM Mode Select (SMS). These bits select operational mode GMCH DRAM interface. special modes intended initialization power DRAM Self-Refresh Mode, Refresh Disabled (Default) Normal Operation, system memory Refresh interval 15.6 system memory Refresh interval 11.7 Normal Operation, system memory Refresh interval system memory Refresh interval 5.85 Normal Operation, system memory Refresh interval 1.28 system memory Refresh interval 0.96 Command Enable. this mode processor cycles SDRAM result Command SDRAM interface. Banks Precharge Enable. this mode processor cycles SDRAM result Banks Precharge Command SDRAM interface. Mode Register Enable. this mode processor cycles SDRAM result mode register command SDRAM interface. Command driven MA[12:0] lines. MA[2:0] must always driven burst mode. must driven interleave wrap type. needs driven value programmed CAS# Latency bit. MA[6:5] should always driven MA[12:7] must driven 00000. BIOS must calculate drive correct host address each memory such that correct command driven MA[12:0] lines. Note that MAB[7:4]# inverted from MAA[7:4]; BIOS must account this. Enable. this mode processor cycles SDRAM result cycle SDRAM interface.
DRAM Cycle Time (DCT). This controls number SCLKs access cycle. Tras SCLKs SCLKs (Default) Tras SCLKs SCLKs.
Host Aperture Cycle Queue Slot Enable. BIOS should this Disable. dedicated queue slot reserved host aperture cycles. (default) Enable. dedicated queue slot reserved host aperture cycles.
82815G GMCH Datasheet
Configuration Registers
Description CAS# Latency (CL). This controls number CLKs between when read command sampled SDRAMs when GMCH samples read data from SDRAMs. CAS# latency SCLKs. CAS# latency SCLKs.
SDRAM RAS# CAS# Delay (SRCD). This controls number SCLKs from Activate Command Read Write Command. clocks inserted between Activate Command either read write command. clocks inserted between Activate either Read Write Command.
SDRAM RAS# Precharge (SRP). This controls number SCLKs RAS# precharge. clocks RAS# precharge provided. clocks RAS# precharge provided.
3.4.18
DRP2-DRAM Population Register (Device
Address Offset: Default Value: Access: Size: Read/Write (Read-Only D_LCK bits
This register extends support physical rows DRAM three DIMMs. width bits. This second DRAM Population Register (DRP2) defines population each side DIMM Note that this entire register becomes read-only when D_LCK set. D_LCK description, SMRAM register (Device address offset 70h). system memory interface configured MHz, system BIOS must register (offset 52h) along with DRP2 register (offset 52h) detect whether memory configuration exceeds double-sided DIMMs three single-sided DIMMs. system BIOS must down-shift clock generator guarantee electrical integrity timings.
Reserved DIMM Population
Reserved.
Description
DIMM Population. This field indicates population DIMM Refer Supported System Memory DIMM Configurations table located with register definition. Note that some larger capacity DIMMs supported DIMM based capacities DIMM DIMM maximum supported main memory capacity
82815G GMCH Datasheet
Configuration Registers
3.4.19
FDHC-Fixed DRAM Hole Control Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This 8-bit register controls single fixed DRAM hole: MB-16
Hole Reserved
Description Hole Enable (HEN). This field enables memory hole DRAM space. Host cycles matching enabled hole passed Controller through interface. interface cycles matching enabled hole ignored GMCH. Note that selected hole re-mapped. Hole Enabled MB-16 (1MB) Hole Enabled
Reserved.
3.4.20
PAM-Programmable Attributes Registers (Device
Address Offset: Default Value: Attribute: Size: 59-5Fh Read/Write bits/register
GMCH allows programmable memory attributes Legacy memory segments various sizes address range. Seven Programmable Attribute (PAM) Registers used support these features. Cacheability these areas controlled MTRR registers processor. bits used specify memory attributes each memory segment. These bits apply host, AGP/PCI, interface initiator accesses areas. These attributes are: Read Enable (RE). When processor read accesses corresponding memory segment claimed GMCH directed main memory. Conversely, when host read accesses directed interface/PCI0. Write Enable (WE). When host write accesses corresponding memory segment claimed GMCH directed main memory. Conversely, when host write accesses directed interface/PCI0. attributes permit memory segment Read-Only, Write Only, Read/Write, disabled. example, memory segment segment Read-Only. Each Register controls regions, typically size. Each these regions 4-bit field. four bits that control each region have same encoding defined Table
82815G GMCH Datasheet
Configuration Registers
Table Attribute Assignments
Bits Reserved Bits Reserved Bits Bits Description Disabled. DRAM disabled accesses directed interface. GMCH does respond AGP/PCI interface target read write access this area. Read-Only. Reads forwarded DRAM writes forwarded interface termination. This write protects corresponding memory segment. GMCH responds AGP/PCI interface target read accesses write accesses. Write Only. Writes forwarded DRAM reads forwarded interface termination. GMCH responds AGP/PCI interface target write accesses read accesses. Read/Write. This normal operating mode main memory. Both read write cycles from host claimed GMCH forwarded DRAM. GMCH responds AGP/PCI interface target both read write accesses.
example, consider BIOS that implemented expansion bus. During initialization process, BIOS shadowed main memory increase system performance. When BIOS shadowed main memory, should copied same address location. shadow BIOS, attributes that address range should write only. BIOS shadowed first doing read that address. This read forwarded expansion bus. host then does write same address, which directed main memory. After BIOS shadowed, attributes that memory area read-only that writes forwarded expansion bus. Table Figure show registers associated attribute bits.
82815G GMCH Datasheet
Configuration Registers
Figure Registers
Offset PAM5 PAM4 PAM3 PAM2 PAM1 Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable
Read Enable (R/W 1=Enable 0=Disable
Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved
Table Registers Associated Memory Segments
PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] Attribute Bits Reserved 0F0000h-0FFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h- 0CFFFFh 0D0000h- 0D3FFFh 0D4000h- 0D7FFFh 0D8000h- 0DBFFFh 0DC000h- 0DFFFFh 0E0000h- 0E3FFFh 0E4000h- 0E7FFFh 0E8000h- 0EBFFFh 0EC000h- 0EFFFFh BIOS Area Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset
82815G GMCH Datasheet
Configuration Registers
Area (00000h-9FFFFh)
area size always mapped main memory controlled GMCH.
Video Buffer Area (A0000h-BFFFFh)
128-KB graphics adapter memory region normally mapped legacy video device interface/PCI (typically controller). This area controlled attribute bits processor-initiated cycles this region forwarded either interface AGP/Internal Graphics Device termination. This region also default region space. Note: functionality been removed from 82815G GMCH. Accesses this range directed either interface AGP/internal Graphics Device based configuration. configuration specified on/off configuration off: bits SMRAM register GMCH Device configuration space. There additional steering information coming from Device configuration registers from some registers Graphics device. GMCHCFG (Device PCI-PCI Command) BCTRL (Device PCI-PCI Bridge Control) configuration registers Control applied accesses initiated from system interfaces; that processor bus, interface, enabled). Note that interface AGP/PCI accesses, only memory write operations supported. AGP/PCI initiated accesses targeting GMCH will master abort. more details, descriptions configuration registers specified above. SMRAM Control register controls accesses this space treated.
Monochrome Adapter (MDA) Range (B0000h-B7FFFh)
Legacy support requires ability have second graphics controller (monochrome) system. system, accesses standard range forwarded (depending configuration bits). Since monochrome adapter interface/PCI ISA) bus, GMCH must decode cycles range forward them interface. This capability controlled configuration (MDA Device BEh). addition memory range B0000h B7FFFh, GMCH decodes cycles 3B4h, 3B5h, 3B8h, 3B9h, 3Bah 3BFh forwards them interface. internal graphics system, bits SMRAM register Device bits Device PCICMD register, bits from some registers control this functionality.
82815G GMCH Datasheet
Configuration Registers
Expansion Area (C0000h-DFFFFh)
This Expansion region divided into eight segments. Each segment assigned four Read/Write states: read-only, write-only, read/write, disabled. Typically, these blocks mapped through GMCH subtractively decoded space. Memory that disabled remapped.
Extended System BIOS Area (E0000h-EFFFFh)
This area divided into four, 16-KB segments. Each segment assigned independent read write attributes mapped either main DRAM interface. Typically, this area used ROM. Memory segments that disabled remapped elsewhere.
System BIOS Area (F0000h-FFFFFh)
This area single, 64-KB segment. This segment assigned read write attributes. default (after reset) read/write disabled cycles forwarded interface. manipulating read/write attributes, GMCH "shadow" BIOS into main DRAM. When disabled, this segment remapped.
82815G GMCH Datasheet
Configuration Registers
3.4.21
SMRAM-System Management Control Register (Device
Address Offset: Default Value: Access: Size: Read/Write, Read-Only bits
SMRAM register controls accesses Compatible Extended SMRAM spaces treated, much any) memory dedicated from system support both SMRAM graphics local memory needs.
Graphics Mode Select Upper Select Lower Select Space Locked E_SMRA M_ER
Description Graphics Mode Select (GMS). This field enables/disables Internal Graphics device selects amount main memory that dedicated support internal graphics device (non-linear) mode only. These bits only have meaning mode. Note: functionality been removed from Intel 82815G GMCH. Internal graphics device Disabled, memory dedicated Internal graphics device Enabled, memory dedicated Internal graphics device Enabled, memory dedicated frame buffer. Internal graphics device Enabled, memory dedicated frame buffer. Notes: When internal graphics device disabled (00), graphics device memory functions disabled clocks this logic turned off; memory accesses range (A0000-BFFFF) forwarded interface graphics local memory space dedicated from main memory. change SMRAM register will affect mode cause controller into mode. When this field non-zero, internal graphics device memory functions enabled; non-SMM memory accesses range will handled internally selected amount graphics local memory space dedicated from main memory. Graphics memory dedicated AFTER TSEG memory dedicated. Once D_LCK set, these bits become read-only. GMCH does support local memory. Software must mode VGA.
82815G GMCH Datasheet
Configuration Registers
Description Upper Select (USMM). This field used enable/disable various memory ranges above TSEG block memory ("Stolen" from Main Memory [TOM-Size] [TOM]) that only accessible processor only while operating mode. HSEG remap segment FEEA0000 FEEBFFFF. Both these areas, when enabled, usable RAM. TSEG HSEG both disabled TSEG disabled, HSEG conditionally enabled TSEG enabled HSEG conditionally enabled TSEG enabled HSEG conditionally enabled Notes: Non-SMM Operations (SMM processor accesses other access) that these address ranges forwarded interface. Once D_LCK set, these bits become read-only. HSEG ONLY enabled LSMM
Lower Select (LSMM). This field controls definition segment space. segment disabled write it). segment enabled general system (anyone write it). segment enabled Code shadow. Only code reads access DRAM segment (processor code reads only). Data operations NonSMM Operations either internal graphics device broadcast interface. segment enabled RAM. operations segment serviced DRAM, Non-SMM operations either internal graphics device broadcast interface (processor access space). When D_LCK set, becomes read-only, writeable ONLY When set, only processor access
Space Locked (D_LCK). When D_LCK then D_LCK, GMS, USMM, most significant LSMM become read-only. D_LCK normal configuration space write only cleared reset. combination D_LCK LSMM provide convenience with security. BIOS LSMM=01 initialize space then D_LCK "lock down" space future that application software BIOS itself) violate integrity space, even program knowledge LSMM function. This also Locks DRP2 registers. E_SMRAM_ERR (E_SMERR). software's responsibility clear this bit. Software must write this clear This when processor accesses defined memory ranges Extended SMRAM (HSEG TSEG) while mode. This case explicit writeback operation.
82815G GMCH Datasheet
Configuration Registers
3.4.22
MISCC-Miscellaneous Control Register (Device
Address Offset: Default Value: Access: Size: 72-73h 0000h Read/Write, Read-Only bits
This register holds miscellaneous control bits GMCH
Enable Reserved Mask Reserved
Throttle Lock
Reserved
Lookahead
Size
Read Throttle Cntl
Write Throttle Cntl
Description System Memory Graphics PC133 Enable-R/W. This allows GMCH operate Graphics Mode with Enhanced System Memory (PC133). Normally, frequency locked Internal Graphics mode, GMCHCFG[2] (SMFS) read-only. Setting this allows frequency changed writing GMCHCFG[2]. This effect mode. Note: functionality been removed from Intel 82815G GMCH. Normal Operation. GMCHCFG[2] hardwired when GMCH Graphics Mode (i.e., APCONT[0]
Allow System Memory when GMCH Graphics Mode. Note that this just enables PC133. actually graphics with GMCHCFG[2] must Also, this should BIOS before GMCH changed from Graphics mode APCONT[0]. Reserved. Transmit Stage Bypass-R/W. Normal Operation (Default). Bypass SM=100 MHz; bypass SM=133 MHz. Always bypass, regardless frequency. System BIOS should this enable bypass optimize system memory latency clock operation (has affect operation). Reserved. Mask Enable-R/W. Normal Operation (default). Never perform command clock accesses system memory. Mask command clock. Note: This must using system memory. 10:8 Reserved.
82815G GMCH Datasheet
Configuration Registers
Description Read Power Throttle Control-R/W. These bits select Power Throttle Bandwidth Limits read operations system memory. R/W, Throttle Lock (bit =1). These bits locked (read-only) when (Throttle Lock) Limit Limit Limit Limit (800 MB/Sec) (Default) (700 MB/Sec) (600 MB/Sec) (500 MB/Sec)
Write Power Throttle Control-R/W. These bits select Power Throttle Bandwidth Limits Write operations System Memory. R/W, Throttle Lock (bit =1). These bits locked (read-only) when (Throttle Lock) Limit Limit Limit Limit (800 MB/Sec) (Default) (500 MB/Sec) (400 MB/Sec) (300 MB/Sec)
Note: These bits must `01' using system memory `10' using system memory. Throttle Lock-R/W. R/W, Throttle Lock (bit =1). Once set, this only cleared reset. Bits [7:3] remain writeable Block writes bits [7:3] Reserved-RO. Lookahead-R/W. This enables unit look further data path optimize (Block Requests) signal increase effective Order Queue) depth. Normal Behavior (default) Lookahead Enable Graphics Translation Window Size Select-R/W. mode this would size (Graphics Translation Table). valid mode. Note: functionality been removed from Intel 82815G GMCH. (default)
82815G GMCH Datasheet
Configuration Registers
3.4.23
CAPID-Capability Identification (Device Mode Only)
Address Offset: Default Value: Access: Size: 88-8Bh F104 A009h Read-Only bits
This register uniquely identifies chipset capabilities defined table below. Writes this register have effect. Note: functionality been removed from 82815G GMCH.
Capability Display Cache Capability Capability Internal Graphics Capability CAPID Version
CAPID Length Next Capability Pointer CAP_ID
Capability-RO.
Description
Component capable front side system memory. Component capable front side system memory. Display Cache Capability-RO. Only supports mode local memory). Component local memory (Display Cache) capable. Capability-RO. mode supported. Note that interface still active through addition AIMM card bits both mode supported. Internal Graphics Capability-RO. Internal graphic controller supported. Internal graphic controller supported. 27:24 23:16 15:8 CAPID Version-RO. This field value 0001b identify first revision CAPID register definition. CAPID Length-RO. This field value indicate structure length. Next Capability Pointer-RO. This field possible values based APCONT[0] offset 51h: when APCONT[0] (AGP Mode) meaning next capability pointer ACAPID. when APCONT[0] (GFX Mode) meaning that this last capability pointer list. CAP_ID-RO. This field value 1001b identify CAP_ID assigned vendor dependent capability pointers.
82815G GMCH Datasheet
Configuration Registers
3.4.24
BUFF_SC-System Memory Buffer Strength Control Register (Device
Address Offset: Default Value: Access: Size: 92-93h FFFFh Read/Write bits
This register programs system memory DRAM interface signal buffer strengths, with exception CKEs. programming these bits should based DRAM density x16), DRAM technology Mb), rows populated, etc. Note that DRAMs supported. Registered DIMMs DIMMS with also supported BIOS upon detection SPD, should report user that DIMM timings supported GMCH. descriptions below, term "Row" equivalent side DIMM. other words, "single-sided" DIMM contains populated (always numbered), empty (even numbered). "double-sided" DIMM contains populated rows. buffer strengths based number "loads" connected each given signal group. "load" represents SDRAM Device. GMCH implied counted load equations. number loads given signal given configuration determined entirely from width SDRAM devices that populate each configuration. This information readily available each Serial Presence Detect mechanism.
82815G GMCH Datasheet
Configuration Registers
SCS[5]# Buffer Strength
SCS[4]# Buffer Strength
SCS[3]# Buffer Strength
SCS[2]# Buffer Strength
SCS[1]# Buffer Strength
SCS[0]# Buffer Strength
SMAC[7:4]# Buffer Strength
SMAB[7:4]# Buffer Strength
SMAA[7:4] Buffer Strength
Buffer Strengths
Control Buffer Strengths
SCS[5]# Buffer Strength (Row Reserved 1.0x load loads)
Description
Each actually selected pair chip select signals (SCSA[n]# SCSB[n]#). number SCS# loads given determined from data using following equation: Loads (width SDRAM devices row) SCS[4]# Buffer Strength (Row Reserved 1.0x load loads) SCS[3]# Buffer Strength (Row Reserved 1.0x load loads) SCS[2]# Buffer Strength (Row Reserved 1.0x load loads) SCS[1]# Buffer Strength (Row Reserved 1.0x load loads) SCS[0]# Buffer Strength (Row Reserved 1.0x load loads) SMAC[7:4]# Buffer Strength (Rows 4/5). 2.7x loads) 1.7x loads) 1.0x loads) 1.0x loads) Separate copies these SMA*[7:4] "Command-Per-Clock" signals provided each DIMM. loads each copy determined number SDRAM devices corresponding DIMM loads). number loads each SMA*[7:4] signal group determined from data using following equation: Loads (SDRAM Device Width row)) (SDRAM Device Width row))
82815G GMCH Datasheet
Configuration Registers
SMAB[7:4]# Buffer Strength (Rows 2/3). 2.7x loads) 1.7x loads) 1.0x loads) 1.0x loads) SMAA[7:4] Buffer Strength (Rows 0/1). 2.7x loads) 1.7x loads) 1.0x loads) 1.0x loads)
Description
SMD[63:0] SDQM[7:0] Buffer Strengths (All Rows). Reserved Reserved Reserved 1.0x (1-6 loads) load SDQM signals function only number populated rows system (range loads): Loads Number populated rows.
SWE#, SCAS#, SRAS#, SMAA[11:8, 3:0], SBS[1:0] Control Buffer Strengths (All Rows). 1.7x loads) 0.7x loads) 1.0x (8-32 loads) 1.0x (8-32 loads) load address control signals (other than SMA*[7:4] above) simply number devices populated rows (range from loads!). Loads Device Width) Device Width) Device Width) Device Width) Device Width) Device Width)
82815G GMCH Datasheet
Configuration Registers
3.4.25
BUFF_SC2-System Memory Buffer Strength Control Register (Device
Address Offset: Default Value: Access: Size: 94-95h FFFFh Read/Write bits
This register programs system memory DRAM interface signal buffer strengths. BUFF_SC register remainder buffer strength controls.
Reserved (R/W)
Reserved (R/W)
CKE5 Buffer Strength
CKE4 Buffer Strength
CKE3 Buffer Strength
CKE2 Buffer Strength
CKE1 Buffer Strength
CKE0 Buffer Strength
15:6 Reserved. SCKE[5] Buffer Strength (Row 2.7x loads 1.7x loads
Description
load given SCKE signal equal number SDRAM devices that particular (either loads). Loads SDRAM Device Width this row) SCKE[4] Buffer Strength (Row 2.7x loads 1.7x loads SCKE[3] Buffer Strength (Row 2.7x loads 1.7x loads SCKE[2] Buffer Strength (Row 2.7x loads 1.7x loads SCKE[1] Buffer Strength (Row 2.7x loads 1.7x loads SCKE[0] Buffer Strength (Row 2.7x loads 1.7x loads
82815G GMCH Datasheet
Configuration Registers
3.4.26
SM_RCOMP-System Memory Compensation Control Register (Device
Address Offset: Default Value: Access: Size: 98-9Bh XXXXXXXXh Read/Write, Read-Only bits
This register controls system memory Rcomp buffers (both horizontally vertically oriented).
Override Enable Reserved SRCOMP_VP Reserved SRCOMP_VN
Override Enable
Reserved
SRCOMP_HP
Reserved
SRCOMP_HN
SRCOMP_V Override Enable-R/W.
Description
Rcomp active vertically oriented buffers (Default). Rcomp NOT-active vertically oriented buffers. 30:23 22:20 Reserved. SRCOMP_VP-RO R/W. P-Channel Compensation Value Vertical Buffers. This value generated Rcomp logic control drive characteristics vertically oriented P-channel devices buffers. Normal operation, field read-only reflects current compensation. Override Mode (see 31), field written with desired compensation value that loaded software when Rcomp operation disabled. 18:16 Reserved. SRCOMP_VN-RO R/W. N-Channel Compensation Value Vertical Buffers. This value generated Rcomp logic control drive characteristics vertically oriented N-channel devices buffers. Normal operation, field read-only reflects current compensation. Override Mode (see 31), field written with desired compensation value that loaded software when Rcomp operation disabled. SRCOMP_H Override Enable-R/W. Rcomp active horizontally oriented buffers (Default). Rcomp active horizontally oriented buffers. 14:7 Reserved.
82815G GMCH Datasheet
Configuration Registers
Description SRCOMP_HP-RO R/W. P-Channel Compensation Value Horizontal Buffers. This value generated Rcomp logic control drive characteristics horizontally oriented P-channel devices buffers. Normal operation, field read-only reflects current compensation. Override Mode (see 15), field written with desired compensation value that loaded software when Rcomp operation disabled.
Reserved. SRCOMP_HN-RO R/W. N-Channel Compensation Value Horizontal Buffers. This value generated Rcomp logic control drive characteristics horizontally oriented N-channel devices buffers. Normal operation, field read-only reflects current compensation. Override Mode (see 15), field written with desired compensation value that loaded software when Rcomp operation disabled.
3.4.27
SM-System Memory Control Register
Address Offset: Default Value: Access: Size: 9C-9Fh XXXXXXXXh Read/Write, Read-Only bits
This register controls System Memory Delay Locked Loop (DLL) blocks that offset transmit receive clocks used interface with external SDRAM devices. Transmit provides early version SCLK provide additional setup margin external SDRAM devices. Receive provides late version SCLK provide additional setup time read data driven SDRAM devices back GMCH. default, Transmit enabled (whether operating frequency MHz). Receive always bypassed, regardless operating frequency. When RDLL bypassed, RDLL Bias field, instead, controls buffer delay chain with programmable points. This chain eight points each with approximately incremental delay slow corner (total delay range about incremental delay "fast" corner 0.56 total range).
Reserved TDLL Bypass Reserved
31:16 Reserved. Transmit Enable (TDLLE)-R/W. TDLL Enabled (Default) TDLL Disabled bypassed 14:0 Reserved.
Description
82815G GMCH Datasheet
Configuration Registers
3.4.28
ACAPID-AGP Capability Identifier Register (Device Mode Only)
Address Offset: Default Value: Access: Size: A0-A3h 00200002h Read-Only bits
This register provides standard identifier capability. Note: functionality been removed from 82815G GMCH.
Reserved
Major Revision Number
Minor Revision Number
Next Capability Pointer
Capability
31:24 23:20 Reserved.
Description
Major Revision Number. These bits provide major revision number specification that this version GMCH conforms. These bits value 0010b indicate Rev. 2.x. Minor Revision Number. These bits provide minor revision number specification that this version GMCH conforms. This number hardwired value "0000" (i.e., implying x.0). Together with major revision number this field identifies GMCH compliant device.
19:16
15:8
Next Capability Pointer. capability first last capability described capability pointer mechanism; therefore, these bits hardwired indicate capability linked list. Capability This field identifies linked list item containing registers. This field value 0000_0010b assigned SIG.
82815G GMCH Datasheet
Configuration Registers
3.4.29
AGPSTAT-AGP Status Register (Device Mode Only)
Address Offset: Default Value: Access: Size: A4-A7h 1F000207h Read-Only bits
This register reports device capability/status. Note: functionality been removed from 82815G GMCH.
Request Queue (RQ) (HW=1Fh) Reserved Reserved (HW=1) Fast Writes (HW=0) Reserved Data Transfer Rate (HW=111; 1x,2x,4x modes supported) Reserve
Reserved
Support (HW=0)
31:24
Description Request Queue (RQ). This field hardwired indicate maximum outstanding command requests handled GMCH. This field contains maximum number command requests GMCH configured manage. lower bits this field reflect value programmed AGPCTRL[12:10]. Only discrete values selected AGPCTRL. Upper bits hardwired Default =1Fh allow maximum outstanding command requests.
23:10
Reserved SideBand Addressing (SBA). Indicates GMCH supports sideband addressing. Hardwired Reserved Greater Than Address Support (4GB). This indicates that GMCH does support addresses greater than hardwired Fast Writes (FW). This indicates that GMCH does support Fast Writes from processor master. hardwired Reserved Data Transfer Rate Capability (RATE). After reset GMCH reports data transfer rate capability. Note that selected data transfer mode applies both bus. data transfer mode data transfer mode data transfer mode. This masked AGPCTRL register (AGP Override). data transfer modes supported GMCH; therefore, this field Default Value 111.
82815G GMCH Datasheet
Configuration Registers
3.4.30
AGPCMD-AGP Command Register (Device Mode Only)
Address Offset: Default Value: Access: Size: A8-ABh 00000000h Read/Write bits
This register provides control operational parameters. Note: functionality been removed from 82815G GMCH.
Reserved Reserved (HW=0) Reserved Data Rate
31:10 Reserved. Sideband Address Enable (SBA). Disable.
Description
Enable. sideband addressing mechanism enabled. Enable. When this reset GMCH ignores operations, including sync cycle. operations received while this will serviced, even this reset this transitions from clock edge middle command being delivered mode, command issued. When this GMCH will respond operations delivered PIPE#, operations delivered SBA, Side Band Enable also Reserved. Greater Than Support (4GB). Hardwired GMCH target does support addressing greater than Fast Writes Enable (FW). This must always programmed chipset will behave unpredictably this programmed with Reserved. Data Rate Capability. settings these bits determine data transfer rate. (and only one) this field must indicate desired data transfer rate. same must both master target. Configuration software will update this field setting only that corresponds capability master (after that capability been verified accessing same functional register within master's configuration space.) becomes reserved (but will still read erroneously) when Override CTRL register because this will updated Override mode. When Override writes Data Rate[2] have functional impact. Note: This field applies buses.
82815G GMCH Datasheet
Configuration Registers
3.4.31
AGPCTRL-AGP Control Register (Device Mode Only)
Address Offset: Default Value: Access: Size: B0-B3h 00000000h Read/Write bits
This register provides additional control interface. Note: functionality been removed from 82815G GMCH.
Reserved GTLB_EN Reserved Override
31:8 Reserved
Description
GTLB Enable (and GTLB Flush Control)-R/W. Disable (default). GTLB flushed clearing valid bits associated with each entry. this mode operation accesses that require translation bypass GTLB. requests that positively decoded graphics aperture force GMCH access translation table main memory before completing request. Translation table entry fetches cached GTLB. Enables normal operations Graphics Translation Lookaside Buffer. Notes: When invalid translation table entry read, this entry still cached GTLB (ejecting least recently used entry). GMCH flushes when software sets clears this ensure coherency between GTLB main memory. This changed dynamically (i.e., while access GTLB occurs).
Reserved Override. When this Rate[2] AGPSTAT register will read This "back-door" register allows BIOS disable mode. introduction universal cards universal motherboards raised some potential problems that this alleviates. operation operate only system that supporting operation, therefore cannot support transfer rate, responsibility BIOS make sure that mode selected.
82815G GMCH Datasheet
Configuration Registers
3.4.32
APSIZE-Aperture Size (Device Mode Only)
Address Offset: Default Value: Access: Size: Read/Write bits
This register determines effective size graphics aperture used particular GMCH configuration. This register updated GMCH-specific BIOS configuration sequence before standard enumeration sequence takes place. register updated, default value will select aperture maximum size (i.e., MB). Note: functionality been removed from 82815G GMCH.
Reserved Aperture Size Reserved
Reserved.
Description
Graphics Aperture Size (GASIZE). operates Aperture Base (APBASE) configuration register. When this forces APBASE behave "hardwired" When this forces APBASE read/write accessible. Only following combinations allowed: 64-MB Aperture Size 32-MB Aperture Size Default APSIZE[3]=0b forces default APBASE[25] (responds "hardwired" This provides maximum aperture size Programming APSIZE[3]=1b enables APBASE[25] read/write programmable.
Reserved.
82815G GMCH Datasheet
Configuration Registers
3.4.33
ATTBASE-Aperture Translation Table Base Register (Device Mode Only)
Address Offset: Default Value: Access: Size: B8-BBh 00000000h Read/Write bits
This register provides starting address Graphics Aperture Translation Table Base located main DRAM. This value used GMCH's Graphics Aperture address translation logic (including GTLB logic) obtain appropriate address translation entry required during translation aperture address into corresponding physical DRAM address. ATTBASE register dynamically changed. Note:
Reserved
address provided ATTBASE 4-KB aligned.
Base Address Reserved
31:29 28:12 11:0 Reserved.
Description
Base Address. This field contains pointer base translation table used memory space addresses aperture range addresses main memory. Reserved.
82815G GMCH Datasheet
Configuration Registers
3.4.34
AMTT-AGP Multi-Transaction Timer (Device Mode Only)
Address Offset: Default Value: Access: Size: Read/Write bits
AMTT controls amount time that GMCH's arbiter allows AGP/PCI master perform multiple back-to-back transactions. GMCH's AMTT mechanism used optimize performance master (using semantics) that performs multiple back-to-back transactions fragmented memory ranges (and consequence long burst transfers). AMTT mechanism applies processor AGP/PCI transactions well guarantees processor fair share AGP/PCI interface bandwidth. Note: functionality been removed from 82815G GMCH. number
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