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Typical VOLP (Output Ground Bounce) 25°C High-Impedance State During P
Top Searches for this datasheetSN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS Typical VOLP (Output Ground Bounce) 25°C High-Impedance State During Power Power Down High-Drive Outputs (-32-mA IOH, 64-mA IOL) Ioff Power-Up 3-State Support Insertion Latch-Up Performance Exceeds JESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) SN54ABT126 PACKAGE (TOP VIEW) internal connection ORDERABLE PART NUMBER SN74ABT126RGYR SN74ABT126N SN74ABT126D SN74ABT126DR SN74ABT126NSR SN74ABT126DBR SN74ABT126PW SN74ABT126PWR SNJ54ABT126J TOP-SIDE MARKING AB126 SN74ABT126N ABT126 ABT126 AB126 AB126 SNJ54ABT126J Copyright 2003, Texas Instruments Incorporated SN54ABT126 PACKAGE SN74ABT126 PACKAGE (TOP VIEW) SN74ABT126 PACKAGE (TOP VIEW) description/ordering information 'ABT126 buffer gates feature independent line drivers with 3-state outputs. Each output disabled when associated output-enable (OE) input low. When between device high-impedance state during power power down. However, ensure high-impedance state above should tied through pulldown resistor; minimum value resistor determined current-sourcing capability driver. ORDERING INFORMATION PACKAGE PDIP SOIC -40°C 85°C 40°C SSOP TSSOP -55°C 125°C 55°C CDIP Tape reel Tube Tube Tape reel Tape reel Tape reel Tube Tape reel Tube LCCC Tube SNJ54ABT126FK SNJ54ABT126FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS FUNCTION TABLE (each buffer) INPUTS OUTPUT logic diagram (positive logic) numbers shown packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT126 SN74ABT126 Input clamp current, Output clamp current, Package thermal impedance, (see Note package 86°C/W (see Note package 96°C/W (see Note package 80°C/W (see Note package 76°C/W (see Note package 113°C/W (see Note package 47°C/W Storage temperature range, Tstg -65°C 150°C Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with JESD 51-7. package thermal impedance calculated accordance with JESD 51-5. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS recommended operating conditions (see Note SN54ABT126 t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Power-up ramp rate Operating free-air temperature SN74ABT126 UNIT ns/V µs/V NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Vhys IOZPU IOZPD IOZH IOZL Ioff ICEX TEST CONDITIONS input Other inputs Outputs high Outputs high Outputs Outputs disabled Outputs enabled Outputs disabled -100 ±100 -200 -200 ±100 -200 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT126 -1.2 SN74ABT126 -1.2 UNIT products compliant MIL-PRF-38535, this parameter does apply. typical values between should less than equal ensure state. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level, rather than GND. PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS switching characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Note Figure PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT126 SN74ABT126 UNIT NOTE Limits vary among suppliers. PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice. POST OFFICE 655303 DALLAS, TEXAS 75265 SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open From Output Under Test (see Note LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note tPZH Output Waveform Open (see Note tPLZ tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING Input tPLH Output tPHL tPHL tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. parameters waveforms applicable devices. Figure Load Circuit Voltage Waveforms POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL MPDI002C JANUARY 1995 REVISED DECEMBER 20002 (R-PDIP-T**) PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE PINS 0.775 (19,69) 0.745 (18,92) 0.775 (19,69) 0.745 (18,92) 0.920 (23,37) 0.850 (21,59) 1.060 (26,92) 0.940 (23,88) 0.260 (6,60) 0.240 (6,10) MS-100 VARIATION 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) 0.020 (0,51) 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.430 (10,92) 14/18 ONLY vendor option 4040049/E 12/2002 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width. POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL DATA MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001 (R-PDSO-G**) PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) Gage Plane 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS 0.197 (5,00) 0.189 (4,80) 0.344 (8,75) 0.337 (8,55) 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 (R-PDSO-G**) PINS SHOWN 0,65 0,38 0,22 0,15 PLASTIC SMALL-OUTLINE 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 0,25 0,95 0,55 Seating Plane 2,00 0,05 0,10 PINS 6,50 6,50 7,50 8,50 10,50 10,50 12,90 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 12/01 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150 POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 0,30 0,19 0,10 0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50 Seating Plane 1,20 0,15 0,05 0,10 PINS 3,10 5,10 5,10 6,60 7,90 9,80 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153 POST OFFICE 655303 DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. 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