SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREE
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M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M37221EF-XXXSP M37221EFSP single-chip microcomputers designed with CMOS silicon gate technology. They housed 42-pin shrink plastic molded DIP. addition their simple instruction sets, ROM, addresses placed same memory enable easy programming. M37221EF-XXXSP M37221EFSP have output function display function, useful channel selection system
CONFIGURATION (TOP VIEW)
HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 CNVSS XOUT
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34
M37221EF-XXXSP M37221EFSP
FEATURES
Number basic instructions Memory size
bytes 1216 bytes display bytes display bytes minimum instruction execution time oscillation frequency) Power source voltage Power dissipation. oscillation frequency, =5.5V, display) Subroutine nesting levels (maximum) Interrupts types, vectors 8-bit timers Programmable ports (Ports P30-P32) Input ports (Ports P33, Output ports (Ports P52-P55) withstand ports drive ports Serial 8-bit channel Multi-master C-BUS interface systems) comparator (6-bit resolution) channels converter (6-bit resolution) output circuit 14-bit 8-bit correction function bytes
Outline 42P4B
display function
Number display characters characters lines lines maximum) Kinds characters kinds structure dots Kinds character sizes kinds Kinds character colors specified character) maximum kinds Kinds character background colors specified character) maximum kinds Kinds raster colors (maximum kinds) Display position Horizontal levels Vertical levels Bordering (horizontal vertical)
APPLICATION
INT3
INT2
SCLK SOUT
PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
INT1
OUT2
OUT1
3031 3435
1312 1136
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
port
port
port
ports P30-P3
Output ports 2-P55
VSYNC HSYNC
FUNCTIONAL BLOCK DIAGRAM M37221EF-XXXSP
Clock input Clock output
XOUT
Timing output
Reset input RESET
Input ports Clock input display Clock output display OSC1 OSC2
Clock generating circuit
TIM2 TIM3
Data
Timer count source selection circuit Timer Timer Timer Control signal Instruction decoder Instruction register circuit Timer
1216 bytes
Program counter
Program counter
bytes
Address
8-bit arithmetic logical unit Index register Stack pointer
Accumulator
Processor status register
Index register
comparator Multi-master C-BUS interface
14-bit circuit
converter
SI/O(8)
8-bit circuit
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONS
Parameter Number basic instructions Instruction execution time Clock frequency Memory size Input/Output ports P10, 5-P17 P11-P1 P20, P22-P2 P30, P33, P52-P5 Serial Multi-master I2C-BUS interface comparator converter output circuit Timers correction function Subroutine nesting Interrupt Input Output Functions (the minimum instruction execution time, oscillation frequency) (maximum) bytes 1216 bytes bytes bytes 8-bit (N-channel open-drain output structure, used output pins, input pins, input pin) 4-bit (CMOS input/output structure, used output pin, input pins, input pin) 4-bit (CMOS input/output structure, used multi-master I2CBUS interface) 2-bit (CMOS input/output N-channel open-drain output structure, used serial pins) 6-bit (CMOS input/output structure, used serial input pin, external clock input pins) 2-bit (CMOS input/output N-channel open-drain output structure, used input pins, conversion output pins) 1-bit (N-channel open-drain output structure) 2-bit (can used display clock pins) 4-bit (CMOS output structure, used output pins) 8-bit systems) channels (6-bit resolution) (6-bit resolution) 14-bit 8-bit 8-bit timer bytes levels (maximum) External interrupt Internal timer interrupt Serial interrupt interrupt Multi-master C-BUS interface interrupt f(XIN)/4096 interrupt VSYNC interrupt interrupt built-in circuits (externally connected ceramic resonator quartzcrystal oscillator) stop mode Operating temperature range Device structure Package display function Number display characters structure Kinds characters Kinds character sizes Kinds character colors Display position (horizontal, vertical) typ. oscillation frequency fCPU MHz, fCRT MHz) typ. oscillation frequency fCPU MHz) 1.65 (maximum) CMOS silicon gate process 42-pin shrink plastic molded characters lines (maximum lines software) dots kinds kinds Maximum kinds specified character levels (horizontal) levels (vertical)
Clock generating circuit Power source voltage Power dissipation
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
VSS. CNVSS
Name Power source
Input/ Output
Functions Apply voltage (typical) VCC, VSS.
CNVSS Reset input Input
This connected enter reset state, reset input must kept more (under normal conditions). more time needed quartz-crystal oscillator stabilize, this condition should maintained required time. This chip internal clock generating circuit. control generating frequency, external ceramic resonator quartz-crystal oscillator connected between pins XOUT. external clock used, clock source should connected XOUT should left open. Port 8-bit port with direction register allowing each individually programmed input output. reset, this port input mode. output structure N-channel open-drain output. note this Table gives full port function. Pins P00-P0 also used output pins PWM0-PWM5 respectively. output structure N-channel open-drain output. Pins also used external interrupt input pins INT2, INT1 respectively. also used analog input A-D4. Port 8-bit port basically same functions port output structure CMOS output. Pins also used output OUT2. output structure CMOS output. Pins P11-P14 used SCL1, SCL2, SDA1 SDA2 respectively, when multi-master 2C-BUS interface used. output structure N-channel open-drain output. Pins P15-P1 also used analog input pins A-D1 A-D3 respectively. also used external interrupt input INT3. Port 8-bit port basically same functions port output structure CMOS output. Pins P23, also used external clock input pins TIM3, TIM2 respectively. also used serial synchronizing clock input/output SCLK. output structure N-channel open-drain output. Pins also used serial data input/output pins SOUT, respectively. output structure N-channel open-drain output. Ports P30-P3 3-bit port basically same functions port Either CMOS output N-channel open-drain output structure selected port P31. output structure port N-channel open-drain output. Pins P30, also used analog input pins A-D5, A-D6 respectively. Pins P30, also used conversion output pins DA1, respectively. Ports 2-bit input port. also used display clock input OSC1. also used display clock output OSC2. output structure CMOS output.
RESET
XOUT P00/PWM0- P05/PWM5, P06/INT2/ A-D4, P07/INT1
Clock input Clock output port
Input Output
output External interrupt input Analog input
Output Input Input Output Input Input Input
P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, P16/A-D2, P17/A-D3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25-P2
port output Multi-master C-BUS interface Analog input External interrupt input port External clock input Serial synchronizing clock input/ output Serial data input/output
P30/A-D5/ DA1, P31/A-D6/ DA2,
port
Analog input conversion output
Input Output Input Input Output
P33/OSC1, Input port P34/OSC2 Clock input display Clock output display
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION (continued)
P52/R, P53/G, P54/B, P55/OUT1 HSYNC VSYNC Output port output HSYNC input VSYNC input output Output Output Input Input Output Ports 4-bit output port. output structure CMOS output. Pins 2-P55 also used output pins OUT1 respectively. output structure CMOS output. This horizontal synchronizing signal input CRT. This vertical synchronizing signal input CRT. This 14-bit output pin.
Note shown memory (Figure port accessed memory address 00C016 zero page. Port port direction register (address 00C116 zero page) which used program each input ("0") output ("1"). pins programmed direction register output pins. When pins programmed "0," they input pins. When pins programmed output pins, output data written into port latch then output. When data read from output pins, output level read data port latch read. This allows previously-output value read correctly even output voltage risen, example, because light emitting diode directly driven. input pins floating state, values pins read. When data written into input pin, written only into port latch, while remains floating state.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
M37221EF-XXXSP uses standard family instruction set. Refer table family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Machine-resident family instructions follows: FST, instruction cannot used. MUL, DIV, instruction used.
Mode Register
mode register contains stack page selection bit. mode register allocated address 00FB
mode register (CPUM address 00FB16) these bits "0."
Stack page selection (Note) Zero page page
these bits "1." Note Please beware this when programming because after reset release.
Fig. Structure mode register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
MEMORY Special Function Register (SFR) Area
special function register (SFR) area zero page contains control registers such ports timers.
Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
Zero Page
bytes from addresses 000016 00FF16 called zero page area. internal special function registers (SFR) allocated this area. zero page addressing mode used specify memory register addresses zero page area. Access this area with only bytes possible zero page addressing mode.
used data storage stack area subroutine calls interrupts.
used storing user programs well interrupt vector area.
Special Page
bytes from addresses FF0016 FFFF called special page area. special page addressing mode used specify memory addresses special page area. Access this area with only bytes possible special page addressing mode.
Display
display used specifying character codes colors display.
Display
display used storing character data.
000016 display bytes)
1000016
(448 bytes)
00C016 area 00FF16 01FF16 used 021716 021B16 02C016 02FF16 030016 05FF16 060016 06B716 used 080016 correction memory (RAM) page register used
Zero page
11FFF16
(768 bytes) display (Note) bytes)
used
bytes)
FF0016 FFDE16 Interrupt vector area FFFF16
Special page 1FFFF16 Note: Refer Table Contents display RAM.
Fig. Memory
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
sSFR area (addresses C016 DF16)
Nothing allocated this write "1") immediately after reset immediately after reset undefined immediately after reset
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
allocation
State immediately after reset
Port (P0) Port direction register (D0) Port (P1) Port direction register (D1) Port (P2) Port direction register (D2) Port (P3) Port direction register (D3)
Port (P5) Port direction register (D5) Port output mode control register (P3S) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) output control register (PW) output control register (PN) data shift register (S0) address register (S0D) status register (S1) control register (S1D) clock control register (S2) Serial mode register (SM) Serial regsiter (SIO) conversion register (DA1) conversion register (DA2)
DA2S DA1S P31S P30S
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
BSEL1 BSEL0 FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20
0016 0016 0016 0016 0016 0016 0016
Fig. Memory (special function register)
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
sSFR area (addresses E016 FF16)
Nothing allocated this write "1") this write "0") immediately after reset immediately after reset undefined immediately after reset
Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Register
allocation
CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20
State immediately after reset
Horizontal register (HR) Vertical register (CV1) Vertical register (CV2) Character size register (CS) Border selection register (MD) Color register (CO0) Color register (CO1) Color register (CO2) Color register (CO3) control register (CC) port control register (CRTP) clock selection register (CK) control register (AD1) control register (AD2) Timer (TM1) Timer (TM2) Timer (TM3) Timer (TM4) Timer mode register (T12M) Timer mode register (T34M) PWM5 register (PWM5)
CS21 CS20 CS11 CS10 MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10
OUT1 OUT2 R/G/B VSYC HSYC
ADM4 ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
T12M4 T12M3 T12M2 T12M1 T12M0 T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
Interrupt input polarity register (RE) Test register (TEST) mode register (CPUM) Interrupt request register (IREQ1) Interrupt request register (IREQ2) Interrupt control register (ICON1) Interrupt control register (ICON2)
IT3R
IICR VSCR CRTR TM4R TM3R TM2R TM1R
IT3E
1T2R 1T1R
IICE VSCE CRTE TM4E TM3E TM2E TM1E
1T2E 1T1E
0016 FF16 0716 FF16 0716 0016
Fig. Memory (special function register)
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
sSFR area (addresses 20016 21F16)
Nothing allocated this write "1") immediately after reset
Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16
Register
allocation
State immediately after reset
RCR1 RCR0
correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register (RCR)
Fig. Memory page register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts caused different sources consisting external, internal, software, reset. Interrupts vectored interrupts with priorities shown Table Reset also included table because operation similar interrupt. When interrupt accepted, contents program counter processor status register automatically stored into stack. interrupt disable flag corresponding interrupt request "0." jump destination address stored vector address enters program counter. Other interrupts disabled when interrupt disable flag "1." interrupts except instruction interrupt have interrupt request interrupt enable bit. interrupt request bits interrupt request registers interrupt enable bits interrupt control registers Figure shows structure interrupt-related registers. Interrupts other than instruction interrupt reset accepted when interrupt enable "1," interrupt request "1," interrupt disable flag "0." interrupt request program, "1." interrupt enable program. Reset treated non-maskable interrupt with highest priority. Figure shows interrupt control.
Interrupt Causes
VSYNC interrupts VSYNC interrupt interrupt request synchronized with vertical sync signal. interrupt occurs after character block display completed. INT1, INT2, INT3 interrupts With external interrupt input, system detects that level changes from from "L," generates interrupt request. input active edge selected bits interrupt input polarity register (address 00F9 when this "0," change from detected; when "1," change from detected. Note that bits cleared reset. Timer interrupts interrupt generated overflow timer Serial interrupt This interrupt request from clock synchronous serial function.
Table Interrupt vector addresses priority Interrupt source Reset interrupt INT2 interrupt INT1 interrupt Timer interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer interrupt Timer interrupt Timer interrupt Serial interrupt Multi-master I2C-BUS interface interrupt INT3 interrupt instruction interrupt Priority Vector addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF8 FFF516, FFF4 FFF316, FFF2 FFF116, FFF0 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFDF16, FFDE16 Active edge selectable Non-maskable (software interrupt) Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
f(XIN)/4096 interrupt This interrupt occurs regularly with f(XIN)/4096 period. output control register "0." Multi-master I2C-BUS interface interrupt This interrupt related multi-maseter C-BUS interface. instruction interrupt This software interrupt least significant priority. does have corresponding interrupt enable bit, affected interrupt disable flag (non-maskable).
Interrupt request Interrupt enable
Interrupt disable flag
instruction Reset
Interrupt request
Fig. Interrupt control
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt request register (IREQ1 address 00FC16) Timer interrupt request Timer interrupt request Timer interrupt request Timer interrupt request interrupt request VSYNC interrupt request Multi-master C-BUS interface interrupt request INT3 interrupt request
Interrupt request register (IREQ2 address 00FD16) INT1 interrupt request INT2 interrupt request Serial interrupt request f(XIN)/4096 interrupt request this "0."
interrupt request issued Interrupt request issued
Interrupt control register (ICON1 address 00FE16) Timer interrupt enable Timer interrupt enable Timer interrupt enable Timer interrupt enable interrupt enable VSYNC interrupt enable Multi-master C-BUS interface interrupt enable INT3 interrupt enable
Interrupt control register (ICON2 address 00FF16) INT1 interrupt enable INT2 interrupt enable Serial interrupt enable this "0." f(XIN)/4096 interrupt enable these bits "0."
Interrupt disabled Interrupt enabled
Interrupt input polarity register address 00F916) these bits "0." INT1 polarity switch Positive polarity Negative polarity INT2 polarity switch Positive polarity Negative polarity INT3 polarity switch Positive polarity Negative polarity this "0."
Fig. Structure interrupt-related registers
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
TIMERS
M37221EF-XXXSP timers: timer timer timer timer timers 8-bit timer with 8-bit timer latch. timer block diagram shown Figure timers count down their divide ratio 1/(n+1), where value timer latch. value timer same time writing count value corresponding timer latch (addresses 00F016 00F316). count value decremented timer interrupt request timer overflow next count pulse after count value reaches "0016".
Timer
Timer select following count sources: f(XIN)/16 f(XIN)/4096 count source timer selected setting timer mode register (address 00F416). Timer interrupt request occurs timer overflow.
reset, timers connected hardware "FF16 automatically timer "0716 timer f(XIN )/16 selected timer count source. internal reset released timer overflow these state, internal clock connected. execution instruction, timers connected hardware "FF16" automatically timer "0716" timer However, f(XIN)/16 selected timer count source. timer mode register (address 00F516 before execution instruction (f(XIN)/16 selected timer count source). internal state released timer overflow these state, internal clock connected. Because this, program starts with stable clock. structure timer-related registers shown Figure
Timer
Timer select following count sources: f(XIN)/16 Timer overflow signal External clock from /TIM2 count source timer selected setting bits timer mode register (address 00F416 When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
Timer
Timer select following count sources: f(XIN)/16 External clock from HSYNC External clock from /TIM3 count source timer selected setting bits timer mode register (address 00F516 Timer interrupt request occurs timer overflow.
Timer
Timer select following count sources: f(XIN)/16 f(XIN)/2 Timer overflow signal count source timer selected setting bits timer mode register (address 00F516 When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Timer mode register (T12M address 00F416)
Timer mode register (T34M address 00F516)
Timer count source selection f(XIN)/16 f(XIN)/4096
Timer count source selection f(XIN)/16 External clock
Timer count source selection Internal clock External clock from P24/TIM2
Timer internal count source selection Timer overflow f(XIN)/16
Timer count stop Count start Count stop
Timer count stop Count start Count stop Timer count stop Count start Count stop
Timer count stop Count start Count stop
Timer internal count source selection f(XIN)/16 Timer overflow
Timer count source selection Internal clock f(XIN)/2
this "0."
Timer external count source selection External clock from P23/TIM3 External clock from HSYNC
Fig. Structure timer-related registers
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Data
1/4096
Timer latch
T12M0 T12M2
Timer T12M4
Timer interrupt request
Timer latch P24/TIM2 T12M1 T12M3 FF16 P23/TIM3 T34M5 Timer latch Timer T34M0 T34M2 0716 Timer latch Timer T34M4 T34M3 Timer interrupt request Timer interrupt request Timer Timer interrupt request
HSYNC
Reset instruction
Selection gate Connected black colored side reset T34M1 T12M Timer mode register T34M Timer mode register
Notes pulse width external clock inputs TIM2 TIM3 needs machine cycles more. When external clock source selected, timers counted rising edge input signal. stop mode wait mode, external clock inputs TIM2 TIM3 cannot used.
Fig. Timer block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
SERIAL
M37221EF-XXXSP built-in serial which either transmit receive 8-bit data serial clock synchronous mode. serial block diagram shown Figure synchronizing clock (SCLK), data pins (SOUT, SIN) also function port serial mode register (address 00DC16) selects whether synchronizing clock supplied internally externally (from 0/SCLK pin). When internal clock selected, bits select whether f(XIN divided selects whether port used serial not. P22/SIN pin, port direction register (address 00C5 "0." operation serial function described below. function serial differs depending clock source; external clock internal clock.
Data Frequency divider
1/16
Synchronization circuit
Selection gate Connected black colored side reset. Serial mode register
latch P20/SCLK latch P21/SOUT P22/SIN SM5: (Note) Serial shift register (Address 00DD16) Serial counter Serial interrupt request
Note: When data serial register (address 00DD16), register functions serial shift register.
Fig. Serial block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Internal clock-the serial counter during write cycle into serial register (address 00DD16), transfer clock goes forcibly. each falling edge transfer clock after write cycle, serial data output from SOUT pin. Transfer direction selected serial mode register. each rising edge transfer clock, data input from data serial register shifted bit. After transfer clock counted times, serial counter becomes transfer clock stops "H." this time interrupt request "1." External clock-when external clock selected clock source, interrupt request after transfer clock counted times. However, transfer operation does stop, control clock externally. external clock 1MHz less with duty cycle 50%. serial timing shown Figure When using external clock transfer, external clock must held initializing serial counter. When switching between internal clock external clock, switch during transfer. Also, sure initialize serial counter after switching. Notes programming, note that serial counter writing serial register with managing instructions instructions. When external clock used synchronizing clock, write transmit data serial register transfer clock input level.
Serial mode register address 00DC16) Internal synchronizing clock selection bits f(XIN)/4 f(XIN)/16 f(XIN)/32 f(XIN)/64 Synchronizing clock selection External clock Internal clock Serial port selection P20, functions port SCLK, SOUT this "0." Transfer direction selection first first Serial input selection Input signal from Input signal from SOUT
Fig. Structure serial mode register
Synchroninzing clock
Transfer clock Serial register write signal Serial output SOUT Serial input
(Note)
Interrupt request Note When internal clock selected, SOUT high-impedance after transfer completed. Fig. Serial timing (for first)
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Serial Common Transmission/Reception Mode
writing serial mode register, signals SOUT switched internally able transmit receive serial data. Figure shows signals serial common transmission/reception mode. Note: When receiving serial data after writing "FF16" serial register.
P20/SCLK
Clock
P21/SOUT Serial shift register P22/SIN
Serial mode register Fig. Signals serial common transmission/reception mode
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
multi-master I2C-BUS interface circuit serial communications conformed with Philips I2C-BUS data transfer format. This interface, having arbitration lost detection function synchronous function, useful serial communications multi-master. Figure shows block diagram multi-master I2C-BUS interface Table shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists address register, data shift register, clock control register, control register, status register other control circuits.
MULTI-MASTER I2C-BUS INTERFACE
Table Multi-master I2C-BUS interface functions Item Function conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 MHz)
Format
Communication mode
clock frequency
System clock f(XIN)/2 Note: responsible third party's infringement patent rights other rights attributable control function (bits control register address 00DA16) connections between I2C-BUS interface ports (SCL1, SCL2, SDA1, SDA2).
address register
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Address comparator Serial data (SDA) Noise elimination circuit Data control circuit data shift register
circuit Internal data circuit
status register
Serial clock (SCL)
Noise elimination circuit
Clock control circuit
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
10BIT BSEL1 BSEL0
clock control register Clock division
control register System clock counter
Fig. Block diagram multimaster I2C-BUS interface
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
data shift register address 00D716 8-bit shift register store receive data write transmit data. When transmit data written into this register, transferred outside from synchronization with clock, each time one-bit data output, data this register shifted left. When data received, input this register from synchronization with clock, each time one-bit data input, data this register shifted left. data shift register write enable status only when control register (address 00DA16 "1." counter reset write instruction data shift register. When both status register (address 00D916 "1," output write instruction data shift register. Reading data from data shift register always enabled regardless value. Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Data Shift Register
address register (S0D: address 00D816) Read/write Slave address
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Fig. Structure address register
Clock Control Register
clock control register (address 00DB used control, mode frequency. Bits frequency control bits (CCR0-CCR4) These bits control frequency. Refer Table mode specification (FAST MODE) This specifies mode. When this "0," standard clock mode set. When "1," high-speed clock mode set. (ACK BIT) This sets status when clockV generated. When this "0," return mode make occurrence clock. When "1," non-return mode set. held status occurrence clock. However, when slave address matches address data reception address data "0," automatically made (ACK returned). there mismatch between slave address address data, automatically made "H"(ACK returned). VACK clock: Clock acknowledgement clock (ACK) This specifies mode acknowledgment which acknowledgment response data transmission. When this "0," clock mode set. this case, clock occurs after data transmission. When "1," clock mode master generates clock upon completion each 1-byte data transmission.The device transmitting address data control data releases occurrence clock (make "H") receives generated data receiving device. Note: write data into clock control register during transmitting. data written during transmitting, clock generator reset, that data cannot transmitted normally.
address register (address 00D816 consists 7-bit slave address read/write bit. addressing mode, slave address written this register compared with address data received immediately after START condition detected. Read/write (RBW) used 7-bit addressing mode. 10-bit addressing mode, first address data received compared with contents (SAD6 SAD0 RBW) address register. cleared automatically when stop condition detected. Bits Slave address (SAD0-SAD6) These bits store slave addresses. Regardless 7-bit addressing mode 10-bit addressing mode, address data transmitted from master compared with contents these bits.
Address Register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
clock control register address 00DB16) frequency control bits Refer Table mode specification Standard clock mode High-speed clock mode returned. returned. clock clock clock
Fig. Structure clock control register Table values clock control register frequency Setting value CCR4-CCR0 CCR4 CCR3 CCR2 CCR1 CCR0 frequency 4MHz, unit kHz) Standard clock High-speed clock mode mode Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 83.3 500/CCR value 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 400(Note) 1000/CCR value 34.5 33.3 32.3
control register (address 00DA16) controls data communication format. Bits counter (BC0-BC2) These bits decide number bits next 1-byte data transmitted. interrupt request signal occurs immediately after number bits specified with these bits transmitted. When START condition received, these bits become "0002" address data always transmitted received bits. interface enable (ES0) This enables multimaster interface. When this "0," disable status provided, become high-impedance. When "1," interface enabled. When "0," following performed. "1," (they bits status register address 00D916 Writing data data shift register (address 00D716) disabled. Data format selection (ALS) This decides whether recognize slave addresses. When this "0," addressing format selected, that address data recognized. When match found between slave address address data result comparison when general call (refer "(5) Status Register," received, transmission processing performed. When this "1," free data format selected, that slave addresses recognized. Addressing format selection (10BIT SAD) This selects slave address specification format. When this "0," 7-bit addressing format selected. this case, only high-order bits (slave address) address register (address 00D816) compared with address data. When this "1," 10-bit addressing format selected, bits address register compared with address data. Bits Connection control bits between 2C-BUS interface ports (BSEL0, BSEL1) These bits controls connection between ports ports (refer Figure 17).
Control Register
Note: high-speed clock mode, duty 40%. other cases, duty 50%.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
BSEL0 SCL1/P11 Multi-master I2C-BUS interface BSEL1 SCL2/P12 BSEL0 SDA1/P13 BSEL1 SDA2/P14
BSEL1 BSEL0
control register (S1D address 00DA16) counter (Number transmit/receive bits) I2C-BUS interface enable Disabled Enabled Data format selection Addressing format Free data format Addressing format selection 7-bit addressing format 10-bit addressing format Connection control bits between I2C-BUS interface ports Connection port None SCL1, SDA1 SCL2, SDA2 SCL1, SDA1, SCL2, SDA2
Fig. Connection port control BSEL0 BSEL1
status register (address 00D916) controls I2C-BUS interface status. low-order bits read-only bits highorder bits read written Last receive (LRB) This stores last value received data also used receive confirmation. returned when clock occurs, "0." returned, this "1." Except mode, last value received data input. state this changed from executing write instruction data shift register (address 00D716). General call detecting flag (AD0) This when general call whose address data received slave mode. general call master device, every slave device receives control data after general call. detecting STOP condition START condition. VGeneral call: master transmits general call address "0016" slaves. Slave address comparison flag (AAS) This flag indicates comparison result address data. slave receive mode, when 7-bit addressing format selected, this following conditions. address data immediately after occurrence START condition agrees with slave address stored high-order bits address register (address 00D816). general call received. slave reception mode, when 10-bit addressing format selected, this with following condition. When address data compared with address register bits consisted slave address RBW), first bytes agree. state this changed from executing write instruction data shift register (address 00D716).
Status Register
Fig. Structure control register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Arbitration lostV detecting flag (AL) master transmission mode, when made other device, arbitration judged have been lost, that this "1." same time, "0," that immediately after transmission byte whose arbitration lost completed, "0." case arbitration lost during slave address transmission, reception mode set. Consequently, becomes possible receive recognize slave address transmitted another master device. VArbitration lost: status which communication master disabled. I2C-BUS interface interrupt request (PIN) This generates interrupt request signal. Each time 1-byte data transmitted, state changes from "0." same time, interrupt request signal occurs CPU. synchronization with falling last clock (including clock) internal clock interrupt request signal occurs synchronization with falling bit. When "0," kept state clock generation disabled. Figure shows interrupt request signal generating timing chart. following conditions. Executing write instruction data shift register (address 00D716). When reset conditions which shown below: Immediately after completion 1-byte data transmission (including when arbitration lost detected) Immediately after completion 1-byte data reception slave reception mode, with immediately after completion slave address general call address reception slave reception mode, with immediately after completion address data reception busy flag (BB) This indicates status system. When this "0," this system busy START condition generated. When this "1," this system busy occurrence START condition disabled START condition duplication prevention function (Note). This flag written software only master transmission mode. other modes, this detecting START condition detecting STOP condition. When control register (address 00DA16 reset, flag kept state. Communication mode specification (transfer direction specification bit: TRX) This decides direction transfer data communication. When this "0," reception mode selected data transmitting device received. When "1," transmission mode selected address data control data output onto synchronization with clock generated SCL. When control register (address 00DA16) slave reception mode selected, (transmit) least significant (R/W bit) address data trans-
mitted master "1." When "0," cleared (receive). cleared following conditions. When arbitration lost detected. When STOP condition detected. When occurence START condition disabled START condition duplication preventing function (Note). With when START condition detected. With when non-return detected. reset Communication mode specification (master/slave specification bit: MST) This used master/slave specification data communication. When this "0," slave specified, that START condition STOP condition generated master received, data communication performed synchronization with clock generated master. When this "1," master specified START condition STOP condition generated, also clocks required data communication generated SCL. cleared following conditions. Immediately after completion 1-byte data transmission when arbitration lost detected When STOP condition detected. When occurence START condition disabled START condition duplication preventing function (Note). reset Note: START condition duplication prevention function disables occurence START condition, reset counter output when following condition satisfied: START condition another master device.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
START Condition Generating Method
status register address 00D916) Last receive (Note) Last Last General call detecting flag (Note) general call detected General call detected Slave address comparison flag (Note) Address disagreement Address agreement Arbitration lost detecting flag (Note) detected Detected I2C-BUS interface interrupt request Interrupt request issued interrupt request issued busy flag free busy Communication mode specification bits Slave receive mode Slave transmit mode Master receive mode Master transmit mode Note: These flags read cannot written. Fig. Structure status register status register write signal flag Setup time Hold time Reset time flag When control register (address 00DA16) "1," execute write instruction status register (address 00D916) setting MST, bits "1." Then START condition occurs. After that, counter becomes "0002" byte output. START condition generating timing timing different standard clock mode high-speed clock mode. Refer Figure START condition generating timing diagram, Table START condition/STOP condition generating timing table.
status register write signal flag Setup time Fig. START condition generating timing diagram Setup time Hold time time flag
STOP Condition Generating Method
When control register (address 00DA16) "1," execute write instruction status register (address 00D916) setting "0". Then STOP condition occurs. STOP condition generating timing flag reset timing different standard clock mode high-speed clock mode. Refer Figure STOP condition generating timing diagram, Table START condition/STOP condition generating timing table.
Fig. STOP condition generating timing diagram
Table START condition/STOP condition generating timing table IICIRQ Item Standard clock mode Setup time cycles) Hold time cycles) Set/reset time cycles) flag High-speed clock mode cycles) cycles) cycles)
Fig. Interrupt request signal generating timing
Note: Absolute time MHz. value parentheses denotes number cycles.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
START/STOP Condition Detecting Conditions
START/STOP condition detecting conditions shown Figure Table Only when conditions Table satisfied, START/STOP condition detected. Note: When STOP condition detected slave mode (MST interrupt request signal "IICIRQ" occurs CPU.
Address Data Communication
There address data communication formats, namely, 7-bit addressing format 10-bit addressing format. respective address communication formats described below. 7-bit addressing format meet 7-bit addressing format, 10BIT control register (address 00DA16) "0." first 7-bit address data transmitted from master compared with high-order 7-bit slave address stored address register (address 00D816 time this comparison, address comparison address register (address 00D8 made. data transmission format when 7-bit addressing format selected, refer Figure (2). 10-bit addressing format meet 10-bit addressing format, 10BIT control register (address 00DA16) "1." address comparison made between first-byte address data transmitted from master 7-bit slave address stored address register (address 00D816). time this comparison, address comparison between address register (address 00D8 which last address data transmitted from master made. 10-bit addressing mode, which last address data only specifies direction communication control data also processed address data bit.
release time (START condition) (STOP condition) Fig. START condition/STOP condition detecting timing diagram Setup time Setup time Hold time Hold time
Table START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode 6.5µs cycles) <SCL release 1.0µs cycles) <SCL release time time 3.25µs cycles) Setup time 0.5µs cycles) Setup time 3.25µs cycles) Hold time 0.5µs cycles) Hold time Note: Absolute time MHz. value parentheses denotes number cycles.
Slave address
Data
Data
bits bits bits master-transmitter transmits data slave-receiver
Slave address
Data
Data
bits bits bits master-receiver receives data from slave-transmitter Slave address bits Slave address byte
Data
Data
bits bits bits bits master-transmitter transmits data slave-receiver with 10-bit address Slave address bits Slave address byte Slave address bits
Data
Data bits
bits bits bits bits master-receiver receives data from slave-transmitter with 10-bit address START condition Restart condition STOP condition Read/Write
From master slave From slave master
Fig. Address data communication format
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
When first-byte address data matches slave address, status register (address 00D916) "1." After second-byte address data stored into data shift register (address 00D7 16), make address comparison between second-byte data slave address software. When address data byte matches slave address, address register (address 00D816) software. This processing match 7-bit slave address data, which received after RESTART condition detected, with value address register (address 00D816 data transmission format when 10-bit addressing format selected, refer Figure (4).
transmitted addresses (general call) status register (address 00D916) interrupt request signal occurs. transmitted addresses match address status register (address 00D916 interrupt request signal occurs. cases other than above status register (address 00D9 interrupt request signal occurs. dummy data data shift register (address 00D716). When receiving control data more than byte, repeat step When STOP condition detected, communication ends.
(10) Example Master Transmission
example master transmission standard clock mode, frequency return mode shown below. slave address high-order bits address register (address 00D816) bit. return mode setting "8516 clock control register (address 00DB16). "1016" status register (address 00D916) hold level. communication enable status setting "4816" control register (address 00DA16). address data destination transmission highorder bits data shift register (address 00D716) least significant bit. "F016" status register (address 00D916) generate START condition. this time, byte clock automatically occurs. transmit data data shift register (address 00D716 this time, clock automatically occurs. When transmitting control data more than byte, repeat step "D016" status register (address 00D916). After this, returned transmission ends, STOP condition occurs.
(11) Example Slave Reception
example slave reception high-speed clock mode, frequency kHz, non-return mode using addressing format shown below. slave address high-order bits address register (address 00D816) bit. clock mode setting "2516" clock control register (address 00DB16). "1016" status register (address 00D916) hold level. communication enable status setting "4816" control register (address 00DA16). When START condition received, address comparison made.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
OUTPUT FUNCTION
M37221EF-XXXSP equipped with 14-bit (DA) 8-bit PWMs (PWM0-PWM5). 14-bit resolution with minimum resolution width 0.25µs (for f(XIN) MHz) repeat period 4096µs. PWM0-PWM5 have same circuit structure 8-bit resolution with minimum resolution width (for f(XIN) MHz) repeat period 1024µs. Figure shows block diagram. timing generating circuit applies individual control signals PWM0-PWM5 using f(XIN) divided reference signal.
Operating 14-bit
with 8-bit PWM, output control register (address 00D516) reset, already automatically), that count source supplied. Next, select output polarity output control register (address 00D616). Then, 14-bit outputs from output setting output control register reset, this already automatically) select output. output example 14-bit shown Figure 14-bit divides data latch into low-order bits high-order bits. fundamental waveform determined with high-order 8-bit data level area with length DH("H" level area fundamental waveform) output every short area 64µs minimum resolution width 0.25µs). level area increase interval (tm) determined with low-order 6-bit data "DL." level smaller intervals "tm" shown Table longer than that other smaller intervals repeat period 64t. Thus, rectangular waveform with different width output from pin. Accordingly, output changes unit pulse width changing contents DA-H DA-L registers. length entirely output cannot output, 256/ 256.
Data Setting
When outputting first high-order bits DA-H register (address 00CE16), then low-order bits DA-L register (address 00CF16 When outputting PWM0-PWM5, 8-bit output data PWMi register means addresses 00D016 00D416, 00F6 16).
Transmitting Data from Register circuit
Data transfer from 8-bit register 8-bit circuit executed writing data register. signal output from 8-bit output corresponds contents this register. Also, data transfer from register (addresses 00CE16 00CF16) 14-bit circuit executed writing data DA-L register (address 00CF16 Reading from DA-H register (address 00CE16 means reading this transferred data. Accordingly, possible confirm data being output from output reading register.
Output after Reset
reset output port P00-P05 high-impedance state, contents register circuit undefined. Note that after reset, output undefined until setting register.
Operating 8-bit
following explanation about operation. first, output control register (address 00D516) reset, this already automatically), that count source supplied. PWM0-PWM5 also used pins P00-P0 respectively. PWM0-PWM5, corresponding bits port direction register (output mode). select each output polarity output control register 2(address 00D616 Then, bits output control register (PWM output). waveform output from output pins setting these registers. Figure shows 8-bit timing. cycle composed (28) segments. kinds pulses relative weight each (bits output inside circuit during cycle. Refer Figure (a). 8-bit outputs waveform performed operation pulses corresponding contents bits 8-bit register. Several examples shown Figure (b). kinds output ("H" level area: 0/256 255/256) selected changing contents register. length entirely output cannot output, i.e. 256/256.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table Relation between low-order 6-bit data high-level area increase interval Low-order bits data Area longer than that other 000000 000001 000010 000100 001000 010000 100000
Nothing
Data
DA-H register (Address 00CE16) latch bits)
DA-L register (Note) (Address 00CF16)
14-bit circuit
timing generating circuit
register (Address 00D016)
8-bit circuit
PWM0
PWM1
PWM1 register (Address 00D116)
PWM2
Selection gate Connected black colored side when reset. Pass gate Inside with others. same contents
PWM2 register (Address 00D216)
PWM5 PWM4 PWM3
PWM3 register (Address 00D316)
Port register
Port direction register output control register output control register
PWM4 register (Address 00D416)
PWM5 register (Address 00F616)
Note DA-L register also functions low-order bits latch.
Fig. block diagram
13579
Fig. 8-bit timing
Pulses showing weight each
0016
0116
1816 (24)
FF16 (255)
output 1024 f(XIN) Example 8-bit
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DA-H register.
"2816" DA-L register.
[DA-H register] writing DA-L latch]
[DA-L register]
Undefined
writing DA-L
These bits decide level area fundamental waveform.
level area fundamental waveform
These bits decide smaller interval "tm" which leval area ["H" level area fundamental waveform
Minimum resolution width 0.25
High-order 8-bit value latch
Fundamental waveform 0.25µs!44 14-bit output 8-bit counter
Waveform smaller interval "tm" specified low-order bits 0.25µs!45 0.25µs 14-bit output 8-bit counter
Fundamental waveform smaller interval "tm" which specified low-order bits changed. 0.25µs!44 0.25µs
14-bit output Low-order 6-bit output latch Repeat period 4096µs
Fig. 14-bit output example (f(XIN) MHz)
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
output control register (PW: address 00D516) count source selection Count source supply Count source stop DA/PN4 output selection output output P00/PWM0 output selection output PWM0 output P01/PWM1 output selection output PWM1 output P02/PWM2 output selection output PWM2 output P03/PWM3 output selection output PWM3 output P04/PWM4 output selection output PWM4 output P05/PWM5 output selection output PWM5 output
output control register (PN: address 00D616)
output polarity selection Positive polarity Negative polarity output polarity selection Positive polarity Negative polarity general-purpose output Output Output
Fig. Structure PWM-related registers
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
COMPARATOR
comparator consists 6-bit converter comparator. comparator block diagram shown Figure reference voltage "Vref" conversion bits control register (address 00EF 16). comparison result analog input voltage reference voltage ref" stored control register (address 00EE 16). comparison, corresponding bits direction register ports analog input pins. Write data select analog input pins bits control register write digital value corresponding compared bits control register voltage comparison starts writing control register completed after machine cycles (NOP instruction
control register (AD2: address 00EF16)
converter bits Refer Table
Fig.30. Structure control register
control register (AD1: address 00EE16)
Table Relation between contents control register reference voltage "Vref" control register Reference voltage "Vref" 1/128 3/128 5/128 123/128 125/128 127/128
Analog input selection bits
A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 set.
Storage comparison result Input voltage reference voltage Input voltage reference voltage
Fig. Structure control register
Data
control register
Bits
Comparator control
P15/A-D1/INT3 P16/A-D2 P17/A-D3 P06/INT2/A-D4 P30/A-D5/DA1 P31/A-D6/DA2
control register Analog signal switch Comparator
control register
Switch tree
Resistor ladder
Fig. comparator block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CONVERTER
M37221EF-XXXSP converters with 6-bit resolution. converter block diagram shown Figure conversion performed setting value conversion register. result conversion output from setting output enable port output mode control register (bits address 00CD16). output analog voltage determined with value decimal number) conversion register.
Port output mode control register (P3S: address 00CD16) output structure selection CMOS output N-channel open-drain output
output structure selection CMOS output N-channel open-drain output output enable input/output output output enable input/output output
output does build buffer, connect external buffer when driving low-impedance load.
Fig. Structure port output mode register
conversion register (DA1: address 00DE16) conversion register (DA2: address 00DF16) conversion bits Refer Table this "0."
Table Relation between contents conversion register output voltage conversion register Output voltage 0/64 1/64 2/64 61/64 62/64 63/64VCC
Fig. Structure converter register
Data
conversion register (address 00DE16)
conversion register (address 00DF16)
Resistor ladder output enable P30/A-D5/DA1
Resistor ladder output enable P31/A-D6/DA2
Fig. converter block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DISPLAY FUNCTIONS
dots
Outline Display Functions
Table outlines display functions M37221EF-XXXSP. M37221EF-XXXSP incorporates display control circuit characters lines. display controlled control register. kinds characters displayed. colors specified each character kinds colors displayed screen. combination colors obtained using each output signal Characters displayed dots configuration obtain smooth character patterns (refer Figure 35). following shows procedure display characters screen. Write display character code display RAM. Specify display color using color register. Write color register which display color display RAM. Specify vertical position using vertical position register. Specify character size using character size register. Specify horizontal position using horizontal position register. Write display enable designated block display flag control register. When this done, display starts according input VSYNC signal. display circuit extended display mode. This mode allows multiple lines lines more) displayed screen interrupting display each time line displayed rewriting data block which display terminated software. Figure shows structure display control register. Figure shows block diagram display control circuit.
dots
Fig. display character configuration
control register (CC: address 00EA16)
Table Outline display functions Parameter Number display characters structure Kinds characters Kinds character sizes Kinds colors Color Coloring unit Display expansion Raster coloring Character background coloring Functions characters lines dots (refer Figure kinds kinds screen: kinds, maximum kinds character Possible (multiline display) Possible (maximum kinds) Possible character unit, screen kinds, maximum kinds)
All-blocks display control (Note) All-blocks display All-blocks display Block display control Block display Block display Block display control Block display Block display P10/OUT2 switch OUT2 Note: Display controlled logical product (AND) between all-blocks display control each block display control bit.
Fig. Structure control register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
OSC1
OSC2
HSYNC VSYNC
(Address 00EA16) control register (Addresses 00E116, 00E216) Display oscillation circuit
Vertical position registers
(Address 00E416) Character size register Display position control circuit (Address 00E016) Horizontal position register (Address 00E516) Border selection register
Display control circuit
display bits (Addresses 00E616 00E916)
display bits
Color registers
Shift register bits
Shift register bits
(Address 00EC16) Output circuit port control register Data OUT1 OUT2
Fig. Block diagram display control circuit
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Display Position
display positions characters specified units called "block." There blocks, block block characters displayed each block (refer Memory Display). display position each block both horizontal vertical directions software. display position horizontal direction selected blocks common from 64-step display positions units oscillating cycle display). display position vertical direction each block selected from 128-step display positions units scanning lines.
Block displayed after display block completed (refer Figure (a)). Accordingly, display block starts during display block only block displayed. Similarly, when multiline display, block displayed after display block completed (refer Figure (b)). vertical position specified from 128-step positions scanning lines step) each block setting values "0016" "7F16" bits vertical position register (addresses 00E116 00E216). Figure shows structure vertical position register.
(HR) Block
Block
Example when each block separated
Block Block
display
Block (second) display
Example when block overlaps with block
Fig. Display position
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
display position vertical direction determined counting horizontal sync signal (HSYNC this time, starts count rising edge (falling edge) HSYNC signal from after about machine cycle rising edge (falling edge) VSYNC signal. interval from rising edge (falling edge) VSYNC signal rising edge (falling edge) HSYNC signal needs enough time machine cycles more) avoiding jitter. polarity HSYNC VSYNC signals select with port control register (address 00EC16). details. refer Output Control. Note: When bits port control register (address 00EC16) (negative polarity), vertical position determined counting falling edge HSYNC signal after rising edge VSYNC control signal microcomputer (refer Figure 39).
Vertical position registers (CV1 address 00E116) (CV2 address 00E216)
Vertical display start positions steps from "0016" "7F16" Fig. Structure vertical position register
VSYNC signal input
0.125 0.25 [µs] f(XIN) 8MHz)
VSYNC control signal microcomputer Period counting HSYNC signal (Note) HSYNC signal input
horizontal position common blocks, steps (where step being display oscillation period) values "3F16 bits horizontal position register (address 00E0 16). structure horizontal position register shown Figure
Horizontal position register address 00E016)
count When bits port control register (address 00EC16) (negative polarity) Note: generate falling edge HSYNC signal near rising edge VSYNC control signal microcomputer avoid jitter.
Horizontal display start positions steps from "0016" "3F16" step 4TC)
Fig. Structure horizontal position register
Fig. Supplement explanation display position
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Character Size
size characters displayed from sizes each block. character size register (address 00E416) character size. character size block specified using bits character size register; character size block specified using bits Figure shows structure character size register. character size selected from sizes: minimum size, medium size large size. Each character size determined number scanning lines height (vertical) direction oscillating cycle display (TC) width (horizontal) direction. minimum size consists scanning line] [1TC]; medium size consists scanning lines] large size consists scanning lines] [3TC Table shows relation between values character size register character sizes.
Character size register address 00E416)
Character size block selection bits Minimum size Medium size Large size set. Character size block selection bits Minimum size Medium size Large size set. Fig. Structure character size register
Minimum
Medium
Large
Horizontal display start position Fig. Display start position each character size (horizontal direction) Table Relation between values character size register character sizes values character size register CSn1 CSn0 Character size Minimum Medium Large Width (horizontal) direction oscillating cycle display This available Height (vertical) direction scanning lines
Note: display start position horizontal direction affected character size. other words, horizontal display start position common blocks even when character size varies with each block (refer Figure 43).
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Memory Display
There types display memory display (addresses 1000016 11FFF16) used store character data (masked) display (addresses 060016 06B716) used specify colors characters displayed. following describes each type display memory.
display (addresses 1000016 11FFF16)
display contains pattern data characters displayed. characters stored this actually displayed, necessary specify them writing character code inherent each character (code determined based addresses display ROM) into display RAM. character code list shown Table
display capacity bytes. Since bytes required character data, stores kinds characters. display space broadly divided into areas. [vertical dots] [horizontal (left side) dots] data display characters stored addresses 1000016 107FF16 1100016 117FF [vertical dots] [horizontal (right side) dots] data display characters stored addresses 10800 10FFF16 1180016 11FFF16 (refer Figure 44). Note however that high-order bits data written addresses 10800 10FFF16 11800 11FFF16 must writing data "FX16").
10XX016 11XX016
10XXF16 11XXF16
10XX016 80016 11XX016 80016
10XXF16 80016 11XXF16 80016
Fig. Display character stored data
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table Character code list (partially abbreviated) Character code 0016 Character data storage address Left dots lines Right dots lines 1000016 1080016 1000F16 1080F 1001016 1081016 1001F16 1081F 1002016 1082016 1002F16 1082F 10030 1083016 1003F16 1083F16 107E016 107EF16 107F016 107FF16 1100016 1100F16 11010 1101F16 117D016 117DF16 117E016 117EF16 117F016 117FF16 10FE016 10FEF16 10FF016 10FFF16 1180016 1180F 1181016 1181F16 11FD016 11FDF16 11FE016 11FEF16 11FF016 11FFF16
display (addresses 060016 06B716
display allocated addresses 060016 06B716 divided into display character code specification part display color specification part each block. Table shows contents display RAM. example, display character position (the left edge) block write character code address 060016 write color register low-order bits (bits address 068016 color register written here color registers which color displayed advance. details color registers, refer Color Registers. structure display shown Figure
0116
0216
0316 7E16
7F16
8016
8116 FD16
FE16
FF16
Table Contents display Block Display position (from left) character character character 22nd character 23rd character 24th character used character character character 22nd character 23rd character 24th character Character code specification 060016 060116 060216 061516 061616 061716 061816 061F 062016 062116 062216 063516 063616 063716 Color specification 068016 068116 068216 069516 069616 069716 069816 069F16 06A016 06A116 06A216 06B516 06B616 06B716
Block
Block
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Block [Character specification] character 060016 24th character 061716 Character code Specify characters ("0016" "FF16") [Color specification] character 068016 24th character 069716 Color register specification Specifying color register Specifying color register Specifying color register Specifying color register Block [Character specification] character 062016 24th character 0637 Character code Specify characters ("0016" "FF16") [Color specification] character 06A016 24th character 06B716 Color register specification Specifying color register Specifying color register Specifying color register Specifying color register
Fig. Structure display
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Color Registers
color displayed character specified setting color registers (CO0 CO3: addresses 00E6 00E9 then specifying that color register with display RAM. There color outputs; using combination these outputs, possible 23-1 (when output) colors. However, since only color registers available, colors disabled time. outputs using bits color register. used specify whether character output blank output. Figure shows structure color register.
Color register (CO0 address 00E616) (CO1 address 00E716) (CO2 address 00E816) (CO3 address 00E916)
signal output selection character output Character output signal output selection character output Character output signal output selection character output Character output signal output (background) selection (Note background color output Background color output OUT1 signal output control (Notes 1,2) Character output Blank output signal output (background) selection background color output Background color output signal output (background) selection (Note background color output Background color output Notes When "1," there output same character border output from OUT1 pin. "0." When only "0," there output from OUT2 pin.
Fig. Structure color registers
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table Display example character background coloring (when green character blue background color) Border selection register Color register output COn7 COn6 COn5 COn4 COn3 COn2 COn1 Green output (Note Same output character
Video signal character color (green) mixed.
output
OUT1 output
Character output
OUT2 output
(Note
output
Green output Same output Video signal character color (green) mixed. character Green output Blank output
image character background displayed.
Blank output
output (Note
Green Background color Blank output Blue
image character background displayed.
output (Note
output Border output (Black)
Border output (Black)
Green output (Note
Video signal character color (green) mixed.
Green output Blank output Black
image character background displayed.
output (Note
Background color border
Border output (Black) Blank output
Green output (Note
Blue
image character background displayed.
Notes1 When COn4 "1," there output same character border output from OUT1 pin. COn4 "0." When only "0," there output from OUT2 pin. :The portion which character dots displayed mixed with video signal. :The wavy-lined arrows Table denote video signals.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Character Border Function
border clock dot) equivalent size added character displayed both horizontal vertical directions. border output from pin. this case, color register (character output). Border specified units block using border selection register (address 00E5 16). Figure shows structure border selection register. Table shows relationship between values border selection register character border function.
Border selection register address 00E516)
Block OUT1 output border selection Same output output Border output Block OUT1 output border selection Same output output Border output
Fig. Example border
Fig. Structure border selection register
Table Relationship between value border selection register character border function Border selection register MDn0 Functions Ordinary Example output output output output output
Border including character
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Multiline Display
M37221EF-XXXSP ordinarily display lines screen displaying blocks different vertical positions. addition, display lines using interrupts. interrupt request occurs point which display each block been completed. other words, when scanning line reaches point display position (specified vertical position registers) certain block, character display that block starts, interrupt occurs point which scanning line exceeds block. Note: interrupt does occur display when block displayed. other words, block display with display control control register (address 00EA 16), interrupt request does occur (refer Figure 49).
Block display) Block display) Block display) Block display)
"CRT interrupt request" "CRT interrupt request" "CRT interrupt request" "CRT interrupt request"
display (CRT interrupt request occurs block display)
Block display) Block display) Block (off display) Block (off display)
"CRT interrupt request" "CRT interrupt request" "CRT interrupt request" "CRT interrupt request"
display (CRT interrupt request does occur block display)
Fig. Timing interrupt request
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Output Control
output pins OUT1 also function ports P52, P53, corresponding port direction register (address 00CB16 specify these pins output pins, specify general-purpose port pins. OUT2 also function port control register (address 00EA specify port P10, specify OUT2 pin. input polarity signals HSYNC VSYNC output polarity signals OUT1 specified with bits port control register (address 00EC specify positive polarity; specify negative polarity. structure port control register shown Figure port control register (CRTP address 00EC16) HSYNC input polarity switch Positive polarity Negative polarity VSYNC input polarity switch Positive polarity Negative polarity output polarity switch Positive polarity Negative polarity OUT2 output polarity switch Positive polarity Negative polarity OUT1 output polarity switch Positive polarity Negative polarity signal output switch signal output MUTE signal output signal output switch signal output MUTE signal output signal output switch signal output MUTE signal output
Raster Coloring Function
entire screen (raster) colored setting bits port control register. Since each pins switched raster coloring output, raster colors obtained. pins have been MUTE signal output, raster coloring signal output part except no-raster colored character Figure character "O") during horizontal scanning period. This ensures that character colors with raster color. this case, MUTE signal output from OUT1 pin. example which magenta character character displayed with blue raster coloring shown Figure
"RED" "BLUE"
Fig. Structure port control register
HSYNC OUT1 Signals across
Fig. Example raster coloring
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
(10) Clock Display
clock display used display, possible select following types. Main clock supplied from Main clock supplied from divided Clock from supplied from pins OSC1 OSC2. Clock from ceramic resonator quartz-crystal oscillator supplied from pins OSC1 OSC2. This clock display selected each block clock selection register (address 00ED16). When selecting main clock, oscillation frequency MHz.
clock selection register address 00ED16) Display clock selection bits Refer Table
these bits "0."
Fig. Structure clock selection register
Table value clock selection register clock display Functions clock display supplied connecting across pins OSC1 OSC2. oscillation frequency Since main clock used clock display, oscillation frequency limited. Because f(XIN) this, character size width (horizontal) direction also limited. this case, pins OSC1 oscillation frequency OSC2 also used input ports respectively. f(XIN)/1.5 clock display supplied connecting following across pins OSC1 OSC2. ceramic resonator only display feedback resistor quartz-crystal oscillator only display feedback resistor (Note)
Note: necessary connect other ceramic resonator quartz-crystal oscillator across pins XOUT.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CORRECTION FUNCTION
This correct data (64K bytes). addresses blocks) corrected, program correction stored memory correction. memory correction bytes blocks. Block addresses 02C0 02DF16 Block addresses 02E0 02FF16 address data corrected into correction address. When value counter matches data address correction address, main program branches program correction stored memory correction. return from program correction main program, code operand instruction (total bytes) needed program correction. case that blocks used series, above instruction needed block correction function controlled correction enable register. Notes Specify first address code address) each instruction correction address. instruction (total bytes) return from main program program correction. same correction address blocks
correction address (high-order) 021716 correction address (low-order) 021816
correction address (high-order) 021916 correction address (low-order) 021A16
Fig. correction addresses
correction enable register (RCR address 021B16) Block enable Disabled Enabled Block enable Disabled Enabled
these bits
Fig. Structure correction enable register
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
RESET CIRCUIT
M37221EF-XXXSP reset according sequence shown Figure starts program from address formed using content address FFFF16 high-order address content address FFFE16 low-order address, when RESET held level more while power source voltage oscillation quartz-crystal oscillator
ceramic resonator stable then returned level. internal state microcomputer reset shown Figure example reset circuit shown Figure reset input voltage must kept less until power source voltage surpasses
RESET Internal RESET SYNC Address Data 32768 count clock cycle (Note
FFFE
FFFF
ADH,
Reset address from vector table
Notes f(XIN) relation f(XIN) question mark indicates undefined state that depends previous state. Immediately after reset, timer timer connected hardware. this time, "FF16" timer "0716" timer Timer counts down with f(XIN)/16, reset state released timer overflow signal.
Fig. Reset sequence Poweron Power source voltage
Reset input voltage
M51953AL
RESET
M37221EF-XXXSP Fig. Example reset circuit
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address
Port direction register Port direction register Port direction register Port direction register Port Port direction register
Contents register 0016 0016 0016
control register port control register clock selection register control register control register Timer Timer Timer Timer Timer mode register Timer mode register Interrupt input polarity register mode register Interrupt request register Interrupt request register Interrupt control register Interrupt control register correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register Processor status register Program counter
Address Contents register (00EA16) (00EC16) (00ED16) (00EE16) (00EF (00F016) (00F116) (00F216) (00F316) (00F416) (00F516) (00F916) (00FB (00FC16) (00FD16) (00FE (00FF16) (021716) (021816) (021916) (021A16) (021B16) (PS) (PCH)
(00C1 (00C3 (00C5 (00C7 (00CA16) (00CB16)
FF16 0716 FF16 0716 0016 0016 0016 0016
Contents addressFFFF16 Contents addressFFFE16
Port output mode control register (00CD16) DA-L register output control register output control register address register status register control register clock control register Serial mode register conversion register conversion register Horizontal register Vertical position register Vertical position register Character size register Border selection register Color register Color register Color register Color register
(00CF16) (00D5 (00D6 (00D8 (00D9 (00DA16) (00DB16) (00DC16) (00DE16) (00DF (00E016) (00E116) (00E216) (00E416) (00E516) (00E616) (00E716) (00E816) (00E916)
0016 0016 0016 0016
Note contents other registers undefined reset, their initial values.
Undefined
Unused
Fig. Internal state microcomputer reset
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Ports P00-P05, N-channel open drain output Direction register Ports P00-P0 Data Port latch Note: Each port also used below: P00-P0 PWM0-PWM5
Ports P30, Direction register CMOS output Ports Note: Each port also used below: OUT2 SCL1 SCL2 SDA1 SDA2 A-D2 A-D3 SCLK SOUT TIM3 TIM2 A-D6/DA2
Data
Port latch
A-D1/INT3 A-D5/DA1
Ports P06, N-channel open-drain output Direction register Ports P06, Data Port latch Note: Each port also used below: INT2/A-D4 INT1
Fig. block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
HSYNC, VSYNC Schmidt input Internal circuit HSYNC, VSYNC
D-A, OUT1, OUT2
CMOS output D-A, OUT1, OUT2 Note: Each also used below: OUT1 OUT2
Internal circuit
Fig. block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CLOCK GENERATING CIRCUIT
built-in clock generating circuit shown Figure When instruction executed, internal clock stops level. same time, timers connected hardware "FF16" timer "0716" timer Select f(XIN)/16 timer count source (set timer mode register before execution instruction). besides, timer timer interrupt enable bits disabled ("0") before execution instruction). oscillator restarts when external interrupt accepted, however, internal clock keeps level until timer overflows. Because this allows time oscillation stabilizing when ceramic resonator quartz-crystal oscillator used. When instruction executed, internal clock stops level oscillator continues running. This wait state released when interrupt accepted (Note). Since oscillator does stop, next instruction executed once. When returning from stop wait state, accept interrupt, corresponding interrupt enable before executing instructions. Note: wait mode, following interrupts invalid. VSYNC interrupt interrupt f(XIN)/4096 interrupt Timer interrupt using f(XIN)/4096 count source Timer interrupt using P24/TIM2 input count source Timer interrupt using P23/TIM3 input count source Timer interrupt using f(XIN)/2 count source Multi-master I2C-BUS interface interrupt circuit example using ceramic resonator quartz-crystal oscillator) shown Figure circuit constants accordance with resonator manufacture's recommended values. circuit example with external clock input shown Figure Input clock pin, open XOUT pin. 37221EFXXXSP
Fig. Ceramic resonator circuit example
M37221EF-XXXSP
External oscillation circuit
Fig. External clock input circuit example
Interrupt request Reset
instruction
Interrupt disable flag
Reset
Selection gate Connected black colored side reset. T34M Timer mode register
instruction
instruction
Internal clock
T34M0 T34M2
Timer
Timer
XOUT
Fig. Clock generating circuit block diagram
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DISPLAY OSCILLATION CIRCUIT
display clock oscillation circuit built-in clock oscillation circuits, that clock display obtained simply connecting ceramic resonator quartz-crystal oscillator circuit across pins Select clock display with bits clock selection register (address 00ED16).
ADDRESSING MODE
memory access reinforced with kinds addressing modes. Refer SERIES <Software> User's Manual details.
MACHINE INSTRUCTIONS
There machine instructions. Refer SERIES <Software> User's Manual details.
PROGRAMMING NOTES
OSC1 OSC2
Fig. Display oscillation circuit
AUTO-CLEAR CIRCUIT
When power source supplied, auto-clear function performed connecting following circuit RESET pin.
divide ratio timer 1/(n+1). Even though instructions executed immediately after interrupt request bits modified program), those instructions only valid contents before modification. least instruction cycle needed (such NOP) between modification interrupt request bits execution instructions. After instructions executed decimal mode), instruction cycle (such NOP) needed before SEC, CLC, instruction executed. instruction needed immediately after execution instruction. order avoid noise latch-up, connect bypass capacitor directly between pin-V pin- CNVSS using thick wire.
Circuit example
RESET
Circuit example
RESET
Note Make level change from point which power source voltage exceeds specified voltage. Fig. Auto-clear circuit example
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
PROM Programming Method
built-in PROM Time PROM version (blank) builtin EPROM version read programmed with general-purpose PROM programmer using special programming adapter. Product M37221EFSP Name Programming Adapter PCA7408
PROM Time PROM version (blank) tested screened assembly process following processes. ensure proper operation after programming, procedure shown Figure recommended verify programming.
Programming with PROM programmer
Screening (Caution) (150°C hours)
Verification with PROM programmer
Functional check target device
Caution screening temperature higher than storage temperature. Never expose 150°C exceeding hours. Fig. Programming testing Time PROM version
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol Input voltage Input voltage Parameter Power source voltage CNVSS P00-P0 7,P10-P17, 0-P27 P30-P3 OSC1, XIN, HSYNC, VSYNC, RESET P06, P10-P1 -P27, P30-P3 OUT1, D-A, XOUT, OSC2 P00-P0 OUT1, 0-P17 P20-P2 P30, OUT1, P10, P15-P1 P20-P2 -P32, 1-P1 0-P0 4-P2 Conditions voltages based VSS. Output transistors off. Ratings -0.3 -0.3 -0.3 Unit
Output voltage
-0.3
IOL1
Output voltage Circuit current Circuit current
-0.3 (Note (Note
IOL2 IOL3 IOL4 Topr Tstg
Circuit current Circuit current Circuit current Power dissipation Operating temperature Storage temperature
(Note (Note (Note
RECOMMENDED OPERATING CONDITIONS unless otherwise noted)
Symbol VIH1 Parameter Power source voltage (Note During CPU, operation Power source voltage input voltage P00-P07,P10-P1 0-P27, 0-P34, SIN, SCLK, HSYNC, VSYNC, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) input voltage P00-P07,P10-P1 0-P27, 0-P34 input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) input voltage SYNC, VSYNC, RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK average output current (Note OUT1, D-A, P10-P1 P20-P2 P30, average output current (Note OUT1, D-A, P06, P10, P15-P17, 0-P27 P30-P3 average output current (Note 1-P14 average output current (Note 0-P05 average output current (Note 4-P27 Oscillation frequency (for operation) (Note Oscillation frequency (for display) (Note OSC1 Input frequency TIM2, TIM3 Input frequency SCLK Input frequency SCL1, SCL2 Min. 0.8VCC Limits Typ. Max. Unit
VIH2 VIL1 VIL2 VIL3 IOL1 IOL2 IOL3 IOL4 fCPU fCRT fhs1 fhs2 fhs3
0.7VCC
Notes total current that flows must (max.). total input current (IOL1 IOL2 IOL3) must less. total average input current ports -P27 must less. Connect more capacitor externally across power source pins VCC-VSS reduce power source noise. Also connect more capacitor externally across pins -CNVSS. quartz-crystal oscillator ceramic resonator oscillation circuit.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
ELECTRIC CHARACTERISTICS (VCC f(XIN) MHz, unless otherwise noted)
Symbol Parameter Power source current System operation Test conditions f(XIN) Stop mode output voltage output voltage f(XIN) Limits Min. Typ. Max. Unit
output voltage output voltage -VT- Hysteresis Hysteresis (Note)
OUT1, D-A, P10-P1 -0.5 P20-P27, OUT1, D-A, P00-P0 P10, P15-P1 -P23, P30-P32 P11-P14 P24-P27 RESET HSYNC, VSYNC, TIM2, TIM3, INT1, INT2, INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK 10.0
IIZH
input leak current RESET, 0-P0 P10-P1 P20-P27, 0-P34 HSYNC, VSYNC input leak current RESET, 0-P0 P10-P1 P20-P27, 0-P34 HSYNC, VSYNC output leak current P00-P05 switch connection resistor (between SCL1 SCL2, SDA1 SDA2)
IIZL
IOZH
Note: P06, P23, have hysteresis when these pins used interrupt input pins timer input pins. P20-P22 have hysteresis when these pins used serial pins. P11-P14 have hysteresis when these pins used multi-master I2C-BUS interface pins.
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
COMPARATOR CHARACTERISTICS
Symbol Resolution Parameter
(VCC f(XIN) MHz, unless otherwise noted) Test conditions Limits Min. Typ. Max. Unit bits
Absolute accuracy Note: When 5/64
CONVERTER CHARACTERISTICS
Symbol Resolution Absolute accuracy Setting time Output resistor Parameter
(VCC f(XIN) MHz, unless otherwise noted) Test conditions Limits Min. Typ. Max. Unit bits
MULTI-MASTER I2C-BUS LINE CHARACTERISTICS
Symbol tBUF tHD:STA tLOW tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO free time Hold time START condition period clock Rising time both signals Data hold time period clock Falling time both signals Data set-up time Set-up time repeated START condition Set-up time STOP condition Parameter Standard clock mode High-speed clock mode Min. 1000 Max. Min. 20+0.1Cb 20+0.1Cb Max. Unit
Note: total capacitance line
tHD:STA tSU:STO
tBUF tLOW
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
Fig. Definition diagram timing multi-master I2C-BUS
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
PACKAGE OUTLINE
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3
Sep. First Edition 1996 H-DF319-B Editioned Committee editing Mitsubishi Semiconductor Data Book Published Mitsubishi Electric Corp., Semiconductor Division This book, parts thereof, reproduced form without permission Mitsubishi Electric Corporation. ©1996 MITSUBISHI ELECTRIC CORPORATION Printed Japan
REVISION DESCRIPTION LIST
Rev. First Edition
M37221EF-XXXSP, M37221EFSP DATA SHEET
Revision Description Rev. date 9708 971130 980731
Information about copywright note, revision number, release data added (last page). Correct note (P54)
(1/1)
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