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SAM87RI PRODUCT FAMILY Samsung's SAM87RI family 8-bit single-chip


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KS86C6204/C6208/P6208 (Preliminary Spec)
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. dual address/data architecture large number bit- nibble-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations. Many SAM87RI microcontrollers have external interface that provides access external memory other peripheral devices.
KS86C6204/C6208/P6208 MICROCONTROLLER
KS86C6204/C6208/P6208 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM87RI core. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C6204 bytes program memory on-chip KS86C6208 bytes. Using SAM87RI design approach, following peripherals were integrated with SAM87RI core: configurable ports pins) 8-bit timer/counter with operating modes Full speed function/ KS86C6204/C6208/P6208 versatile microcontroller with Full speed capabilities that used wide range general purpose applications. especially suitable controller that require capabilities available 32-pin SDIP package.
KS86C6204/C6208 microcontroller also available (One Time Programmable) version, KS86P6208. KS86P6208 microcontroller on-chip 8K-byte one-time-programmable EPROM instead masked ROM. KS86P6208 comparable KS86C6204/C6208, both function configuration.
KS86C6204/C6208/P6208 (Preliminary Spec)
FEATURES
SAM87RI core General programmable ports pins total)
Memory 8-Kbyte (KS86C6208/P6208) internal program memory (ROM) 4-Kbyte (KS86C6204) internal program memory (ROM) 256-bytes
Slave only IIC-bus Serial Peripheral Interface
Universal Service (USB) with Compatible specification Rev1.0 upstream port, downstream ports (including internal downstream port) Serial interface engine (SIE) Packet decoding/generation generation checking NRZI encoding/decoding bit-stuffing Embedded function with three endpoint bytes FIFOs) Built-in voltage regulator
Instruction instructions IDLE STOP instructions added powerdown modes
Instruction Execution Time fOSC
Interrupts interrupt sources with vector, each source pending level, vector interrupt structure Operating Voltage Range Oscillator Frequency 12MHz 5.25 Operating Temperature Range 40°C 85°C
Package Types 32-pin SDIP
Timer/Counter 8-bit basic timer watchdog function programmable oscillation stabilization function three selectable internal clock frequency 8-bit timer/counter with clock sources (Capture Interval modes)
KS86C6204/C6208/P6208 (Preliminary Spec)
BLOCK DIAGRAM
P0.0-P0.7
P1.0-P1.
Port
Port
VDD1, DD2, TEST
RESET XOUT CLKOUT OCREF DP0,DM0 DP1,DM1 DP2,DM2 DP3,DM3 DP4,DM4 DP5,DM5 PWREN1 PWREN2 PWREN3 PWREN4 OCDET1 OCDET2 OCDET3 OCDET4 Main
Basic Timer
Port Interrupt Control
Timer Module SAM87RI
T0CAP
IIC-BUS Device Control 4/8-KByte 256-Byte Register
Figure 1-1. KS86C6204/C6208/P6208 Simplified Block Diagram
KS86C6204/C6208/P6208 (Preliminary Spec)
ASSIGNMENTS
VSS1 XOUT TEST P0.0/TOCAP/CLKOUT P0.1/TOCAP/OCREF
RESET
P0.4/OCDET4 P0.3/OCDET3 P0.2/OCDET2 OCDET1 PWREN1 P0.5/PWREN2 P0.6/PWREN3 P0.7/PWREN4
KS86C6204 KS86C6208
(Top View)
VDD1 P1.1/SCL P1.0/SDA 3.3VOUT VDD2
Figure 1-2. KS86C6204/C6208 Assignment Diagrams
KS86C6204/C6208/P6208 (Preliminary Spec)
DESCRIPTIONS
Table 1-1. KS86C6204/C6208/P6208 Descriptions Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 OCDET1 OCDET2 OCDET3 OCDET4 PWREN1 PWREN2 PWREN3 PWREN4 DP0,DM0 DP1,DM1 DP2,DM2 DP3,DM3 DP4,DM4 VDD1,VDD2 VSS1,VSS2 3.3VOUT XIN, XOUT Type Description General-purpose, 8-bit port. P0.0 used timer capture input pin, clock output pin. P0.1 used over current reference analog input timer capture input pin. Circuit Type Numbers 27,28 25,26 21,22 19,20 17,18 24,32 1,23 Share Pins T0CAP/CLKOUT OCREF/T0CAP OCDET2 OCDET3 OCDET4 PWREN2 PWREN3 PWREN4 P1.0 P1.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
General-purpose, 2-bit port. Clock Data Pins 4-bit over current detection input pins. Analog input digital input selected OCDET1. OCDET2-OCDET4 used normal ports. 4-bit N-channel open-drain output power enable pins.
These pins upstream four downstream pins.
Digital power pins output Pass Filter System clock input output pins (crystal/ceramic oscillator, external clock source) System reset Factory test input normal operation, factory test mode
RESET
TEST
KS86C6204/C6208/P6208 (Preliminary Spec)
CIRCUITS
Data Other Function Pull-up Resistor Open-Drain Output Disable RESET Noise Filter Input Data
Figure 1-4. Circuit Type
Figure 1-6. Circuit Type
Data Other Function
Digital
Output Disable Input Data Noise Filter
Analog
OCREF
T0CAP
Figure 1-5. Circuit Type
Figure 1-7. Circuit Type
KS86C6204/C6208/P6208 (Preliminary Spec)
Pull-up Resistor Pull-Up Enable
Output Disable Noise Filter Digital Input Analog OCREF Input
Figure 1-8. Circuit Type
Data
Output
Figure 1-9. Circuit Type
KS86C6204/C6208/P6208 (Preliminary Spec)
Only upstream port
RxDP
RxDM
TxDP Speed (only downstream port) TxDM
Only Downstream Port
Figure 1-10. Circuit Type
KS86C6204/C6208/P6208 (Preliminary Spec)
ELECTRICAL DATA
OVERVIEW
ELECTRICAL DATA
this section, following KS86C6204/C6208 electrical characteristics presented tables graphs: Absolute maximum ratings D.C. electrical characteristics D.C. electrical characteristics module Full speed source electrical characteristics speed source electrical characteristics Differential input sensitivity over entire common mode range Data signal rise fall time A.C. electrical characteristics capacitance Oscillator characteristics Oscillation stabilization time Clock timing measurement points Comparator electrical characteristics Stop mode release timing when initiated RESET
ELECTRICAL DATA
KS86C6204/C6208/P6208 (Preliminary Spec)
Table 13-1. Absolute Maximum Ratings Parameter Supply voltage Input voltage Symbol Output voltage Output current high Operating temperature Storage temperature TSTG Conditions Type (n-channel, open drain) port pins except output ports active pins active Output current active Total current except IOL3 Total current type (n-channel, open drain) Rating
Unit
Table 13-2. D.C. Electrical Characteristics 5.25 Parameter Input high voltage Input voltage Symbol VIH1 VIH2 VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions input pins except VIH2 XIN, XOUT input pins except VIL2 XIN, XOUT
RESET
Unit
5.25 Type (P0.5-0.7) 5.25 ports except
VOH2
13-2
KS86C6204/C6208/P6208 (Preliminary Spec)
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued) 5.25 Parameter Output voltage Symbol VOL1 Conditions 5.25 8mA, Type (P0.5-0.7), Type (PWREN1) 6mA, Type D-1, 6mA, SCL, inputs except ILIH2, ILIH3 VDD, XOUT only VDD, only inputs except ILIL2, ILIL3 RESET XOUT only only VOUT output pins except ILOH2 VOUT Type RESET only Normal operation mode, 12-MHz clock Idle mode; 12-MHz clock Stop mode; Stop mode Stop mode, VDDDR Unit
VOL3 VOL4 Input high leakage current ILIH1 ILIH2 ILIH3 Input leakage current ILIL1 ILIL2 ILIL3 Output high leakage current Output leakage current Pull-up resistors ILOH1 ILOL
Supply current (note)
IDD1 IDD2 IDD3
Data retention supply voltage Data retention supply current
VDDDR IDDDR
NOTE: Supply current include drawn internal pull-up resistors external loads output.
13-3
ELECTRICAL DATA
KS86C6204/C6208/P6208 (Preliminary Spec)
Table 13-3. D.C. Electrical Characteristics Module Parameter Supply Voltage: Powered (Host HUB) port Bus-powered port Leakage Current: Hi-Z state data line leakage Input Levels: Differential input sensitivity Differential common mode range Single ended receiver threshold Output Levels: Static output Static output high Terminations: pull-up resistor root port pull-up resistor downstream port Symbol VBUS VBUS Conditions (notes 3.3V (DP) (DM) figure 13-1 Includes range 4.75 4.40 5.25 5.25 Unit
3.6V (1.5
1.425 14.25
1.575 15.75
Table 13-4. Full Speed Source Electrical Characteristics Parameter Driver Characteristics: Transition time: Rise time Fall time Rise/fall time matching Output signal crossover voltage Driver output resistance Data source timings: Full speed data rate Symbol Conditions (notes (5)(6), figure 13-1 50pF 50pF (TR/TF) Steady state drive Ave. rate (12Mb/s 0.25%) Unit
TRFM VCRS ZDRV TDRATE
11.97
12.03
Mb/s
NOTES: voltages measured from local ground potential, unless otherwise specified. timing capacitive load (CL) ground 50pF, unless otherwise specified. Full speed timings have 1.5K pull-up 2.8V data line. speed timings have 1.5K pull-up 2.8V data line. Measured from data signal. There should smooth transitions between rising falling edges (monotonic).
13-4
KS86C6204/C6208/P6208 (Preliminary Spec)
ELECTRICAL DATA
Table 13-5. Speed Source Electrical Characteristics Parameter Driver Characteristics: Transition time: Rise time Fall time Rise/fall time matching Output signal crossover voltage Data Source Timings: speed data rate TDRATE Ave. rate (1.5Mb/s 1.5%) 1.4775 1.5225 Mb/s TRFM VCRS (5)(6), figure 13-2 50pF 350pF 50pF 350pF (TR/TF) Symbol Conditions (notes Unit
NOTES: voltages measured from local ground potential, unless otherwise specified. timing capacitive load (CL) ground 50pF, unless otherwise specified. Full speed timings have 1.5K pull-up 2.8V data line. speed timings have 1.5K pull-up 2.8V data line. Measured from data signal. There should smooth transitions between rising falling edges (monotonic).
Minimum Differential Sensitivity (volts)
Common Mode Input Voltage (volts) Figure 13-1. Differential Input Sensitivity over Entire Common Mode Range
13-5
ELECTRICAL DATA
KS86C6204/C6208/P6208 (Preliminary Spec)
Rise Time
Fall Time
Differential Data Lines
Full Speed: 20ns L=50pF Speed: 75ns L=50pF, 300ns L=350ns
Figure 13-2. Data Signal Rise Fall Time
Table 13-6. A.C. Electrical Characteristics 5.25 Parameter Noise Filter Symbol Conditions Unit tNF1H, tNF1L Type Delay) tNF2
RESET only Delay)
NF1L NF1H
Table 13-7. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Conditions MHz; unmeasured pins connected Unit
13-6
KS86C6204/C6208/P6208 (Preliminary Spec)
ELECTRICAL DATA
Table 13-8. Oscillator Characteristics Oscillator Main crystal Main ceramic (fOSC) Clock Circuit
Test Condition Oscillation frequency 5.25
Unit
XOUT
External clock (main)
XOUT
Oscillation frequency 5.25
Table 13-9. Oscillation Stabilization Time 5.25 Oscillator Main Crystal Main Ceramic External Clock input high level width (tXH, tXL) 1/24 Test Condition 5.25 Unit
Figure 13-3. Clock Timing Measurement Points
13-7
ELECTRICAL DATA
KS86C6204/C6208/P6208 (Preliminary Spec)
Table 13-10. Comparator Electrical Characteristics 5.25 Parameter Input voltage range Reference voltage range Input voltage accuracy Input leakage current Symbol VREF VCIN ICIN, IREF Conditions Unit
Internal Reset Operation Stop Mode Data Retention Mode
Idle Mode (Basic Timer Active)
VDDDR
RESET
Execution Stop Instruction
Normal Operating Mode
WAIT
twait same 4096 1/Fose
Figure 13-4. Stop Mode Release Timing When Initiated RESET
13-8
KS86C6204/C6208/P6208 (Preliminary Spec)
MECHANICAL DATA
OVERVIEW
14.00
MECHANICAL DATA
KS86C6204/C6208 available 42-pin SDIP package (Samsung: 32-SDIP-400) 44-pin package (44-QFP-1010B). Package dimensions shown Figures 13-1 13-2.
0-15
15.24
42-SDIP-
39.50 3.50
39.10
0.50 (1.77) 1.00 1.778
0.51MIN
5.08MAX
NOTE: Dimensions millimeters.
Figure 14-1. 32-Pin SDIP Package Mechanical Data (32-SDIP-400
3.30
0.250+0.1
MECHANICAL DATA
KS86C6204/C6208/P6208 (Preliminary Spec)
NOTES
14-2
KS86C6204/C6208/P6208 (Preliminary Spec)
KS86P6208
OVERVIEW
KS86P6208
KS86P6208 single-chip CMOS microcontroller (One Time Programmable) version KS86C6204/C6208 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS86P6208 fully compatible with KS86C6204/C6208, both function configuration. Because simple programming requirements, KS86P6208 ideal evaluation chip KS86C6204/C6208.
XOUT /TEST P0.0/TOCAP/CLKOUT P0.1/T0CAP/OCREF
RESET
RESET
P0.4/OCDET4 P0.3/OCDET3 P0.2/OCDET2 OCDET1 PWREN1 P0.5/ PWREN2 P0.6/PWREN3 P0.7/PWREN4
KS86P6208
(Top View)
VDD1/VDD P1.1/SCL/ SCLK P1.0/SDA/ SDAT U33V VDD2/VDD VSS2 /VSS
Figure 15-1. KS86P6208 Assignments (32-SDIP Package)
KS86P6208
KS86C6204/C6208/P6208 (Preliminary Spec)
Table 15-1. Descriptions Pins Used Read/Write EPROM Main Chip Name P1.0 (Pin Name SDAT During Programming Function Serial data pin. Output port when reading input port when writing. assigned Input push-pull output port. Serial CLocK pin. Input only pin. Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option) Chip initialization Logic power supply pin. should tied during programming.
P1.1 (Pin TEST
SCLK VPP(TEST)
RESET
RESET
32/1 24/23
VDD1 VSS1 VDD2 VSS2
Table 15-2. Comparison KS86P6208 KS86C6204/C6208 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS86P6208 Kbyte EPROM 5.25 (TEST)=12.5V SDIP User Program time SDIP Programmed factory KS86C6204/C6208 Kbyte mask
OPERATING MODE CHARACTERISTICS When 12.5 supplied (TEST) KS86P6208, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 15-3 below. Table 15-3. Operating Mode Selection Criteria
REG/
ADDRESS
EPROM read
MODE
(RESET) 12.5 12.5 12.5
(A15-A0) 0000H 0000H 0000H 0E3FH EPROM program EPROM verify EPROM read protection
NOTE: means level; means High level.
15-2
KS86C6204/C6208/P6208 (Preliminary Spec)
KS86P6208
D.C. ELECTRICAL CHARACTERISTICS Table 15-4. D.C. Electrical Characteristics 5.25 Parameter Supply Current
(note)
Symbol IDD1 IDD2 IDD3
Conditions Normal operation mode, clock Idle mode; clock Stop mode;
Unit
15-3
KS86P6208
KS86C6204/C6208/P6208 (Preliminary Spec)
START
Address= First Location
=5V, PP=12.5V
Program Pulse
Increment
FAIL
Verify Byte
Verify Byte
FAIL
Last Address
Increment Address
FAIL
Compare Byte
PASS
Device Failed
Device Passed
Figure 15-2. Programming Algorithm
15-4

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