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TAS3002

Digital Audio Processor With Codec

TAS3002
Digital Audio Processor With Codec
Data Manual
Digital Audio: Digital Speakers
SLAS307B
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
Contents
A-1 A-1 A-3 A-3 A-4 A-4 A-6 A-7 A-8 A-8 A-10 A-10 A-10 A-11 A-12 A-13 A-13 A-14
List of Illustrations
List of Tables
1 Introduction
1.1 Description
The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU through the I2C slave port or from an external EEPROM through the I2C master port. The TAS3002 device also has an integrated 24-bit stereo codec with two I2C-selectable, single-ended inputs per channel. The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass, high-pass, and low-pass). The internal loudness contour algorithm can be controlled and programmed with an I2C command. Dynamic range compression / expansion (DRCE) is programmable through the I2C port. The system designer can set the threshold, energy estimation time constant, compression ratio, and attack and decay time constants. The TAS3002 device supports 13 serial interface formats (I2S, left justified, right justified) with data word lengths of 16, 18, 20, or 24 bits. The sampling frequency (fS) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface formats are listed and described in Section 2.1. The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock for the PLL is provided by an external master clock (MCLK) of 256fS or 512fS, or a 256fS crystal. The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass, treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal microcontroller.
1.2 Features
· · · · · · · · Programmable seven-band parametric equalization Programmable digital volume control Programmable digital bass and treble control Programmable dynamic range compression / expansion (DRCE) Programmable loudness contour / dynamic bass control Configurable serial port for audio data Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of the codec (analog input). These channels are controlled by I2C commands. Three output data channels: Left and right data go through equalization bass, treble, DRCE, and volume to SDOUT1 SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer channel. The output of the ADC is available for additional processing. Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation Serial I2C master / slave port that allows: - - Downloading of control data to the device externally from the EEPROM or an I2C master Controlling other I2C devices
Two I2C-selectable, single-ended analog input stereo channels Equalization bypass mode Single 3.3-V power supply Power down without reloading the coefficients Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz Master clock frequency of 256fS or 512fS Can have crystal input to replace MCLK. Crystal input frequency is 256fS. Six GPI terminals for volume, bass, treble up / down control, mute, and selection of equalization filters
1.3 Functional Block Diagram
Figure 1-1 is a block diagram showing the major functions of the TAS3002.
AVSS(REF) VREFM
VREFP VRFILT
AINRP AINRM RINA RINB Voltage Reference Analog Supplies Digital Supplies
AINRP
AINRM AINLP AINLM LINA LINB AINLP 24-Bit Stereo ADC SDOUT0
AINLM ALLPASS INPA Controller GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 L+R I2C Control CS1 SDA SCL L+R SDOUT2 32-Bit Audio Signal Processor SDOUT1 32-Bit Audio Signal Processor VCOM AOUTL AOUTR 24-Bit Stereo DAC
Control
SDATA Control
OSC / CLK Select
LRCLK / O
CLKSEL
XTALI / MCLK XTALO
MCLKO
Figure 1-1. TAS3002 Block Diagram
SDIN1 SDIN2
1.4 Terminal Assignments
Figure 1-2 shows the terminal locations on the package outline, along with the signal name assigned to each terminal.
PACKAGE (TOP VIEW)
LINB AINLP AINLM V REFM V REFP AINRM AINRP RINB RINA AOUTL VCOM AOUTR
NC AVDD NC GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 ALLPASS SDOUT1 SDOUT0
Figure 1-2. TAS3002 Terminal Assignments
1.5 Terminal Functions
Table 1-1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type, and a description of the terminal function. Table 1-1. TAS3002 Terminal Functions
TERMINAL NAME AINLM AINLP AINRM AINRP ALLPASS AOUTL AOUTR AVDD AVSS AVSS(REF) NO. 46 47 43 42 27 39 37 35 4 3 I / O I I I I I O O I I I DESCRIPTION ADC left channel analog input (antialias capacitor) ADC left channel analog input (antialias capacitor) ADC right channel analog input (antialias capacitor) ADC right channel analog input (antialias capacitor) Logic high bypasses equalization filters Left channel analog output Right channel analog output Analog power supply (3.3 V) Analog voltage ground Analog ground voltage reference
XTALI / MCLK XTALO SCL SDA DVDD DVSS LRCLK / O SCLK / O IFM / S SDIN1 SDIN2 SDOUT2
Table 1-1. TAS3002 Terminal Functions (Continued)
2 Audio Data Formats
2.1 Serial Interface Formats
The TAS3002 device works in master or slave mode. In the master mode, terminal 21 (IFM / S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI / MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be connected to XTALI / MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK / O) and 20 (SCLK / O) becoming outputs to drive slave devices. In the slave mode, IFM / S is tied low. LRCLK / O and SCLK / O are inputs and the interface operates as a slave device requiring externally supplied MCLK, LRCLK (left / right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates. If the 512fS MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate of 512fS must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied. In both cases, an LRCLK of 64SCLK must be supplied. · · MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart. If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified, and left justified. Table 2-1 indicates how the 13 options are selected using the I2C bus and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS. Additionally, the 16-bit mode operates at 32fS. Table 2-1. Serial Interface Options
MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 MCR BIT (6) 0 1 1 1 1 1 1 1 1 1 1 1 1 MCR BIT (5-4) 00 00 01 10 00 01 10 00 01 10 00 01 10 MCR BIT (1-0) 00 00 00 00 01 01 01 10 10 10 11 11 11 SERIAL INTERFACE SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0 16-bit, 32fS 16-bit, left justified, 64fS 16-bit, right justified, 64fS 16-bit, I2S, 64fS 18-bit, left justified, 64fS 18-bit, right justified, 64fS 18-bit, I2S, 64fS 20-bit, left justified, 64fS 20-bit, right justified, 64fS 20-bit, I2S, 64fS 24-bit, left justified, 64fS 24-bit, right justified, 64fS 24-bit, I2S, 64fS
Figure 2-1 through Figure 2-3 illustrate the relationship between the SCLK, LRCLK, and the serial data I / O for the different interface protocols.
2.2 Digital Output Modes
The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.
MSB-First, Right-Justified, Serial-Interface Format
The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2-1 shows the following characteristics of this protocol: · · · · Left channel is transmitted when LRCLK is high. The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK. The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK. If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SDOUT
Left Channel
Right Channel
Figure 2-1. MSB-First, Right-Justified, Serial-Interface Format
I2S Serial-Interface Format
The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2-2 shows the following characteristics of this protocol: · · · · Left channel is transmitted when LRCLK is low. SDIN is sampled with the rising edge of SCLK. SDOUT is transmitted on the falling edge of SCLK. If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SDOUT
Left Channel
Right Channel
Figure 2-2. I2S Serial-Interface Format
MSB-Left-Justified, Serial-Interface Format
The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2-3 shows the following characteristics of this protocol: · · · Left channel is transmitted when LRCLK is high. The SDIN data is justified to the leading edge of the LRCLK. The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SDOUT
Left Channel
Right Channel
Figure 2-3. MSB-Left-Justified, Serial-Interface Format
2.3 Switching Characteristics
td(SLR)
tf(SCLK)
LRCLK
td(SDOUT) SDOUT1 SDOUT2 SDOUT0 tsu(SDIN)
td(SLR)
th(SDIN) SDIN1 SDIN2
Figure 2-4. For Right- / Left-Justified and I2S Serial Protocols
3 Analog Input / Output
The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or B analog input is accomplished by setting a bit in the analog control register (ACR) by an I2C command. Additionally, the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).
3.1 Analog Input
Figure 3-1 shows the technique and components required for analog input to the TAS3002 device. The maximum input signal must not exceed 0.7 Vrms. Selection of the above component values gives a frequency response from 20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.
2 1200 pF 0.47 µF 1 1 0.47 µF AINRP AINRP AINRM RINA RINB Voltage Reference
2 1200 pF 0.47 µF 1 1 0.47 µF AINLP AINLM LINA LINB
AINRM 24-Bit Stereo ADC AINLP
AINLM
Input Select Command From Internal Controller
Figure 3-1. Analog Input to the TAS3002 Device
3.2 Analog Output
3.2.1 Direct Analog Output
The full scale analog output from the TAS3002 device is 0.707 Vrms. It is referenced to VCOM which is approximately 1.5 Vdc. VCOM must be decoupled with the network shown in Figure 3-2.
Analog Output (Adjust Capacitors for Desired Low Frequency Response) AOUTR
24-Bit DAC
VCOM + 10 µF AOUTL 0.1 µF
Figure 3-2. VCOM Decoupling Network
Analog Output With Gain
Because the maximum analog output from the TAS3002 device is 0.707 Vrms, the output level can be increased by using an external amplifier. The circuit shown in Figure 3-3 boosts the output level to 1 Vrms (when it has a gain of 1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is improved also.
C4 Analog Output (Adjust Capacitors for Desired Low Frequency Response) - C1 + 24-Bit DAC VCOM 10 µF AOUTL + 0.1 µF +5 Op Amp / 2 AGND C5 C3 TLV2362 or Equilvalent
AOUTR
TLV2362 or Equilvalent
Figure 3-3. Analog Output With External Amplifier
Reference Voltage Filter
Figure 3-4 shows the TAS3002 reference voltage filter.
4 AVSS
3 AVSS(REF)
2 VRFILT
45 VREFM VREFP
TAS3002
Figure 3-4. TAS3002 Reference Voltage Filter
4 Audio Control / Enhancement Functions
4.1 Soft Volume Update
The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute). The volume is adjustable by downloading a gain coefficient through the I2C interface in 4.16 format-4 bits for the integer and 16 bits for the fractional part. Table A-5 lists the 4.16 coefficients converted into dB for the range of -70 dB to 18 dB with 0.5-dB step resolution. Right and left channel volumes can be unganged and set to different values. This feature implements a balance control. Volume is changed by writing the desired value into the volume control registers. This is done by asserting the volume-up or volume-down GPI terminal (see Section 7.6.1) for a limited range of volume control. Alternatively, volume control settings can be sent to the TAS3002 device over the I2C bus.
4.2 Software Soft Mute
Soft mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down over a duration of 2048fS samples to a final output of 0 (- infinity dB). Soft mute can be enabled by either asserting the mute GPI terminal (see Section 7.6.1) or sending a mute command over the I2C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on.
4.3 Input Mixer Control
The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers. See Figure 4-1 for a functional block diagram of the input mixer. The values loaded into these registers are in 4.20 format-4 bits for the integer and 20 bits for the fractional part. Table A-8 lists the 4.20 numbers converted into dB for the range of -70 dB to 18 dB, although any positive 4.20 number may be used. To mute any of the channels, 0s are loaded into the respective mixer control register. Mixer controls are updated instantly and can cause audible artifacts for large changes in setting when updated dynamically outside of the fast load mode therefore, it is desirable to use fast load in conjunction with the soft-volume mode. SDIN1, SDIN2, and the ADC output can be mixed with a user-selectable gain for each channel. The gain control registers are represented in 4.20 format.
Left Channel Mix Coefficients I2C Register Address 08h
7 Biquad Filters
Soft Volume DRCE
7 Biquad Filters
Soft Volume DRCE
Figure 4-1. TAS3002 Mixer Function
4.4 Mono Mixer Control
4.5 Treble Control
The treble gain level may be adjusted within the range of 15 dB to -15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading treble codes (shown in Table A-6) into the treble gain register. Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see Section 7.6.1). The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate. The gain values for treble control can be found in Section A.4.
4.6 Bass Control
The bass gain level can be adjusted within the range of 15 dB to -15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading bass codes (shown in Table A-7) into the bass frequency control register. Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see Section 7.6.1). Bass control is a shelf filter with a corner frequency of 250 Hz at a 48-kHz sample rate. The gain values for bass control can be found in Section A.5.
4.7 De-Emphasis Mode (DM)
De-emphasis is implemented in the DAC and is software controlled. De-emphasis is valid at 44.1 kHz and 48 kHz. To enable de-emphasis, values are written into the analog control register via the I2C command. See Section 4.8 for analog control register operation. Figure 4-2 illustrates the frequency response of the de-emphasis mode.
De-Emphasis
Response (dB)
3.18 (50 µs) Frequency (kHz)
10.6 (15 µs)
Figure 4-2. De-Emphasis Mode Frequency Response
4.8 Analog Control Register (40h)
The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC, and analog power down. An I2C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h.
Table 4-1. Analog Control Register Description
4.9 Dynamic Loudness Contour
Volume
Biquad
Figure 4-3. Dynamic Loudness Contour Block Diagram The loudness contour is activated by sending an activation command via I2C from an external device. Optionally, a contour gain command can be sent by an external device to provide tracking with the system volume control.
Loudness Biquads
Loudness biquad filters for the left and right channels are independently programmable via I2C. Their subaddresses are 21h and 22h, respectively. The digital filters are written as five 24-bit (4.20) hex coefficients for each channel.
Loudness Gain
Loudness gain values for the left and right channels are independently programmable via I2C. Their subaddresses are 23h and 24h, respectively. The gain values are written as one 4.20 hex coefficient for each channel.
Loudness Contour Operation
When the frequency of the loudness contour is determined, a digital filter must be developed. Then, the gain of the filter is determined. These values are placed in the storage area of the system controller (microcontroller) and sent to the TAS3002 device when it is desired to activate the loudness contour. If it is necessary to change the frequency or gain of the contour, new gain and filter coefficients are sent by the system controller. This function is performed normally when the volume control is changed (that is, more volume, less contour). The gain of the loudness contour filter then tracks the volume control. The loudness contour biquad filters are provided in addition to the seven equalization biquad filters. See Section A.7 for programming instructions.
4.10 Dynamic Range Compression / Expansion (DRCE)
The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE receives data, and affects scaling after the volume / loudness block. As shown in Figure 4-4, the DRCE is applied after the volume / loudness control block as a DRCE scale factor. The DRCE must be adjusted such that the signal does not reach the hard limit value. However, if the signal does reach the maximum digital value, the saturation logic serves as a hard limiter that does not allow the signal to extend beyond the available range.
(Analog in From ADC)
Dynamic Range Control
(7) 2nd Order IIR Filters (Parametric Equalization)
Bass / Treble (Tone)
Soft Volume / (DRCE Scaling) Loudness
Saturation Logic
(Right Channel Mixer)
Figure 4-4. TAS3002 Digital Signal Processing Block Diagram The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code of Table A-9. Each instruction downloaded must be eight bytes. If only one byte is changed, all eight bytes must be transmitted. The first two bytes remain the same for every instruction, however the last six bytes can be programmed using hexadecimal values from the corresponding tables referred to in Section A.8. With high compression ratios and fast attack times available, this function is suited for a commercial killer in a television set application.
4.11 AllPass Function
This function is enabled by setting terminal 27 (ALLPASS) on the TAS3002 device to 1. When asserted, the internal equalization filters are set into AllPass (flat) mode. When this terminal is reset to 0, the equalization filters are returned to the equalization that was in use before the terminal was asserted. In AllPass mode, the bass and treble controls are still functional. This function is frequently used for headphones. When the headphone plug is inserted into its jack, a switched contact in the jack enables the AllPass function. The AllPass function also can be activated by writing a 1 to bit 2 of the analog control register.
4.12 Main Control Register 1 (01h)
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and serial-port word length. It is accessed via I2C with the address 01h. MCR1 (01h)
Table 4-2. Main Control Register 1 Description
Reserved W
4.13 Main Control Register 2 (43h)
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR2 register contains the bits associated with the AllPass function and the download of bass and treble control information, and it is accessed via I2C with the address 43h. MCR2 (43h)
Table 4-3. Main Control Register 2 Description
5 Filter Processor
5.1 Biquad Block
The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in Figure 5-1. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has independent coefficients.
Biquad 0 Biquad 1 .. Biquad 6
Figure 5-1. Biquad Cascade Configuration
Filter Coefficients
The filter coefficients for the TAS3002 device are downloaded through the I2C port and loaded into the biquad memory space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is processed by the biquad block and then converted into analog waveforms by the DAC. Alternatively, filters can be loaded by asserting terminals on the GPI port.
Biquad Structure
The biquad structure that is used for the parametric equalization filters is as follows: b ) b 1z 1 ) b 2z 2 H(z) + 0 a 0 ) a 1z 1 ) a 2z 2 NOTE: a0 is fixed at value 1 and is not downloadable. The coefficients for these filters are represented in 4.20 format-4 bits for the integer part and 20 bits for the fractional part. In order to transmit them over I2C, it is necessary to separate each coefficient into three bytes. The upper 4 bits of byte 2 comprise the integer part the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part. The filters can be designed using the automatic loudspeaker equalization program (ALE) or a script running under MatLab named Filtermaker. Both of these tools are available from Texas Instruments.
6 I2C Serial Control Interface
6.1 Introduction
Control parameters for the TAS3002 device can be loaded from an I2C serial EEPROM by using the TAS3002 master interface mode. If no EEPROM is found, the TAS3002 device becomes a slave device and loads from another I2C master interface. Information loaded into the TAS3002 registers is defined in Appendix A. The I2C bus uses terminals 16 (SDA for data) and 15 (SCL for clock) to communicate between integrated circuits in a system. These devices can be addressed by sending a unique 7-bit slave address plus R / W bit (1 byte). All compatible devices share the same terminals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used to set the high level on the bus. The TAS3002 device operates in standard mode up to 100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF. Furthermore, the TAS3002 device supports a subset of the SMBus protocol. When it is attached to the SMBus, then byte, word, and block transfers are supported. The SMBus NAK function is not supported and care must be taken with the sequence of the instructions sent to the TAS3002 device. Additionally, the TAS3002 device operates in either master or slave mode therefore, at least one device connected to the I2C bus must operate in master mode.
6.2 I2C Protocol
The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. Figure 6-1 shows these conditions. These start and stop conditions for the I2C bus are required by standard protocol to be generated by the master. The master must also generate the 7-bit slave address and the read / write (R / W) bit to open communication with another device and then wait for an acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 6-1 shows a generic data transfer sequence.
7-Bit Slave Address R / W 8-Bit Register Data for Address (N) 8-Bit Register Data for Address (N+1) 8-Bit Register Data for Address (N+2)
SCL Start Stop
Figure 6-1. Typical I2C Data Transfer Sequence
Table 6-1 lists the definitions used by the I2C protocol. Table 6-1. I2C Protocol Definitions
DEFINITION Transmitter Receiver Master Slave Multimaster Arbitration Synchronization The device that sends data The device that receives data The device that initiates a transfer, generates clock signals, and terminates the transfer The device addressed by the master More than one master can attempt to control the bus at the same time without corrupting the message. Procedure to ensure the message is not corrupted when two masters attempt to control the bus. Procedure to synchronize the clock signals of two or more devices DESCRIPTION
6.3 Operation
The 7-bit address for the TAS3002 device is 0110 10X R / W where X is a programmable address bit, set by terminal 7 (CS1). Combining CS1 and the R / W bit, the TAS3002 device can respond to four different I2C addresses (two read and two write). These two addresses are licensed I2C addresses that do not conflict with other licensed I2C audio devices. In addition to the 7-bit device address, subaddresses direct communication to the proper memory location within the device. A complete table of subaddresses and control registers is provided in Appendix A. For example, to change bass to 10-dB gain, Section 6.3.1 shows the data that is written to the I2C port: Table 6-2. I2C Address Byte Table
I2C ADDRESS BYTE 68h 69h 6Ah 6Bh A6-A1 011010 011010 011010 011010 CS1 (A0) 0 0 1 1 R / W 0 1 0 1
Start
Write Cycle Example
Slave Address R / W FUNCTION Start Slave address R / W A Subaddress (treble control register) Data (0 dB gain) Stop A Subaddress A Data A Stop
NOTE: Table is for serial data (SDA) serial clock (SCL) is not shown but conditions apply as well.
Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle. For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow otherwise, the cycle is incomplete and errors occur.
TAS3002 I2C Readback Example
I2C Start
Send I2C address byte with read bit set to 1 (LSB set equal to 1) Receive Byte 0 Send Ack Receive Byte 1 Send Ack Receive Byte 2 Send Ack Receive Byte 3 Send Ack Receive Byte 4 Send Ack Receive Byte 5 Send Ack Receive Byte 6 (if an ACK is sent after byte 6 it locks up the TAS3002) I2C Stop
Where: · · · · I2C Start is a valid I2C Start command. Receive Byte is a valid I2C command which reads a byte from the TAS3002. Send Ack is a a valid I2C command that informs the TAS3002 that a byte has been read. I2C Stop is a valid I2C Stop command.
NOTES: 1. The TAS3002 will appear to be locked up, if a Send Ack is issued after the last byte read. It is required to send an I2C Stop command after the last byte and not a Send Ack. 2. The I2C Start and I2C Stop commands are the same for both I2C read and I2C write.
I2C Wait States
The TAS3002 device performs interpolation algorithms for its volume and tone controls. If a volume or tone change is sent to the part via I2C, the command sent after the volume or tone (bass and treble) change causes an I2C wait state to occur. This wait state lasts from 41 ms to 231 ms, depending on the system clock rate, the command sent, and, in the case of bass or treble, the amount of the change. Secondly, if a long series of commands is sent to the TAS3002 device, it may occasionally create a short wait state on the order of 150 µs to 300 µs while it loads and processes the commands. When a sample rate of 32 kHz is used, longer wait states can occur, occasionally up to 15 ms. The preferred way to take care of wait states is to use an I2C controller that recognizes wait states. During the wait state period, it stops sending data over I2C. If this function is not available on the system controller, fixed delays can be implemented in the system software to ensure that the controller is not trying to send more data while the TAS3002 device is busy. Sending I2C data while the TAS3002 device is busy causes errors and locks up the device, which must then be reset.
Table 6-3 gives typical values of the wait states that can be expected with the various functions of the part: Table 6-3. I2C Wait States
SYSTEM SAMPLING FREQUENCY 32 kHz Volume Bass Treble DRC on Mixer Loudness Equalization 62 ms 231 ms 231 ms 300 µs None None 15 ms 44.1 kHz 49 ms 167 ms 167 ms 300 µs None None 190 µs 48 kHz 41 ms 153 ms 153 ms 300 µs None None 300 µs Can occur with each filter 0 to -18 dB 0 to -18 dB Comment Not dependent on size of change
6.4 SMBus Operation
The TAS3002 device supports a subset of the SMBus protocol. With proper programming techniques, it is possible to use the SMBus to set up the TAS3002 device.
Block Write Protocol
The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. This operation signals the TAS3002 device that the next byte is the SMBus byte-count byte. The next byte after the byte count is then entered into the device as the first byte of data.
Write Byte Protocol
The TAS3002 device also supports the SMBus write byte protocol. Writing to the main control register (MCR), bass, and treble registers requires using the byte write protocol. To send a command using this protocol, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. The next byte after the command byte is then entered into the device as the first byte of data.
Wait States
If separate I2C / SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This happens when the device is busy while performing smoothing operations and changing volume, bass, and treble. The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed according to the SMBus specification (worst case 200 ms). The following is a possible bus wait state scenario:
CODE Start 68 84 06 01 00 Wait 00 01 00 00 Stop
ACTUAL Start 68 84 06 01 00 00 01 00 00 Stop If the master does not recognize bus waiting or if the master times out on a long wait, the master must not send consecutive I2C / SMBus commands without a time interval of 200 ms between transactions.
TAS3002 SMBus Readback
SMBus Command Byte SENT RECEIVED Start Start 69h 07h Byte Count xxh aah Byte Count 07h ddh Stop ddh ddh ddh ddh ddh Stop
NOTE: Use read sequence defined in 6.3.2
7 Microcontroller Operation
The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform housekeeping and interface functions. Additionally, it handles I2C communication and general purpose input functions.
7.1 General Description
7.2 Power-Up / Power-Down Reset
7.2.1 Power-Up Sequence
An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 7-1. On reset, SCL and SDA go to a high-impedance state. If the I2C address is set to 68h, approximately 400 µs after RESET returns to a 1, the device sends a one-byte query via I2C to look for an EEPROM. If an EEPROM is found, the TAS3002 becomes an I2C master otherwise, it becomes an I2C slave. When using address 68h in the slave mode, an external master must wait until after the EEPROM query or else bus contention and improper operation occur. I2C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.
Reset
The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the following process: · Clears all the RAM memory content
Clears all the registers in the circuits Purges the codec Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low Initializes the equalization parameters to AllPass filters Sets the digital audio interface to the I2S 18-bit mode Sets the bass / treble to 0 dB Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in Sets the volume to -40 dB Turns off all enhancement features (DRCE, etc.) Reads the I2C address. If the address is 68h, the device reads its EEPROM. It is possible to load the user-defined bass / treble data and break points (optional). If there is no data, the device loads default bass / treble delta and break points from ROM. If the address is 6Ah, the device puts the I2C interface in slave mode and waits for input.
Reset Circuit
10 k 6 0.1 µF DVSS RESET
TAS3002
Fast Load Mode
Codec Reset
During initialization, the output of the codec is disabled. Throughout reset and initialization, the output of the DAC is muted to prevent extraneous noise being sent to the system output. Data from the ADC and other internal processing is purged so that when reset / initialization is complete, only valid inputs are sent to the system output.
7.3 Power-Down Mode
The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control registers and equalization programming of the device are stored in the device. To enter power-down mode: 1. Assert the power-down control signal (1) 2. Set the serial audio input clocks to 0 The TAS3002 device goes into power-down mode. To exit the power-down mode: 1. Assert RESET (logic 0) 2. Restart the serial audio clocks 3. Wait for a delay of 1.0 ms (to allow the PLL to lock) 4. Negate the power-down control signal (logic 0) 5. Negate RESET (logic 1) The device then returns to the state it was in before power down (resumes normal operation).
Power-Down Timing Sequence
RESET
LRCLK
SDATA Power-Down Mode 1 ms Normal Operation
Figure 7-2. Power-Down Timing Sequence In power-down mode, the TAS3002 device typically consumes less than 1 mA.
7.4 Test Mode
Terminal 9 (TEST) is tied low in normal operation. This function is reserved for factory test and must not be asserted.
7.5 Internal Interface
Figure 7-3 shows the flow chart of the interface between the microcontroller and its peripheral blocks.
7.6 GPI Terminal Programming
During initialization, the microcontroller fetches a control byte from its EEPROM or receives a command from I2C.
GPI Interface
The six GPI terminals are programmed to operate as indicated in Table 7-1.
Table 7-1. GPI Terminal Programming
Initially (after reset), the TAS3002 GPI is set to control volume, bass, and treble. Simultaneously setting GPI bits 1 and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization. To return to volume, bass, and treble control, simultaneously set GPI terminals 2 and 3 low for 1 second. When a GPI terminal is activated, the TAS3002 device echoes its function over I2C to a TAS3001 device mapped to address 6Ah. Therefore, a system with two audio equalization chips can be implemented without the need for a microcontroller.
GPI Architecture
The GPI provides simple but flexible input port to activate the input parameters. Each terminal input is an active logic low.
Start
Power Up
Restore Volume and MCR
Initialize Default
EEPROM
Initialize TAS3002 TAS3001
Slave Write
Load Parameters and Coefficients to DSP
Volume / Bass / Treble Up / Down Echo to TAS3001 Switch BQ Set
Power Down
Figure 7-3. Internal Interface Flow Chart
7.7 External EEPROM Memory Maps
Table 7-2 through Table 7-5 show the 512-byte and 2048-byte EEPROM memory maps. Table 7-2. 512-Byte EEPROM Memory Map 2.0 Channels
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
Table 7-3. 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)
NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels. Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
Table 7-4. 2048-Byte EEPROM Memory Map-2.0 Speakers With Multiple Equalizations
TAS3002 ADDRESS LEFT BIQUAD 000h 001h 002h 003h-00Bh 00Ch-014h 015h-019h 01Ah 01Bh 01Ch-021h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah-185h 200h-20Eh 20Fh-21Dh 21Eh-22Ch 22Dh-23Bh 23Ch-24Ah 24Bh-259h 25Ah-268h 269h-277h 278h-286h 287h-295h 296h-2A4h 2A5h-2B3h 2B4h-2C2h 2C3h-2D1h 2D2h-2E0h 2E1h-2EFh 2F0h-2FEh 2FFh-30Dh 30Eh-31Ch 31Dh-32Bh 32Ch-33Ah 33Bh-349h 34Ah-358h 359h-367h 368h-376h 377h-385h 386h-394h 395h-3A3h NUMBER OF BYTES 1 1 1 9 / 3 9 / 3 6 / 2 1 1 6 15 15 15 15 15 15 15 236 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Set 4 Set 3 Set 2 Set 1 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Bass treble table 40Dh-41Bh 41Ch-42Ah 42Bh-439h 43Ah-448h 449h-457h 458h-466h 467h-475h 476h-484h 485h-493h 494h-4A2h 4A3h-4B1h 4B2h-4C0h 4C1h-4CFh 4D0h-4DEh 4DFh-4EDh 4EEh-4FCh 4FDh-50Bh 50Ch-51Ah 51Bh-529h 52Ah-538h 539h-547h 548h-556h 557h-565h 566h-574h 575h-583h 584h-592h 593h-5A1h 5A2h-5B0h 5B1h-5BFh 5C0h-5CEh 5CFh-5DDh 5DEh-5ECh 5EDh-5FBh 5FCh-60Ah 60Bh-619h 61Ah-628h 629h-637h 638h-646h 647h-655h 656h-664h 665h-673h 674h-682h 683h-691h 692h-6A0h 6A1h-6AFh 6B0h-6BEh 6BFh-6CDh 6CEh-6DCh 6DDh-6EBh 6ECh-6FAh 6FBh-709h 70Ah-718h 719h-727h 728h-736h 737h-745h 746h-754h Set 0 1 0 0 MCR Mixer left gain Mixer right gain DRC (ratio, threshold, energy, attack, decay) Bass Treble Volume 3A4h-3B2h 3B3h-3C1h 3C2h-3D0h 3D1h-3DFh 3E0h-3EEh 3EFh-3FDh 3FEh-40Ch FUNCTION CATEGORY TAS3002 ADDRESS RIGHT BIQUAD TAS3001
Signature (2Ah) 0 0 0 1 1EFh 1F0h-1F2h 1F3h-1F5h 1F6h-1F7h 1F8h 1F9h 1FAh-1FFh 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh 0
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
Table 7-5. 2048-Byte EEPROM Memory Map-2.1 Speakers With Multiple Equalizations
TAS3002 ADDRESS 000h 001h 002h 003h-00Bh 00Ch-014h 015h-019h 01Ah 01Bh 01Ch-021h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah-185h 200h-20Eh 20Fh-21Dh 21Eh-22Ch 22Dh-23Bh 23Ch-24Ah 24Bh-259h 25Ah-268h 269h-277h 278h-286h 287h-295h 296h-2A4h 2A5h-2B3h 2B4h-2C2h 2C3h-2D1h 2D2h-2E0h 2E1h-2EFh 2F0h-2FEh 2FFh-30Dh 30Eh-31Ch 31Dh-32Bh 32Ch-33Ah 33Bh-349h 34Ah-358h 359h-367h 368h-376h 377h-385h 386h-394h 395h-3A3h NUMBER OF BYTES 1 1 1 9 / 3 9 / 3 6 / 2 1 1 6 15 15 15 15 15 15 15 236 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Set 4 Set 3 Set 2 Set 1 Biquad 0 Biquad 1 Biquad 2 Biquad 3 Biquad 4 Biquad 5 Biquad 6 Bass treble table 5B1h-5BFh 5C0h-5CEh 5CFh-5DDh 5DEh-5ECh 5EDh-5FBh 5FCh-60Ah 60Bh-619h 61Ah-628h 629h-637h 638h-646h 647h-655h 656h-664h 665h-673h 674h-682h 683h-691h 692h-6A0h 6A1h-6AFh 6B0h-6BEh 6BFh-6CDh 6CEh-6DCh 6DDh-6EBh 6ECh-6FAh 6FBh-709h 70Ah-718h 719h-727h 728h-736h 737h-745h 746h-754h 40Dh-41Bh 41Ch-42Ah 42Bh-439h 43Ah-448h 449h-457h 458h-466h 467h-475h 476h-484h 485h-493h 494h-4A2h 4A3h-4B1h 4B2h-4C0h 4C1h-4CFh 4D0h-4DEh 4DFh-4EDh 4EEh-4FCh 4FDh-50Bh 50Ch-51Ah 51Bh-529h 52Ah-538h 539h-547h 548h-556h 557h-565h 566h-574h 575h-583h 584h-592h 593h-5A1h 5A2h-5B0h Set 0 1 0 0 MCR Mixer left gain Mixer right gain DRC (ratio, threshold, energy, attack, decay) Bass Treble Volume 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh FUNCTION CATEGORY TAS3001 ADDRESS LEFT CHANNEL TAS3001 ADDRESS RIGHT CHANNEL
Signature (2Ah) 0 0 0 0 1EFh 1F0h-1F2h 1F3h-1F5h 1F6h-1F7h 1F8h 1F9h 1FAh-1FFh 3A4h-3B2h 3B3h-3C1h 3C2h-3D0h 3D1h-3DFh 3E0h-3EEh 3EFh-3FDh 3FEh-40Ch 1
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
8 Electrical Characteristics
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Human body model per Method 3015.2 of MIL-STD-833B.
8.2 Recommended Operating Conditions
MIN Supply voltage, AVDD Supply voltage, DVDD Operating Supply current, analog current Power down (see Note 2) Operating Supply current digital current, Power down (see Note 2) Operating Power dissipation NOTE 2: If the clocks are turned off. Power down (see Note 2) 3.0 3.0 NOM 3.3 3.3 34 88 47 942 267 3.5 MAX 3.6 3.6 UNIT V V mA µA mA µA mW mW
8.3 Static Digital Specifications
8.4 ADC Digital Filter
Figure 8-1. ADC Digital Filter Characteristics
0 -20 Amplitude - dB -40 -60 -80 -100 0 0.2 fs 0.4 fs 0.6 fs f - Frequency - Hz 0.8 fs 1 fs
Figure 8-2. ADC Digital Filter Stop-Band Characteristics
0.008 0.006 Amplitude - dB 0.004 0.002 0 -0.002 0 0.1 fs 0.2 fs 0.3 fs f - Frequency - Hz 0.4 fs 0.5 fs
Figure 8-3. ADC Digital Filter Pass-Band Characteristics
0.2 0 Amplitude - dB -0.2 -0.4 -0.6 -0.8 -1 0 1 fs 2 fs f - Frequency - Hz 3 fs 4 fs
Figure 8-4. ADC High-Pass Filter Characteristics
8.5 Analog-to-Digital Converter
8.6 Input Multiplexer
PARAMETER Input impedance Crosstalk Full-scale input voltage range TEST CONDITIONS MIN TYP 20 85 1.7 MAX UNIT k dB VPP
8.7 DAC Interpolation Filter
Figure 8-5. DAC Filter Overall Frequency Characteristics
Amplitude - dB
-0.1 0 0.1 fs 0.2 fs 0.3 fs f - Frequency - Hz 0.4 fs 0.5 fs
Figure 8-6. DAC Digital Filter Pass-Band Ripple Characteristics
8.8 Digital-to-Analog Converter
8.9 DAC Output Performance Data
PARAMETER Output load resistance Output load capacitance VCOM internal resistance (see Note 4) VCOM output CLOAD VRFILT internal resistance (see Note 5) NOTES: 4. VCOM may vary during power down. 5. VRFILT must never be used as a voltage reference. 1 10 1 100 TEST CONDITIONS MIN 10 25 TYP MAX UNIT k pF k µF k
8.10 I2C Serial Port Timing Characteristics
MIN f(SCL) t(buf) t(low) t(high) SCL clock frequency Bus free time between start and stop Low period of SCL clock High period of SCL clock 0 4.7 4.7 4.0 4.0 4.7 0 250 1000 300 4.0 400 20 MAX 100 UNIT kHz µs µs µs µs µs µs ns ns ns µs pF
th(sta) Hold time repeated start tsu(sta) Setup time repeated start th(dat) Data hold time (See Note 6) tsu(dat) Data setup time tr tf Rise time for SDA and SCL Fall time for SDA and SCL
tsu(sto) Setup time for stop condition C(b) Capacitive load for each bus line
NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. P S P
SDA t(buf)
Valid th(dat) tr tsu(dat) Change of Data Allowed tsu(sto) tsu(sta)
SCL Data Line Stable
tf th(sta) NOTE: t(low) is measured from the end of tf to the beginning of tr. t(high) is measured from the end of tr to the beginning of tf.
th(sta)
Figure 8-7. I2C Bus Timing
9 System Diagrams
Figure 9-1 and Figure 9-2 show the TAS3002 stereo and 2.1-channel applications, respectively.
+3.3 VDD
RESET Clock Select Logic Analog Out
Analog In
SPDIF or USB
TAS3002
EEPROM
Master
B-T-V-EQ Switches NOTE: Items such as the PLL network and power supplies are omitted for clarity.
Figure 9-1. Stereo Application
+3.3 VDD
RESET Clock Select Logic Analog Out (To Satellite Amplifiers)
Analog In
SPDIF or USB
TAS3002
EEPROM
Master
SDOUT2
Echoes Switches on GPIO
B-T-V-EQ-Sub Vol L+R Mix
Slave I2S PCM1744 Analog Out
TAS3001
Figure 9-2. TAS3002 Device, 2.1 Channels
10 Mechanical Information
The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical dimensions for the PFB package. PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
13 0, 13 NOM 1 5, 50 TYP 7, 20 SQ 6, 80 9, 20 SQ 8, 80 0, 05 MIN 1, 05 0, 95 Seating Plane 0, 75 0, 45 Gage Plane 0, 25 0°-7° 12
1, 20 MAX
0, 08 4073176 / B 10 / 96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
Appendix A Software Interface
A.1 I2C Register Map
Table A-1 is a listing of all the registers used by the I2C interface. Table A-1. I2C Register Map
REGISTER Reserved Main control 1 DRC Reserved Volume Treble Bass Mixer left gain ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 6 1 1 9 VL(23-16), VL(15-8), VL(7-0) VR(23-16), VR(15-8), VR(7-0) T(7-0) B(7-0) S1L(23-16), S1L(15-8), S1L(7-0) S2L(23-16), S2L(15-8), S2L(7-0) AIL(23-16), AIL(15-8), AIL(7-0) S1R(23-16), S1R(15-8), S1R(7-0) S2R(23-16), S2R(15-8), S2R(7-0) AIR(23-16), AIR(15-8), AIR(7-0) 1 5 MCR1(7-0) Ratio(7-0), Threshold(7-0), Energy(7-0), Attack(7-0), Decay(7-0) NUMBER OF BYTES BYTE DESCRIPTION
Mixer right gain
Reserved Left biquad 0
09h 0Ah 15 B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Left biquad 1
Left biquad 2
Left biquad 3
Left biquad 4
Table A-1. I2C Register Map (Continued)
NUMBER OF BYTES 15
REGISTER Left biquad 5
ADDRESS 0Fh
BYTE DESCRIPTION B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Left biquad 6
Reserved Reserved Right biquad 0
11h 12h 13h 15 B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Right biquad 1
Right biquad 2
Right biquad 3
Right biquad 4
Right biquad 5
Right biquad 6
Reserved Left loudness biquad
20h 21h 15 B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Table A-1. I2C Register Map (Continued)
Left loudness biquad gain Right loudness biquad gain Reserved Test Reserved Analog control Test Test Main control 2 Reserved
23h 24h 25h-28h 29h 30h to 3Fh 40h 41h 42h 43h 44h-FFh
A.2 Main Control Register Map
A.2.1 Main Control Register 1
MCR1 01h C(7) FL 1 C(6) SC x C(5) E1 x C(4) E0 x C(3) F1 x C(2) F0 x C(1) W1 x C(0) W0 x
Table A-2 lists the bit fields making up main control register 1 and defines the function associated with each bit field. Table A-2. Main Control Register 1 Description
A.2.2
Main Control Register 2
C2(6) XX 0 C2(5) XX 0 C2(4) XX 0 C2(3) XX 0 C2(2) XX 0 C2(1) AP 1 C2(0) XX 0
MCR2 43h C2(7) DL 1
Table A-3 lists the bit fields making up main control register 2 and defines the function associated with each bit field. Table A-3. Main Control Register 2 Description
REGISTER C2(7) ( ) C2(6) ( ) C2(5) ( ) C2(4) ( ) C2(3) ( ) C2(2) ( ) C2(1) ( ) C2(0) ( ) DESCRIPTOR DL XX XX XX XX XX AP XX FUNCTION Bass and treble load Reserved Reserved Reserved Reserved Reserved AllPass mode Reserved VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Normal operation Sets equalization filters to all pass Normal operation mode Downloaded values DESCRIPTION
A.2.3
Analog Control Register
A(6) XX 0 A(5) XX 0 A(4) XX 0 A(3) DM1 1 A(2) DM0 1 A(1) INP 1 A(0) APD 1
ANA 40h A(7) XX 0
Table A-4 lists the bit fields making up the analog control register and defines the function associated with each bit field. Table A-4. Analog Control Register Description
A.3 Volume Gain Command
Device ID Subaddress VL(23-16) VL(15-8) VL(7-0) VR(23-16) VR(15-8) VR(7-0)
Table A-5 lists the possible gains for the volume gain command in 0.5 dB increments from 18 to -70 dB, with the corresponding hexadecimal value for each gain. Table A-5. Volume Versus Gain Values
GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) 07, F1, 7B 07, 7F, BB 07, 14, 57 06, AE, F6 06, 4F, 40 05, F4, E5 05, 9F, 98 05, 4F, 10 05, 03, 0A 04, BB, 44 04, 77, 83 04, 37, 8B 03, FB, 28 03, C2, 25 03, 8C, 53 03, 59, 83 03, 29, 8B 02, FC, 42 02, D1, 82 02, A9, 25 02, 83, 0B 02, 5F, 12 02, 3D, 1D 02, 1D, 0E 01, FE, CA 01, E2, 37 01, C7, 3D 01, AD, C6 01, 95, BC 01, 7F, 09 GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) 01, 69, 9C 01, 55, 62 01, 42, 49 01, 30, 42 01, 1F, 3D 01, 0F, 2B 01, 00, 00 00, F1, AE 00, E4, 29 00, D7, 66 00, CB, 59 00, BF, F9 00, B5, 3C 00, AB, 19 00, A1, 86 00, 98, 7D 00, 8F, F6 00, 87, E8 00, 80, 4E 00, 79, 20 00, 72, 5A 00, 6B, F4 00, 65, EA 00, 60, 37 00, 5A, D5 00, 55, C0 00, 50, F4 00, 4C, 6D 00, 48, 27 00, 44, 1D GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) 00, 40, 4E 00, 3C, B5 00, 39, 50 00, 36, 1B 00, 33, 14 00, 30, 39 00, 2D, 86 00, 2A, FA 00, 28, 93 00, 26, 4E 00, 24, 29 00, 22, 23 00, 20, 3A 00, 1E, 6D 00, 1C, B9 00, 1B, 1E 00, 19, 9A 00, 18, 2B 00, 16, D1 00, 15, 8A 00, 14, 56 00, 13, 33 00, 12, 20 00, 11, 1C 00, 10, 27 00, 0F, 40 00, 0E, 65 00, 0D, 97 00, 0C, D5 00, 0C, 1D GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) 00, 0B, 6F 00, 0A, CC 00, 0A, 31 00, 09, 9F 00, 09, 15 00, 08, 93 00, 08, 18 00, 07, A5 00, 07, 37 00, 06, D0 00, 06, 6E 00, 06, 12 00, 05, BB 00, 05, 69 00, 05, 1C 00, 04, D2 00, 04, 8D 00, 04, 4C 00, 04, 0F 00, 03, D5 00, 03, 9E 00, 03, 6A 00, 03, 39 00, 03, 0B 00, 02, DF 00, 02, B6 00, 02, 8F 00, 02, 6B 00, 02, 48 00, 02, 27 GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) 00, 02, 09 00, 01, EB 00, 01, D0 00, 01, B6 00, 01, 9E 00, 01, 86 00, 01, 71 00, 01, 5C 00, 01, 48 00, 01, 36 00, 01, 25 00, 01, 14 00, 01, 05 00, 00, F6 00, 00, E9 00, 00, DC 00, 00, CF 00, 00, C4 00, 00, B9 00, 00, AE 00, 00, A5 00, 00, 9B 00, 00, 93 00, 00, 8B 00, 00, 83 00, 00, 7B 00, 00, 75 00, 00, 6E 00, 00, 68 00, 00, 62
Table A-5. Volume Versus Gain Values (Continued)
VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 5D 00, 00, 57 00, 00, 53 00, 00, 4E 00, 00, 4A 00, 00, 45 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 42 00, 00, 3E 00, 00, 3A 00, 00, 37 00, 00, 34 00, 00, 31 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 2E 00, 00, 2C 00, 00, 29 00, 00, 27 00, 00, 25 00, 00, 23 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 21 00, 00, 1F 00, 00, 1D 00, 00, 1C 00, 00, 1A 00, 00, 19 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 17 00, 00, 16 00, 00, 15 00, 00, 00
GAIN (dB)
-69.0 -69.5 -70.0 mute
A.4 Treble Control Register Command
Both left and right channels are given the same treble gain setting.
Device ID Subaddress T(7-0)
Table A-6 lists the possible gain adjustments in 0.5 dB increments across the range of treble control, 18 to -18 dB, with the corresponding hexadecimal value for each gain adjustment. Table A-6. Treble Control Register
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 T(7-0) (hex) 01h 01h 04h 08h 13h 1Ah 20h 26h 2Ch 31h 36h 3Bh 3Fh 43h 47h GAIN (dB) 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 T(7-0) (hex) 4Ah 4Dh 51h 53h 56h 59h 5Bh 5Dh 60h 62h 63h 65h 67h 68h 69h GAIN (dB) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 T(7-0) (hex) 6Bh 6Ch 6Dh 3Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah GAIN (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 T(7-0) (hex) 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h GAIN (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 T(7-0) (hex) 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h
A.5 Bass Control Register Command
Both left and right channels are given the same bass gain setting.
Device ID Subaddress B(7-0)
Table A-7 lists the possible gain adjustments in 0.5 dB increments across the range of bass control, 18 to -18 dB, with the corresponding hexadecimal value for each gain adjustment. Table A-7. Bass Control Register
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 B(7-0) (hex) 01h 0Ah 11h 18h 1Eh 24h 29h 2Eh 33h 37h 3Bh 3Fh 43h 46h 49h GAIN (dB) 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 B(7-0) (hex) 4Ch 4Fh 52h 55h 58h 5Bh 5Dh 5Fh 61h 62h 63h 65h 66h 67h 69h GAIN (dB) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 B(7-0) (hex) 6Ah 6Bh 6Dh 6Eh 6Fh 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah GAIN (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 B(7-0) (hex) 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h GAIN (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 B(7-0) (hex) 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h
A.6 I2C Mixer Register Command
Device ID Subaddress Mixer1 Mixer2 ADC Mixer
Right
Even if only one of the mixers needs to be changed, the whole command must be sent. Table A-8 lists the possible gain settings for the I2C mixer input channels in 0.5 dB increments from 18 to -70 dB, with the corresponding hexadecimal value for each gain.
Table A-8. Mixer1, Mixer2 and ADC Mixer Gain Values
GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) 7F, 17, AF 77, FB, AA 71, 45, 75 6A, EF, 5D 64, F4, 03 5F, 4E, 52 59, F9, 80 54, F1, 06 50, 30, A1 4B, B4, 46 47, 78, 28 43, 78, B0 3F, B2, 78 3C, 22, 4C 38, C5, 28 35, 98, 2F 32, 98, B0 2F, C4, 20 2D, 18, 18 2A, 92, 54 28, 30, AF 25, F1, 25 23, D1, CD 21, D0, D9 1F, EC, 98 1E, 23, 6D 1C, 73, D5 1A, DC, 61 19, 5B, B8 17, F0, 94 16, 99, C0 15, 56, 1A 14, 24, 8E 13, 04, 1A 11, F3, C9 10, F2, B4 GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) 10, 00, 00 0F, 1A, DF 0E, 42, 90 0D, 76, 5A 0C, B5, 91 0B, FF, 91 0B, 53, BE 0A, B1, 89 0A, 18, 66 09, 87, D5 08, FF, 59 08, 7E, 80 08, 04, DC 07, 92, 07 07, 25, 9D 06, BF, 44 06, 5E, A5 06, 03, 6E 05, AD, 50 05, 5C, 04 05, 0F, 44 04, C6, D0 04, 82, 68 04, 41, D5 04, 04, DE 03, CB, 50 03, 94, FA 03, 61, AF 03, 31, 42 03, 03, 8A 02, D8, 62 02, AF, A3 02, 89, 2C 02, 64, DB 02, 42, 93 02, 22, 35 GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) 02, 03, A7 01, E6, CF 01, CB, 94 01, B1, DE 01, 99, 99 01, 82, AF 01, 6D, 0E 01, 58, A2 01, 45, 5B 01, 33, 28 01, 21, F9 01, 11, C0 01, 02, 70 00, F3, FB 00, E6, 55 00, D9, 73 00, CD, 49 00, C1, CD 00, B6, F6 00, AC, BA 00, A3, 10 00, 99, F1 00, 91, 54 00, 89, 33 00, 81, 86 00, 7A, 48 00, 73, 70 00, 6C, FB 00, 66, E3 00, 61, 21 00, 5B, B2 00, 56, 91 00, 51, B9 00, 4D, 27 00, 48, D6 00, 44, C3 GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) 00, 40, EA 00, 3D, 49 00, 39, DB 00, 36, 9E 00, 33, 90 00, 30, AE 00, 2D, F5 00, 2B, 63 00, 28, F5 00, 26, AB 00, 24, 81 00, 22, 76 00, 20, 89 00, 1E, B7 00, 1C, FF 00, 1B, 60 00, 19, D8 00, 18, 65 00, 17, 08 00, 15, BE 00, 14, 87 00, 13, 61 00, 12, 4B 00, 11, 45 00, 10, 4E 00, 0F, 64 00, 0E, 88 00, 0D, B8 00, 0C, F3 00, 0C, 3A 00, 0B, 8B 00, 0A, E5 00, 0A, 49 00, 09, B6 00, 09, 2B 00, 08, A8 GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) 00, 08, 2C 00, 07, B7 00, 07, 48 00, 06, E0 00, 06, 7D 00, 06, 20 00, 05, C9 00, 05, 76 00, 05, 28 00, 04, DE 00, 04, 98 00, 04, 56 00, 04, 18 00, 03, DD 00, 03, A6 00, 03, 72 00, 03, 40 00, 03, 12 00, 02, E6 00, 02, BC 00, 02, 95 00, 02, 70 00, 02, 4D 00, 02, 2C 00, 02, 0D 00, 01, F0 00, 01, D4 00, 01, BA 00, 01, A1 00, 01, 8A 00, 01, 74 00, 01, 5F 00, 01, 4B 00, 00, 00
-54.0 -54.5 -55.0 -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute
A.7 Programming Instruction for the Loudness Contour
Device ID Subaddress B0(23-0) B1(23-0) B2(23-0) A1(23-0) A2(23-0)
For example: Left Loudness Biquad
68 21 001A82 000000 FFE57E E03550 0FCABB
Right Loudness Biquad
68 22 001A82 000000 FFE57E E03550 0FCABB
Left Loudness Biquad Gain
G(23-0)
04C6D0
Right Loudness Biquad Gain
68 24 04C6D0
A.8 Examples of Dynamic Range Compression / Expansion (DRCE)
Table A-9. Example of a DRCE I2C Instruction With DRCE On
BYTE NUMBER 1 2 3 4 5 6 7 8 INSTRUCTION (HEX) 68 02 68 22 9F B0 60 A0 INSTRUCTION DEFINITION TAS3002 device identification DRC subaddress Above-threshold ratio of 5.33:1 with DRCE on Below-threshold ratio of 1.33:1 Threshold of -30 dB Integration interval for energy level detection of 212 ms Attack time constant 6.7 ms Decay time constant 106 ms See Table A-11 and Table A-12 See Table A-13 and Table A-14 See Table A-15 See Table A-16 TABLE
A.8.1
DRCE On / Off
The DRCE default mode in the TAS3002 device is off. The DRCE turns on if all eight bytes in Table A-9 are transmitted and the LSB of the above-threshold ratio byte is 0. The DRCE turns off if all eight bytes in Table A-10 are transmitted and the LSB of the above-threshold ratio byte is 1. Table A-10 is identical to Table A-9 except for this third byte. Table A-10. Example of a DRCE I2C Instruction With DRCE Off
BYTE NUMBER 1 2 3 4 5 6 7 8 INSTRUCTION (HEX) 68 02 69 22 9F B0 60 A0 INSTRUCTION DEFINITION TAS3002 device identification DRC subaddress Above threshold ratio of 5.33:1 with DRCE off Below threshold ratio of 1.33:1 Threshold of -30 dB Integration interval for energy level detection of 212 ms Attack time constant 6.7 ms Decay time constant 106 ms See Table A-11 and Table A-12 See Table A-13 and Table A-14 See Table A-15 See Table A-16 TABLE
A.8.2
Above-Threshold Ratios
The above threshold ratios are applied when the energy level of the incoming signal is detected anywhere between the threshold (from Table A-15) and 0 dB. See Figure A-1.
Output (dB) 0 dB
Expansion
Compression
-89.625 dB -89.625 dB
Input (dB) Threshold Above Threshold 0 dB
Below Threshold
Figure A-1. TAS3002 DRCE Characteristics in the dB Domain Table A-11. Above-Threshold Ratios for Compression
HEXADECIMAL VALUE 02 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 RATIO (IN:OUT) 1.00 : 1 1.07 : 1 1.14 : 1 1.23 : 1 1.33 : 1 1.45 : 1 1.60 : 1 1.78 : 1 2.00 : 1 2.29 : 1 2.67 : 1 3.20 : 1 4.00 : 1 5.33 : 1 8.00 : 1 16.0 : 1
Table A-12. Above-Threshold Ratios for Expansion
HEXADECIMAL VALUE 02 0A 12 1A 22 2A 32 3A 42 RATIO (IN:OUT) 1 : 1.00 1 : 1.06 1 : 1.13 1 : 1.19 1 : 1.25 1 : 1.31 1 : 1.38 1 : 1.44 1 : 1.50
A.8.3
Below-Threshold Ratios
The below-threshold ratios are applied when the energy level of the incoming signal is detected as being anywhere between the threshold (from Table A-15) and -89.625 dB. See Figure A-1. Table A-13. Below-Threshold Ratios for Expansion
HEXADECIMAL VALUE 02 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 RATIO (IN:OUT) 1 : 1.00 1 : 1.06 1 : 1.13 1 : 1.19 1 : 1.25 1 : 1.31 1 : 1.38 1 : 1.44 1 : 1.50 1 : 1.56 1 : 1.63 1 : 1.69 1 : 1.75 1 : 1.81 1 : 1.88 1 : 1.94 1 : 2.00
Table A-14. Below-Threshold Ratios for Compression
HEXADECIMAL VALUE 02 0A 12 1A 22 2A 32 3A 42 RATIO (IN:OUT) 1.00 : 1 1.07 : 1 1.14 : 1 1.23 : 1 1.33 : 1 1.45 : 1 1.60 : 1 1.78 : 1 2.00 : 1
A.8.4
Threshold
Table A-15 lists a range of threshold values from 0 dB to -89.625 dB in 0.75-dB decrements. NOTE: The TAS3002 device is capable of 0.375-dB increments. The associated hexadecimal value can be determined by interpolating between the existing hexadecimal values in Table A-15. Table A-15. Threshold Values
HEX VALUE EF ED EB E9 E7 E5 E3 E1 DF DD DB D9 D7 D5 D3 D1 CF CD CB C9 C7 C5 C3 C1 BF dB 0 -0.75 -1.50 -2.25 -3.00 -3.75 -4.50 -5.25 -6.00 -6.75 -7.50 -8.25 -9.00 -9.75 -10.50 -11.25 -12.00 -12.75 -13.50 -14.25 -15.00 -15.75 -16.50 -17.25 -18.00 HEX VALUE BD BB B9 B7 B5 B3 B1 AF AD AB A9 A7 A5 A3 A1 9F 9D 9B 99 97 95 93 91 8F 8D dB -18.75 -19.50 -20.25 -21.00 -21.75 -22.50 -23.25 -24.00 -24.75 -25.50 -26.25 -27.00 -27.75 -28.50 -29.25 -30.00 -30.75 -31.50 -32.25 -33.00 -33.75 -34.50 -35.25 -36.00 -36.75 HEX VALUE 8B 89 87 85 83 81 7F 7D 7B 79 77 75 73 71 6F 6D 6B 69 67 65 63 61 5F 5D 5B dB -37.50 -38.25 -39.00 -39.75 -40.50 -41.25 -42.00 -42.75 -43.50 -44.25 -45.00 -45.75 -46.50 -47.25 -48.00 -48.75 -49.50 -50.25 -51.00 -51.75 -52.50 -53.25 -54.00 -54.75 -55.50 HEX VALUE 59 57 55 53 51 4F 4D 4B 49 47 45 43 41 3F 3D 3B 39 37 35 33 31 2F 2D 2B 29 dB -56.25 -57.00 -57.75 -58.50 -59.25 -60.00 -60.75 -61.50 -62.25 -63.00 -63.75 -64.50 -65.25 -66.00 -66.75 -67.50 -68.25 -69.00 -69.75 -70.50 -71.25 -72.00 -72.75 -73.50 -74.25 HEX VALUE 27 25 23 21 1F 1D 1B 19 17 15 13 11 0F 0D 0B 09 07 05 03 01 00 dB -75.00 -75.75 -76.50 -77.25 -78.00 -78.75 -79.50 -80.25 -80.00 -81.75 -82.50 -83.25 -84.00 -84.75 -85.50 -86.25 -87.00 -87.75 -88.50 -89.25 -89.625
A.8.5
Time Constants
Table A-16. Time Constants
HEXADECIMAL VALUE 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 TIME DELAY 1.7 ms 3.5 ms 6.7 ms 13 ms 26 ms 53 ms 106 ms 212 ms 425 ms 850 ms 1.7 s 2.4 s
A.8.6
DRCE Example With Threshold at -12 dB
Output (dB) 0 dB
1:1 Below Threshold Ratio for Compression
Figure A-2. DRCE Example With Threshold at -12 dB