Digital Audio Processor DAV-Audio Products SLAS226A IMP

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TAS3001C
Digital Audio Processor
DAV-Audio Products
SLAS226A
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Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
Contents
Section Title Page Introduction Description Overview Features 1.3.1 Stereo Digital Audio Processing 1.3.2 Interfaces 1.3.3 Electrical Physical Applications 1.4.1 Digital Audio Controls 1.4.2 Equalization 1.4.3 Loudspeaker Active Crossovers Functional Block Diagram Mixing/Input Scaling High-Precision, Second-Order Biquad Filter Structure Bass Treble Controls Soft Volume True Soft Mute 1.10 Dynamic Range Compression 1.11 Reliability Flexibility Digital Filtering 1.12 Assignments 1.13 Functions 1.14 Ordering Information 1.15 Power Supply Audio Data Formats Serial Audio Interface 2.1.1 Serial Format 2.1.2 Left-Justified Serial Format 2.1.3 Right-Justified Serial Format LRCLKOUT SCLKOUT Serial Control Interface (I2C) Protocol Operation 3.2.1 Write Cycle Example 3.2.2 Timing Wait Cycles 3.2.3 Resetting TAS3001 Interface 3.2.4 Power-Up Conditions 3.2.5 Serial Port Timing Digital Audio Processor
Input Mixer Control Biquad Block 4.2.1 Filter Coefficients Volume Control Functions 4.3.1 Soft Volume Update 4.3.2 Software Soft Mute Tone Controls 4.4.1 Treble Control 4.4.2 Bass Control 4.4.3 Frequency Dependence Treble Bass Controls Dynamic Range Compression (DRC) Device Operation Device Initialization 5.1.1 Reset 5.1.2 Device Power System Reset 5.1.3 Fast Load Power Consumption Power Down Start-Up Electrical Characteristics Absolute Maximum Ratings Over Operating Free-Air Temperature Range Recommended Operating Conditions Power Consumption Static Digital Specifications Measured Audio Performance Some Typical Examples Using TAS3001 System TAS3001 Applications Measurement-Based Speaker Correction Sound-Based Speaker Correction Loudspeaker Equalization Example Speaker Correction Equalization TAS3001 Implement Nearly Second-Order Filter Converting Analog Filters Digital Automatic Loudspeaker Equalizer Automatic Generation Equalization Filters Given Measurement Automatic Approximation Equalization Curve Manual Filter Design Conversion Decimal Filter Coefficients TAS3001 Format Editing TAS3001 File Format Examples Filter Types Available From FilterBuilder FilterMaker Software Interface Main Control Register (MCR) Mechanical Information
10-1
List Illustrations
Figure Title Page TAS3001 Signal Flow Examples High-Pass Filters Examples Equalization Filters Bass Treble Shelves Multiple Filter Response Combed Response Multiple Filters Bass Treble Filters TAS3001 Location Diagram I2S-Compatible Serial Format Right/Left Justified, I2S, Left/Left Justified Serial Protocols Left-Justified Serial Format Right-Justified Serial Format Master Mode Slave Mode Typical Data Transfer Sequence Write Cycle Example Wait Cycle Example Serial Port Timing Cascaded Biquad Filters Audio Processing Architecture Example Main Control Register (MCR) Power-Down Timing Start-Up Timing Typical TAS3001 Connection Audio Performance Measurement System Audio Performance Test Filters TAS3001 System Equalizer TAS3001 Crossover Equalizer TAS3001 Dynamic Range Compressor Equalizer Typical Small Loudspeaker Response Preparation Equalization After Equalization
List Illustrations (Continued)
Equalization Filters Individual Filters Combined Response Equalization Filters High- Low-Pass Filters Treble Bass Shelf Filters Notch Filters
List Tables
Table Title Serial Interface Input Options Serial Interface Output Options Protocol Definitions TAS3001 Address Write Cycle Example Wait States Bass Control Corner Frequencies Treble Control Corner Frequencies Audio Filter Performance Register Main Control Register (MCR) Main Control Register (MCR) Description Interface (Byte Interface (Byte Volume Gain Values Treble Control Register Bass Control Register Mixer1 Mixer2 Gain Values Page
Introduction
Description
TAS3001 high-quality, fixed-function, 32-bit digital audio processor. This device contains number built-in processing functions including mixing/scaling digital inputs; bass treble controls; cascaded stereo high-precision, limit-cycle-free, second-order filters; dynamic range compression; soft volume; soft mute. These functions controlled specifying desired operating parameters using interface. TAS3001 architecture preserves high-quality audio using 32-bit data path, 32-bit multiplies, bits precision some internal calculations. using 24-bit filter coefficients, TAS3001 implement practically second-order filter with outstanding fidelity.
Overview
TAS3001 32-bit audio signal processor that provides mixing digital inputs, digital parametric equalization, dynamic range compression. addition, this device provides high-quality, soft digital volume, bass, treble controls. control parameters uploaded through port from outside MCU. TAS3001 five audio processing blocks shown Figure 1-1. digital stereo audio inputs that scaled mixed prior processing. Parametric that consists cascaded independent second-order filters each left right independent channels. Each filter five 24-bit coefficients that configured into many different filter functions, such band-pass, high-pass, low-pass, shelves, notch, all-pass, high-/low-pass with shelf, etc. Digital bass treble controls Digital soft volume mute Dynamic range compression (DRC)
TAS3001 device uses system clock that generated internal phase-locked loop (PLL). external master clock (MCLK) times sampling frequency provides reference clock PLL. TAS3001 device supports several serial data formats (I2S, left justified, right justified) with data word lengths sampling frequencies (fs) that supported include kHz, 44.1 kHz, kHz.
Features
1.3.1
Stereo Digital Audio Processing
Supports nine serial data formats. Receive transmit serial data formats different. Programmable two-input digital mixer Programmable six-band digital parametric Programmable digital bass treble controls Programmable digital volume control with soft mute Dynamic range compression 108-dB dynamic range Sample rates from
1.3.2
Interfaces
serial digital input channels
Single serial digital output channel Serial control channel
1.3.3
Electrical Physical
Single 3.3-V power supply 28-pin package Low-power standby
Applications
1.4.1 Digital Audio Controls
TAS3001 used provide high-quality digital system control volume, bass, treble, parametric equalization, dynamic range compression.
1.4.2
Equalization
TAS3001 used perform parametric equalization correct frequency response loudspeakers microphones. TAS3001 corrects response applying filters compensate response irregularities transducers.
1.4.3
Loudspeaker Active Crossovers
TAS3001 used implement active crossover multi-way loudspeaker systems.
Functional Block Diagram
Slave Address Select
System Control
Dynamic Range Compression
SDIN1 SDIN2 LRCLK SCLK MCLK
Serial Audio Input Port
2-Channel Stereo Mixer
Biquad Filters
Treble/ Bass
Volume
SDOUT
Clock Generator
LRCLKOUT SCLKOUT
Internal Clocks
Figure 1-1. TAS3001 Signal Flow Figure shows signal flow from inputs (SDIN1 SDIN2) though each processing stage output (SDOUT) where passed external DAC, digital amplifier, other subsequent digital data processing stage. Each these audio processing functions discussed more detail following sections.
Mixing/Input Scaling
TAS3001 equipped with dual-input stereo digital mixer. This mixer permits each input scaled independently. stereo scaled results produced.
High-Precision, Second-Order Biquad Filter Structure
TAS3001 cascaded biquad filters left right channels permit parametric equalization filtering input signal. Each biquad able specify wide variety first- second-order filter types, including high-pass, low-pass, band-pass, band-block, notch, all-pass filter types. Examples filters that implemented TAS3001 shapes illustrated Figure though Figure 1-6.
ATTENUATION FREQUENCY
ATTENUATION FREQUENCY
Attenuation
Attenuation
Frequency
Frequency
Figure 1-2. Examples High-Pass Filters biquad structure form: H(z)
Figure 1-3. Examples Equalization Filters
Coefficients downloaded TAS3001 registers 4.20 format.
ATTENUATION FREQUENCY
Attenuation Frequency Attenuation
ATTENUATION FREQUENCY
Frequency
Figure 1-4. Bass Treble Shelves
Figure 1-5. Multiple Filter Response
TAS3001 provides zero-input limit-cycle-free second-order filtering structure that implements direct form filter structure. This architecture preserves high-quality audio using 32-bit data path, 32-bit multiplies, bits precision some internal calculations. using 24-bit filter coefficients, TAS3001 implement practically second-order filter with outstanding fidelity. Texas Instruments several tools that provide powerful flexible means develop applications using TAS3001. Section provides examples TAS3001 used meet various system needs.
ATTENUATION FREQUENCY
Attenuation Frequency
Figure 1-6. Combed Response Multiple Filters
Bass Treble Controls
TAS3001 bass treble controls that adjusted dynamically. These controls adjusted throughout their entire range without experiencing pops, clicks, other audible artifacts. This permits user have listening experience much like what experienced when adjusting high-quality analog controls. Figure shows response bass treble filters plotted 3-dB intervals 44.1-kHz sample-rate data.
ATTENUATION FREQUENCY
Attenuation Frequency
Figure 1-7. Bass Treble Filters
Soft Volume True Soft Mute
TAS3001 contains proprietary soft volume update. This allows smooth pleasant-sounding change from volume level another over entire range volume mute). volume adjustable downloading 4.20 gain coefficient through interface. Mute implemented loading zeros volume control register. This causes volume ramp down over 2048 samples final output zero dB).
1.10 Dynamic Range Compression
Every system, whether analog digital, limited dynamic range. dynamic range exceeded when system able reproduce smallest largest amplitudes input signal. example exceeding dynamic range system when listener turns volume stereo only have system start producing distortion. This classical problem dynamic range limitation. developed technology manage dynamic range while providing best overall listening experience. These techniques used recording process playback process. This technology available TAS3001 dynamic range compressor. operation, system gain such that low-level signals fully audible. When large signals encountered, system gain temporarily decreased prevent signal from exceeding dynamic range power output system producing distortion. systems with very limited dynamic range limited output power capability, dynamic range compression produces greater perceived loudness than otherwise would available.
1.11 Reliability Flexibility Digital Filtering
Digital filtering provides outstanding consistency, reliability, flexibility. Once digital filter designed tested system, continues perform same manner without change. Because digital filters computed, their performance exceedingly consistent does change variations component matching, tolerances, environmental conditions, aging, effects moisture dust. Analog filters, however, affected these. performance analog filters improved, part, using high-quality precision components this comes with higher comparable cost. greatest strengths digital filter flexibility. Each filter completely specified five 24-bit coefficients. modifying value more filter coefficients, both filter value filter type changed. system, these modifications produce different crossover curves, different equalization curves, different sound effects changing relative phase left right loudspeakers) different user graphical equalization settings. Attempting similar changes analog filter would require component changes potentially circuit layout. flexibility digital filtering provides particular advantage digital equalization. Because programmability, single design using digital filtering provide wide range filtering functions. result, this design span number applications. product that production, digital filtering permit equalization changes with minimal cost impact because this programmability. concern about digital filters that some implementations have been prone zero-input limit cycles. This condition where filter oscillates level when signal presented. digital audio system, this condition present itself tone low-level noise. TAS3001 patent-pending technique combat this problem.
1.12 Assignments
PACKAGE (TOP VIEW)
DVSS DVDD SDIN1 SDIN2 SDOUT MCLK LRCLK SCLK AVSS_PLL AVDD_PLL CAP_PLL
RESERVED SCLKOUT LRCLKOUT RESET POWERDOWN RESERVED
internal connection
Figure 1-8. TAS3001 Location Diagram
1.13 Functions
TERMINAL NAME AVDD_PLL AVSS_PLL CAP_PLL DVDD DVSS LRCLK LRCLKOUT MCLK POWERDOWN RESET RESERVED SCLK SCLKOUT SDIN1 SDIN2 SDOUT 20-22, Analog power supply Analog ground 1500 0.068 (recommended) address high address high Digital power supply Digital ground left/right clock sampling frequency (fs) LRCLK generated from input MCLK (usually normally routed (LRCLK) input sample clock. Master clock Reserved connection normal operation Powerdown input Reset, high normal operation, reinitialize device Reserved digital ground normal operation Slave serial clock Shift clock (bit clock) SCLK generated from input MCLK (usually normally routed (SCLK) input clock. Slave serial data Serial audio data input Serial audio data input Serial audio data output DESCRIPTION
NOTE: Reset other control functions require MCLK running. system reset operation synchronous operation requires minimum four MCLK cycles reset device.
1.14 Ordering Information
PACKAGE 70°C SMALL OUTLINE (PW) TAS3001CPW
1.15 Power Supply
Digital supply voltage-DVDD, DVSS Analog supply voltage-AVDD-PLL, AVSS-PLL NOTE: AVDD AVSS derived from digital supply digital ground.
Audio Data Formats
Serial Audio Interface
TAS3001 operates digital audio slave mode only. TAS3001 supports three serial audio data formats: I2S, left-justified, right-justified. Data word lengths bits supported. Data input into SDIN1 SDIN2 under influence master clock (MCLK), left/right clock (LRCLK), shift clock (SCLK) inputs. There options selecting clock rates. MCLK rate selected, terminal (CLKSEL) tied high MCLK rate times sampling frequency must supplied. MCLK selected, CLKSEL tied MCLK times sampling frequency must supplied. both cases, LRCLK SCLK must supplied. MCLK SCLK must synchronous their rising falling edges must least apart. Data output SDOUT under influence master clock (MCLK) input plus left/right clock (LRCLKOUT) shift clock (SCLKOUT) outputs. LRCLKOUT SCLKOUT generated from MCLK input (usually fs). Typically these routed LRCLK input sample clock) SCLK input clock). TAS3001 device compatible with different serial interfaces. Available interface options I2S, right-justified, left-justified. Table Table indicate options selected using main control register (MCR, address 01h). serial interface options either bits operate with SCLK 16-bit mode, left-justified, operate Table 2-1. Serial Interface Input Options
MODE BITS F(1,0) BITS W(1,0) SERIAL INTERFACE SDIN1, SDIN2 16-bit, left-justified, 16-bit, left-justified, 16-bit, right-justified, 16-bit, I2S, 18-bit, left-justified, 18-bit, right-justified, 18-bit, I2S, 20-bit, left-justified, 20-bit, right-justified, 20-bit, I2S,
Table 2-2. Serial Interface Output Options
MODE BITS E(1,0) BITS W(1,0) SERIAL INTERFACE SDOUT 16-bit, left-justified, 16-bit, left-justified, 16-bit, right-justified, 16-bit, I2S, 18-bit, left-justified, 18-bit, right-justified, 18-bit, I2S, 20-bit, left-justified, 20-bit, right-justified, 20-bit, I2S,
Figure through Figure illustrate relationship between SCLK, LRCLK, serial data input output protocol options.
2.1.1
Serial Format
following characteristics this protocol: LRCLK left/right clock. left channel transmitted when LRCLK low. right channel transmitted when LRCLK high. SDIN sampled with rising edge SCLK. SDOUT transmitted falling edge SCLK. LRCK must have duty cycle.
SCLK
LRCLK
SDIN
SDOUT
Left Channel
Right Channel
Figure 2-1. I2S-Compatible Serial Format
2.1.1.1 Signal Timing
PARAMETER tc(SCLK) td(SLR) td(SDOUT) tsu(SDIN) th(SDIN) SCLK frequency SCLK rising LRCLK edge SDOUT valid from SCLK falling (see Note SDIN setup before SCLK rising edge SDIN hold after SCLK rising edge LRCLK Duty cycle NOTE Maximum 50-pF external load SDOUT. 44.1/48 1/(256 6.144 UNIT
tc(SCLK) SCLK td(SLR) LRCLK td(SDOUT) SDOUT1 SDOUT2 SDOUT0
tr(SCLK)
tf(SCLK)
td(SLR)
SDIN1 SDIN2
Figure 2-2. Right/Left Justified, I2S, Left/Left Justified Serial Protocols
2.1.2
Left-Justified Serial Format
following characteristics this protocol: LRCLK left/right clock. left channel transmitted when LRCLK high. right channel transmitted when LRCLK low. SDIN data justified leading edge LRCLK. MSBs transmitted same time LRCLK edge, captured very next rising edge SCLK. Serial data sampled into device rising edge SCLK. Serial data transmitted device falling edge SCLK. SCLK LRCLK SCLK only supported 16-bit data) LRCLK this mode, LRCLK does have duty-cycle clock. number bits used interface sets minimum duty cycle. There must enough SCLK pulses shift data.
SCLK
LRCLK
SDIN
SDOUT
tsu(SDIN)
th(SDIN)
Left Channel
Right Channel
Figure 2-3. Left-Justified Serial Format
2.1.3
Right-Justified Serial Format
following characteristics this protocol: LRCLK left/right clock. left channel transmitted when LRCLK high. right channel transmitted when LRCLK low. SDIN data (recorded data) justified trailing edge LRCLK. Serial data sampled rising edge SCLK. Serial data transmitted falling edge SCLK. this mode, LRCLK does have duty-cycle clock. number bits used interface sets minimum duty cycle. There must enough SCLK pulses shift data.
SCLK
LRCLK
SDIN1
SDOUT
Left Channel
Right Channel
Figure 2-4. Right-Justified Serial Format
LRCLKOUT SCLKOUT
digital audio processor on-chip logic sequenced using internal system clock that derived from MCLK (master clock). Also derived from MCLK LRCLKOUT SCLKOUT signals that provide clocks TAS3001 other devices system. TAS3001 allows multiple system clocking schemes. Figure 2-5, TAS3001 provides system clocks (LRCLK SCLK) other parts system. Figure 2-6, system master, other than TAS3001, provides system clocks (LRCLK SCLK) TAS3001.
MCLK TAS3001 LRCLKOUT SCLKOUT SCLK LRCLK TLC320AD77 (Codec)
Crystal Oscillator
MCLK LRCLK SCLK
Figure 2-5. Master Mode
MCLK
S/PDIF Receiver
MCLK LRCLK TAS3001 SCLK SCLK LRCLK TLC320AD77 (Codec)
Figure 2-6. Slave Mode
Serial Control Interface (I2C)
TAS3001 operation controlled using RESET signal serial control interface. Control information downloaded into TAS3001 control registers master device, such microprocessor, microcontroller DSP. These registers control settings volume, bass, treble, mixing, filtering, dynamic range compression. description register addresses control formats given Appendix employs signals, (data) (clock), communicate between integrated circuits system. Each device addressed sending unique 7-bit slave address plus byte). compatible devices controlled using signals using wire-ANDed connection. pullup resistor must used high level bus. TAS3001 operates standard mode kbps with many devices desired capacitance load limit TAS3001 slave-only device; therefore, least device connected with this device must operate master mode. pullup resistor generally 4.99 Upon power unknown state until master clock been applied TAS3001 been reset. Prior reset, TAS3001 hold and/or lines low. This will create communication errors other device that attempts bus.
Protocol
standard uses transitions data (SDA) while clock high indicate start stop conditions. high-to-low transition indicates start, low-to-high transition indicates stop. Normal data-bit transitions must occur within time clock period. These conditions shown Figure 3-1. These start stop conditions required standard protocol generated master. master must also generate 7-bit slave address read/write (R/W) open communication with another device then wait acknowledge condition. slave holds during acknowledge clock period indicate acknowledgment. When this occurs, master transmits next byte sequence. After each 8-bit word, acknowledgment must transmitted receiving device. There limit number bytes that transmitted between start stop conditions. When last word transfers, master generates stop condition release bus. generic data transfer sequence shown Figure 3-1. Definitions protocol terms listed Table 3-1.
Slave Address
Subaddress
Data Address
Data Address
Start Stop
Figure 3-1. Typical Data Transfer Sequence Table 3-1. Protocol Definitions
DEFINITION Master Receiver Slave device that receives data device addressed master DESCRIPTION device that initiates transfer, generates clock signals, terminates transfer
Operation
permit multiple devices controlled bus, each slave device address. TAS3001 been assigned four unique addresses permit multiple TAS3001s used system. addresses selected using pins. These four addresses, listed Table 3-2, licensed addresses conflict with other licensed audio devices. communicate with TAS3001, master must address 01101XX. addition 7-bit device address, subaddresses used direct communication proper memory location within device. complete table subaddresses control registers provided Appendix Software Interface. Table 3-2. TAS3001 Address
ADDRESS BYTE A6-A2 01101 01101 01101 01101 CS2(A1) CS1(A0)
3.2.1
Write Cycle Example
example write cycle demonstrated Figure Table 3-3.
Start Slave Address Subaddress Data Byte Data Byte Data Byte Data Byte Stop
Figure 3-2. Write Cycle Example Table 3-3. Write Cycle Example
FUNCTION Start Slave address Subaddress Data Stop DESCRIPTION Start condition defined 0110100 (CS1 (write) Acknowledgement defined (slave) 00000110 (see Appendix Software Interface) 00011100 (see Appendix Software Interface) Stop condition defined
Whenever writing subaddress, correct number data bytes must follow order complete write cycle. example, volume control register with subaddress written bytes data must follow; otherwise, cycle will incomplete errors will occur.
3.2.2
Timing Wait Cycles
TAS3001 issues wait cycles regulate flow command information. TAS3001 issue wait cycles each instruction. instruction, TAS3001 issue sample wait between data bytes between last data byte stop. This wait generated after acknowledgement. duration this wait cycle slightly longer than sample interval, order 44.1 kHz). This wait cycle illustrated Figure 3-3.
Start Slave Address Subaddress Data Byte Wait Data Byte Wait Data Byte Wait Data Byte Wait Stop
Figure 3-3. Wait Cycle Example TAS3001 also issue wait state after receiving entire volume tone command. TAS3001 produces these wait cycles while executes interpolation algorithms from present setting setting. volume command always takes same amount time process given sample rate. treble bass commands will vary depending upon current index destination index. E.g., moving from vice versa will produce longest wait.
However, this wait cycle does occur during volume tone change command, instead occurs during next command after acknowledgement first data byte. Table gives typical values wait states TAS3001 commands. Table 3-4. Wait States
SYSTEM SAMPLING FREQUENCY Volume Bass Treble Mixer Equalization None None 44.1 None None None None None None COMMENT dependent size change
operation sequence that TAS3001 uses assert wait cycle TAS3001 detects valid start condition correct device this point TAS3001 issues ACK. TAS3001 decodes eight-bit subaddress issues another ACK. TAS3001 decodes first data byte issues third ACK. this point, TAS3001 device hold clock line until internal controller ready accept more data. This slave wait state. There ways master handle slave wait. preferred handle wait states master that recognizes wait states. During wait-state period, master stops sending data over I2C. this case, when master releases clock high after slave latch next data), master monitors line ensures that slave released SCL. Once been released master start next transmission. Alternatively, this function available system controller, fixed delays implemented system software ensure that TAS3001 ready receive additional data. Sending data while TAS3002 device busy will cause errors device will lock have reset.
Issuing stop command middle transaction puts TAS3001 slave block into unknown state, possibly locking controller causing send incorrect data signal processing block.
3.2.3
Resetting TAS3001 Interface
TAS3001 back into known state, transaction with subaddress followed bytes zeros clears slave block buffer. Resetting device also puts into known state. During normal operation, TAS3001 should never issue NACK. TAS3001 issues NACK, this indication protocol discrepancy.
3.2.4
Power-Up Conditions
Upon system power initialize mode which line held low. This prevents operations from being performed. prevent this from occurring, always hold RESET minimum MCLK clock cycles after applying power. Upon reset, TAS3001 goes through initialization sequence with duration
3.2.5
f(scl) tBUF tw(low) tw(high) th(STA) tsu(STA) th(DAT) tsu(DAT)
Serial Port Timing
PARAMETER clock frequency free time between start stop Pulse duration, clock (see Note Pulse duration, clock high (see Note Hold time, repeated start Setup time, repeated start Hold time, data Setup time, data Rise time Fall time 1000 UNIT
tsu(STO) Setup time stop condition device must internally provide hold time least signal bridge undefined region falling edge SCL. NOTES: tw(low) measured from beginning tw(high) measured from beginning
tBUF
Valid th(STA) th(DAT) th(STA) tsu(DAT) tsu(STA) tsu(STO)
Change Data Allowed
Data Line Stable
Figure 3-4. Serial Port Timing
Digital Audio Processor
Input Mixer Control
TAS3001 capable mixing channels serial audio data. mixer permits each input scaled independently then stereo summation performed. important function this circuit scale input signals down compensate gains equalization settings bass treble controls. This prevents system from exceeding maximum digital signal output. mixer operation controlled loading values into MIXER1 (07h) MIXER2 (08h) control registers. mixer control values 4.20 format-4 bits integer bits fraction. formula converting number log(X), where positive number. mute mixer channel, loaded into respective mixer control register. order transmit mixer control values over I2C, necessary separate each value into three bytes. first nibble byte integer; second nibble byte bytes fraction. Table contains converted into 4.20 numbers range although positive 4.20 number used. mixer operation updated instantly response control register change. This cause audible artifacts when changing mixer settings outside fast load mode.
Biquad Block
biquad block consists digital biquad filters channel organized cascade structure shown Figure 4-1. Each these biquad filters five downloadable 24-bit (4.20) coefficients. Each stereo channel independent coefficients.
Biquad Biquad Biquad
Figure 4-1. Cascaded Biquad Filters
4.2.1
Filter Coefficients
filter coefficients TAS3001 downloaded through port loaded into biquad memory space. Digital audio data coming into device processed biquad filters then output from device, usually external DAC. biquad filter downloaded processed TAS3001. biquad structure that used parametric equalization filters H(z) coefficients these filters quantized represented 4.20 format-4 bits integer part bits fractional part. Each biquad uses five coefficients define operation.
Volume Control Functions
4.3.1 Soft Volume Update
TAS3001 implements proprietary soft volume update. This update allows smooth pleasant-sounding change from volume level another over entire range volume mute).
volume adjustable downloading 4.20 gain coefficient through interface register (04h). Table Appendix lists 4.20 coefficient values 0.5-dB volume steps range However, positive 4.20 values other than those listed Table allowed. Right left channel volumes unganged different values implement balance control.
4.3.2
Software Soft Mute
Mute implemented loading zeros volume control register. This causes volume ramp down automatically over maximum 2048 samples final output zero dB).
Tone Controls
4.4.1 Treble Control
treble gain level adjusted within range with step resolution. level changes accomplished downloading byte treble control codes into treble control register (05h). bass control codes shown Appendix Table A-7.
4.4.2
Bass Control
bass gain level adjusted within range with step resolution. level changes accomplished downloading byte bass control codes into bass control register (06h). treble control codes shown Appendix Table A-8.
4.4.3
Frequency Dependence Treble Bass Controls
bass treble controls based upon fixed filter coefficients. coefficients define response that based upon data sample rate. result, sample rate increased decreased factor, filter frequency response will increase decrease frequency equal factor. Table Table show relationship between sample frequency corner frequency bass treble controls. Table 4-1. Bass Control Corner Frequencies
Sampling Rate Corner Frequency 32,000 72.6 44,100 100.0 48,000 108.8 96,000 217.7
Table 4-2. Treble Control Corner Frequencies
Sampling Rate Corner Frequency 32,000 7,256 44,100 10,000 48,000 10,884 96,000 21,769
Dynamic Range Compression (DRC)
TAS3001 provides user with ability manage dynamic range audio system. receives data after bass control block, effects scaling after volume control block.
Dynamic Range Compression SDIN1
SDIN2 2-Channel Stereo Mixer
2nd-Order Filters
Treble/ Bass
Volume
SDOUT
Figure 4-2. Audio Processing Architecture fixed compression ratio 3:1.
attack time constant release time attack time constant point where compressor reached programmed compression. release time constant point where compressor released uncompressed level. controlled writing two-byte control word (02h). first byte control word must 11XX XXX1. Setting first byte other value results unpredictable operation. second byte control word threshold value. threshold largest amplitude limit before compression occurs. signals larger than threshold compressed. compression threshold adjustable increments between approximately Table appendix shows available threshold values. Setting threshold disables DRC. enabled when threshold desired operating point.
OUTPUT (dB)
Compression Ratio
INPUT (dB)
Figure 4-3. Example example shown Figure 4-3. formula calculating output with given threshold fixed compression ratio Final output (dB) (dB) [Vref (dB)-T (dB)] Where: compression ratio Threshold (dB) Vref Reference voltage (normally shown figure, with threshold input exceeds this value, then output will compressed ratio until maximum input yields output
Device Operation
Device Initialization
5.1.1 Reset
reset allows device reset. reset operation synchronous operation requiring MCLK perform sequence reset operations. During reset, TAS3001 returns default state described this section. TAS3001 does reset automatically when power applied device. reset required after power applied power pins. Required conditions successful reset: MCLK running. RESET minimum MCLK cycles.
reset operation typically takes complete. Once reset completed, master control register (MCR) should set. sets serial mode fast load. recommended that only once, following reset.
5.1.2
Device Power System Reset
When power applied TAS3001, device powers unknown state. must reset before device will known state. recommended that RESET applied following power TAS3001 performs internal reset operations then ready operation. Following reset, TAS3001 initializes default state (fast load mode). main control register configured 1XXX XXXX, where initialized, shown Figure (see Appendix complete description MCR). Only fast load main control register. This puts device into fast load mode (see Section 5.1.3, Fast Load). random access memory (RAM) will initialized (previous data will overwritten).
Figure 5-1. Main Control Register (MCR) address pins (CS1 CS2) should driven biased TAS3001 known address. This also ensures port active immediately after reset initialization phase. Furthermore, when implementing three- six-speaker system, pins must always driven unique addresses devices. port powered does acknowledge activity until entire device been initialized. This initialization typically takes
5.1.3
Fast Load
During initialization, system enters fast-load mode. Upon entering fast-load mode, following occur part initialization: parametric initialized (all-pass). tone (bass/treble) function sets SDIN1 SDIN2 mute (no-pass). volume mute.
While fast-load mode, possible update parametric without audio processing delay. audio processor pauses while being updated this mode. recommended that parametric downloaded this mode. Bass treble cannot downloaded this mode. Mixer1 Mixer2 registers downloaded this mode normal mode recommended download volume control register mixer registers this mode. Once download complete, fast-load needs cleared writing into main control register. This puts TAS3001 into normal mode. NOTE: While fast-load mode, TAS3001 does accept audio. device must normal mode before accept process audio data. When coming fast-load mode, good practice sure that system muted. This prevents system from producing spurious pops clicks. Once back normal mode, treble, bass, volume controls downloaded complete device setup.
Power Consumption
During normal operation average power consumption When RESET held low, asserted, TAS3001 draws average current
Power Down Start-Up
TAS3001 placed low-power mode. entered synchronously asserting POWERDOWN high, logic followed asserting RESET low, logic microsecond later. Figure illustrates timing power down. MCLK must present TAS3001 enter power-down mode.
MCLK
RESET
POWERDOWN NOTE: RESET POWERDOWN have synchronized with MCLK.
Figure 5-2. Power-Down Timing recover from power-down state, POWERDOWN low, logic followed asserting RESET high, logic microsecond later. Figure illustrates timing start-up. MCLK must present TAS3001 exit power-down mode.
MCLK
RESET POWERDOWN
NOTE: RESET POWERDOWN have synchronized with MCLK.
Figure 5-3. Start-Up Timing
Electrical Characteristics
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
Supply voltage range, AVDD_PLL, DVDD -0.3 Digital input voltage range -0.3 Operating free-air temperature range, 70°C Storage temperature range, Tstg -65°C 150°C Case temperature seconds, 122.3°C Lead temperature from case seconds 97.8°C tolerance 2000
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. Human body model method 3015.2 MIL-STD-883B.
Recommended Operating Conditions
supply voltage, AVDD Digital supply voltage, DVDD Capacitive load each line CL(bus) (SDA, SCL) Operating free-air temperature, UNIT
Power Consumption
PARAMETER TEST CONDITIONS 32-48 SAMPLE RATE load load, Reset active load, Standby SAMPLE RATE UNIT
digital supply current,
Static Digital Specifications
PARAMETER IOZ(H) IOZ(L) High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current SCL, SCL, TEST CONDITIONS -0.3 +0.3 UNIT
Serial Data S/PDIF Receiver Clocks Digital Amplifier Control Initialization Power Down Digital Amplifier
Figure 6-1. Typical TAS3001 Connection
Control Micro controller
TAS3001
RESERVED DVSS DVDD SCLKOUT SDIN1 LRCLKOUT SDIN2 SDOUT MCLK RESET LRCLK SCLK AVSS_PLL AVDD_PLL POWERDOWN RESERVED CAP_PLL
Digital 4.99 4.99
Ohms 1500 Serial Data
Measured Audio Performance Some Typical Examples
illustrate performance TAS3001, series measurements performed system shown Figure 7-1.
Measurement System
S/PDIF Receiver
TAS3001
S/PDIF Transmitter
Control Interface TAS3001 Test System
Figure 7-1. Audio Performance Measurement System system performance measured three filter types kHz. Butterworth high-pass filter Butterworth low-pass filter filter with gain bandwidth
audio performance that measured shown Table 7-1. response shapes three test filters shown Figure 7-2. Table 7-1. Audio Filter Performance
PARAMETER All-pass THD+N 1-kHz second-order Butterworth high- low-pass filters 1-kHz 500-Hz bandwidth filters filters FILTER CONDITIONS mixer 48-kHz mixer 48-kHz mixer MEASURED -110 0.0003% -106 0.0005% -108 0.0004% 0.001%
ATTENUATION FREQUENCY
Attenuation
Frequency
Figure 7-2. Audio Performance Test Filters
Using TAS3001 System
TAS3001 Applications
TAS3001 used perform number audio processing functions. TAS3001 used perform parametric equalization correct frequency response pair loudspeakers microphones shown Figure 8-1. this case TAS3001 used shape frequency response transducers applying filters compensate response irregularities each transducer (peaks valleys microphone loudspeaker response).
Interface
TAS3001 TUSB3200 TAS1020 Streaming Controller TAS3001
TLC320AD77 Section
Conventional Amplifier
TLC320AD77 Section
Preamplifier
Figure 8-1. TAS3001 System Equalizer
filters developed evaluated using personal computer, TAS3001 EVM, speaker analysis package, automatic loudspeaker equalization program. next section will demonstrate Texas Instruments automatic loudspeaker equalization program that automates many steps developing filters loudspeaker equalization. second application TAS3001 perform both crossover frequency equalization individual loudspeaker drivers two- multi-way loudspeaker design Figure 8-2. this case TAS3001 provides functions; crossover band-pass band-limiting functions each speaker compensation response irregularities each loudspeaker driver.
S/PDIF Interface Digital Amplifier Tweeter DIR1703 S/PDIF Receiver TAS3001 TAS5100 Bridge TAS5100 TAS3001 TAS5100 Bridge Woofer
Figure 8-2. TAS3001 Crossover Equalizer third application TAS3001 perform volume/balance/fader controls, bass treble adjustment, loudspeaker equalization dynamic range compression loudspeaker system Figure 8-3.
S/PDIF Receiver
Performing Decoding
TAS3001
Stereo Digital Amplifier
S/PDIF Interface
TAS3001
Stereo Digital Amplifier
TAS3001
Stereo Digital Amplifier
Figure 8-3. TAS3001 Dynamic Range Compressor Equalizer
Measurement-Based Speaker Correction
Although loudspeakers ideally should designed uniform sound pressure response function frequency, cost physical constraints usually result speakers that less than ideal. correct large nonlinearities response, shape response listener preferences, speaker equalization performed. example speaker response, shown Figure 8-4, seen that sound pressure level (y-axis) varies significantly function frequency (x-axis). speakers such this typical loudspeaker, equalization improve performance enhance listening experience.
Figure 8-4. Typical Small Loudspeaker Response addition equalization frequency response, TAS3001 used notch specific frequencies that excite mechanical resonances speaker. removal mechanical resonances improves temporal response loudspeaker that more accurately reproduces recorded signal. small ported loudspeakers, high-pass filter eliminates signal energy that lower than speaker reproduce. This filtering improves loudspeaker power handling intelligibility eliminating large cone excursions produced signals that below loudspeaker resonant frequency. kinds corrections being discussed here begin with thorough understanding inherent operation particular loudspeaker. This information best obtained means measurement such that shown Figure 8-4. measurement information allows equalization designer find resonances other problems associated with speaker, correct them.
Sound-Based Speaker Correction
While high-quality speaker measurement extremely valuable equalization designer, many good equalization designers also rely upon their perception sound from speaker. Based upon what they measure hear, designers able design filters achieve specific frequency response desired sonic character. Digital filters used provide these corrections shape produced sound.
Loudspeaker Equalization Example
example loudspeaker equalization follows. Figure 8-4, loudspeaker frequency response shown. Figure designer specifies desired response that center three lines. lines above below center line tolerances. tolerances adjusted.
Figure 8-5. Preparation Equalization Figure shows corrected loudspeaker response that been developed program.
Figure 8-6. After Equalization
Figure shows filters that were used equalize loudspeaker response.
Figure 8-7. Equalization Filters
Speaker Correction Equalization
Digital filters able provide fairly broad range filter types responses. TAS3001 contains programmable filters. system designer choice using these filters. filters used equalize response peaks dips from desired response. They also used shape loudspeaker phase response. Because their available precision temperature insensitivity, only filters used equalize frequency phase response loudspeaker closely, they also used remove resonances other small deviations response loudspeaker surgically. This permits system designer greater degree flexibility design both individual loudspeaker drivers cabinet. additional filtering needed, multiple TAS3001s cascaded. This enables greater freedom design acoustical systems. TAS3001 permits additional flexibility transducer design. Overall flatness transducer response longer overriding concern with low-cost/high-performance frequency correction TAS3001. constraints transducer design relaxed that they provide optimum performance after correction. This, turn, allows transducer equalization designed system, providing wide flexibility design achieving outstanding sound presentation.
TAS3001 Implement Nearly Second-Order Filter
Filter designs computational resources, uncommon simplified filter implementations that must limit either number nature filters that implemented. example, particular architecture might impose limits gains, and/or center frequencies that implemented. This, however, case with TAS3001. high-precision, patent-pending structure allows implementation almost second-order filter. These implemented almost limitless range filter functions without fear degradation limit cycles increased system noise. Additionally, higher order filters developed factoring desired filter into consecutive multiple second-order sections. Similarly, filter that been designed analog converted implemented digital filter.
ATTENUATION FREQUENCY
Attenuation
Frequency
Figure 8-8. Individual Filters From left right filters that shown Figure are: Variable high-pass filter with emphasize bass prevent distortion cutting frequencies below cabinet resonance Equalization filters various amplitudes, center frequencies, bandwidths treble shelf Chebychev low-pass filter with ripple attenuate high frequencies combined response these filters shown Figure 8-9.
ATTENUATION FREQUENCY
Attenuation
Frequency
Figure 8-9. Combined Response
Converting Analog Filters Digital
Many audio engineers already using analog equalization. satisfactory analog filters already been defined, user convert those analog filters digital. This perhaps easiest started. converting analog filters digital, please refer Digital Signal Processing, Oppenheim, Schafer, Prentice-Hall, 1975, 197-211. This information also available almost digital signal processing textbook. Users Matlab perform these manipulations easily using BILINEAR IMPINVAR commands available Matlab signal processing toolbox.
Automatic Loudspeaker Equalizer
simplify process designing digital filters implementation TAS3001, Texas Instruments provides filter design tool called Automatic Loudspeaker Equalizer, ALE. Details this tool provided this section.
Automatic Generation Equalization Filters Given Measurement
capability reading speaker environment measurement. user then provide desired speaker response. From these inputs, automatically produce optimized filters equalize speaker. patent-pending optimization algorithm developed Texas Instruments. example operation shown Figure through Figure 8-7.
Automatic Approximation Equalization Curve
When desired equalization transfer function known, problem becomes finding digital second-order filters implement case where H(s) known, converted digital filter using bilinear impulse invariant method. resulting transfer function (H(z)) then factored implemented combination second- first-order sections using TAS3001. (This factoring capability included ALE, accomplished simply Matlab.) However, many cases desired transfer function specified curve. this case, curve read ALE. Then approximation generated manually (see manual filter generation method below) automatically. automatic mode, again uses patent-pending optimization technique developed Texas Instruments.
Manual Filter Design
many cases, user already filter specifications just needs designing such filters. such cases, ordinary filter parameters, such gain, bandwidth, center frequency entered into ALE, which then provides coefficients desired filters. filters generated, displays responses individual filters composite filter response. addition, manual filter generation capability used conjunction with automatic capability (see Section 9.2). user specify filters manually allow optimize them generate additional filters automatically needed. user also specify manual filters automatically generate additional filters needed without disturbing manually-generated filters. addition, user manually modify filters created ALE. graphical user interface allows easy manipulation filters movement between automatic manual filter generation modes.
Conversion Decimal Filter Coefficients TAS3001 Format
filters generated saved TAS3001 hexadecimal format integer bits, fraction bits, complement). read filters decimal, convert them hexadecimal format needed implementation TAS3001.
Editing TAS3001 File Format
read write filter files TAS3001 format. This allows filters generated stored format used TAS3001 control software. addition, read TAS3001 filter files display filters.
Examples Filter Types Available From
current time following filter types designed ALE: Equalization (bell-shaped) filters with variety center frequencies, gains, shown Figure 9-1.
Figure 9-1. Equalization Filters Similarly, system design variety high- low-pass filters such Butterworth, Linkwitz-Riley, Type Chebychev. Examples Butterworth, Linkwitz-Riley, high- low-pass filters with equal frequencies (and pass-band ripple specification Chebychev filters), shown Figure 9-2.
Figure 9-2. High- Low-Pass Filters
Treble bass shelf filters employed with various gains corner frequencies shown Figure 9-3.
Figure 9-3. Treble Bass Shelf Filters Notch filters employed remove energy that excites mechanical resonances loudspeakers shown Figure 9-4.
Figure 9-4. Notch Filters also supports number filters which shown here, including Chebychev high/low plateau, Linkwitz-Riley, variable versions developed, more filter types will added. addition, Texas Instruments filtering engineers available help TAS3001 users design needed filter type.
FilterBuilder FilterMaker
make filter creation simple possible everyone, Texas Instruments provide tools addition (previous section). FilterBuilder Excel spreadsheet based manual filter creation tool. While nearly capable ALE, simple effective started quickly with filter creation. FilterMaker another manual filter creation tool created Texas Instruments. runs Matlab environment. This might choice those prefer work Matlab, would like additional capabilities their filter generation tool. addition, engineers additional filter types either these tools.
10-1
10-2
Appendix Software Interface
Table A-1. Register
REGISTER Reserved Reserved Volume Treble Bass Mixer Mixer Reserved Left Biquad Left Biquad Left Biquad Left Biquad Left Biquad Left Biquad Reserved Right Biquad Right Biquad Right Biquad Right Biquad Right Biquad Right Biquad ADDRESS 10h-12h B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) VL(23-16), VL(15-8), VL(7-0), VR(23-16), VR(15-8), VR(7-0) T(7-0) B(7-0) S(23-16), S(15-8), S(7-0) S(23-16), S(15-8), S(7-0) C(7-0) Dynamic Range Compression, Section 1.10. BYTES BYTE DESCRIPTION
Reserved 19h-FFh volume value 4.16 coefficient. order transmit over I2C, necessary separate value into three bytes. Byte (MSB) integer part bytes fractional part. mixer gain values biquad coefficients 4.20 coefficients. order transmit them over I2C, necessary separate value into three bytes. first nibble byte (MSB) integer part; second nibble byte bytes fractional part.
Main Control Register (MCR)
Configuration digital serial audio interface through main control register shown Table Table A-3. Bits allow selection between three different serial data formats (left justified right justified standard 10). output serial port mode must same value input serial port mode Bits allow selection between three different word widths (16-bit word 18-bit word 20-bit word 10). selects 32fs 64fs clock. primarily during initialization defined Device Initialization (see Section 5.1). Section Serial Control Interface, additional information address main control register.
Table A-2. Main Control Register (MCR)
Table A-3. Main Control Register (MCR) Description
C(7) C(6) C(5,4) DESCRIPTOR E(1,0) FUNCTION Fast load SCLK frequency Output serial port mode VALUE (default) C(3,2) F(1,0) Input serial port mode C(1,0) W(1,0) Serial port word length FUNCTION Normal operating mode Fast load mode SCLK SCLK Left justified Right justified Reserved Left justified Right justified Reserved Reserved
Table A-4. Interface (Byte
Table A-5. Interface (Byte
BYTE (BITS) 1001 0000 1001 0001 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 BYTE (BITS) 1001 0000 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 DESCRIPTION ILLEGAL
1111 0000 1111 0000 NOTE: interface byte sets threshold value. must always greater than (1001 0000). Legal values range from F0h.
Table A-6. Volume Gain Values [The gain error less than 0.12 (excluding mute)]
VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0)
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0
GAIN (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5
GAIN (dB) -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5
GAIN (dB) -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5
GAIN (dB) -54.0 -54.5 -55.0 -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute
Table A-7. Treble Control Register (Both left right channel will given same treble gain setting)
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 T(7-0) (hex) Gain (dB) 10.5 10.0 T(7-0) (hex) Gain (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 T(7-0) (hex) Gain (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 T(7-0) (hex) Gain (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 T(7-0) (hex)
Table A-8. Bass Control Register (Both left right channel will given same bass setting)
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 B(7-0) (hex) Gain (dB) 10.5 10.0 B(7-0) (hex) Gain (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 B(7-0) (hex) Gain (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 B(7-0) (hex) Gain (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 B(7-0) (hex)
Table A-9. Mixer1 Mixer2 Gain Values [The gain error less than 0.12 (excluding mute)]
Gain S(23-16), S(15-8), S(7-0) Gain S(23-16), S(15-8), S(7-0) Gain S(23-16), S(15-8), S(7-0) Gain S(23-16), S(15-8), S(7-0) Gain S(23-16), S(15-8), S(7-0)
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0
Gain (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5
Gain (dB) -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5
Gain (dB) -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5
Gain (dB) -54.0 -54.5 -55.0 -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute
Appendix Mechanical Information
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153

Digital Audio Processor DAV-Audio Products SLAS226A IMP

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