AT80F52 low-power, high-performance CMOS 8-bit microcomputer with byte

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AT80F52 low-power, high-performance CMOS 8-bit microcomputer with byte

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Compatible with MCS-51Products Bytes Factory Programmable QuickFlashMemory Fully Static Operation: Three-Level Program Memory Lock 8-Bit Internal Programmable Lines Three 16-Bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Power Idle Power Down Modes
AT80F52 low-power, high-performance CMOS 8-bit microcomputer with bytes QuickFlash memory. device manufactured using Atmel's high density nonvolatile memory technology compatible with industry standard 80C51 80C52 instruction pinout. on-chip QuickFlash allows custom codes quickly programmed factory. combining versatile 8-bit with QuickFlash monolithic chip, Atmel AT80F52 powerful microcomputer which provides highly flexible cost effective solution many embedded control applications. (continued)
8-Bit Microcontroller with Bytes QuickFlashMemory AT80F52
Configurations
(T2) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7
PDIP
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
TQFP
(T2) (AD0) (AD1) (AD2) (AD3)
P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
P1.4 P1.3 P1.2 P1.1 P1.0 P0.0 P0.1 P0.2 P0.3
INDEX CORNER
(RXD) (TXD) (INT0) (INT1) (T0) (T1)
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
PLCC
(T2) (AD0) (AD1) (AD2) (AD3)
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
(WR) P3.6 (RD) P3.7 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
(RXD) (TXD) (INT0) (INT1) (T0) (T1)
P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
(WR) P3.6 (RD) P3.7 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
P1.4 P1.3 P1.2 P1.1 P1.0 P0.0 P0.1 P0.2 P0.3
INDEX CORNER
0980A-A-12/97
3-15
Block Diagram
P0.0 P0.7 P2.0 P2.7
PORT DRIVERS PORT DRIVERS
ADDR. REGISTER
PORT LATCH
PORT LATCH
QUICK FLASH
REGISTER
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP2
TMP1
BUFFER
INTERRUPT, SERIAL PORT, TIMER BLOCKS
INCREMENTER
PROGRAM COUNTER
PSEN PORT LATCH PORT LATCH TIMING CONTROL INSTRUCTION REGISTER DPTR
PORT DRIVERS PORT DRIVERS
P1.0 P1.7
P3.0 P3.7
3-16
AT80F52
AT80F52
AT80F52 provides following standard features: bytes QuickFlash, bytes RAM, lines, three 16-bit timer/counters, six-vector two-level interrupt architecture, full duplex serial port, on-chip oscillator, clock circuitry. addition, AT80F52 designed with static logic operation down zero frequency supports software selectable power saving modes. Idle Mode stops while allowing RAM, timer/counters, serial port, interrupt system continue functioning. Power Down Mode saves contents freezes oscillator, disabling other chip functions until next hardware reset. Port Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins, they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because internal pullups. Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX DPTR). this application, Port uses strong internal pullups when emitting During accesses external data memory that 8-bit addresses (MOVX RI), Port emits contents Special Function Register. Port also receives high-order address bits some control signals during QuickFlash verification. Port Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins, they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because pullups. Port also serves functions various special features AT89C51, shown following table. Port also receives some control signals QuickFlash verification.
Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions (serial input port) (serial output port) INT0 (external interrupt INT1 (external interrupt (timer external input) (timer external input) (external data memory write strobe) (external data memory read strobe)
Supply voltage. Ground. Port Port 8-bit open drain bidirectional port. output port, each sink eight inputs. When written port pins, pins used highimpedance inputs. Port also configured multiplexed loworder address/data during accesses external program data memory. this mode, internal pullups. Port also outputs code bytes during program verification. External pullups required during program verification. Port Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins, they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because internal pullups. addition, P1.0 P1.1 configured timer/counter external count input (P1.0/T2) timer/counter trigger input (P1.1/T2EX), respectively, shown following table. Port also receives low-order address bytes during QuickFlash verification.
Port P1.0 P1.1 Alternate Functions (external count input Timer/Counter clock-out T2EX (Timer/Counter capture/reload trigger direction control)
Reset input. high this machine cycles while oscillator running resets device. Address Latch Enable output pulse latching byte address during accesses external memory. normal operation, emitted constant rate oscillator frequency used external timing clocking purposes. Note, however, that pulse skipped during each access external data memory. 3-17
desired, operation disabled setting location 8EH. With set, active only during MOVX MOVC instruction. Otherwise, weakly pulled high. Setting ALE-disable effect microcontroller external execution mode. PSEN Program Store Enable read strobe external program memory. When AT80F52 executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. External Access Enable. must strapped order enable device fetch code from external program memory locations starting 0000H FFFFH. Table AT80F52 Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H XX000000 11111111 0X000000 11111111 SCON 00000000 11111111 TCON 00000000 11111111 TMOD 00000000 00000111 00000000 00000000 00000000 00000000 SBUF XXXXXXXX 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 00000000 00000000
Note, however, that lock programmed, will internally latched reset. should strapped internal program executions. XTAL1 Input inverting oscillator amplifier input internal clock operating circuit. XTAL2 Output from inverting oscillator amplifier.
0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 00000000 00000000 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 00000000 00000000 PCON 0XXX0000
3-18
AT80F52
AT80F52
Special Function Registers
on-chip memory area called Special Function Register (SFR) space shown Table Note that addresses occupied, unoccupied addresses implemented chip. Read accesses these addresses will general return random data, write accesses will have indeterminate effect. User software should write these unlisted locations, since they used future products invoke Table T2CON-Timer/Counter Control Register
T2CON Address 0C8H Addressable EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Reset Value 0000 0000B
features. that case, reset inactive values bits will always Timer Registers: Control status bits contained registers T2CON (shown Table T2MOD (shown Table Timer register pair (RCAP2H, RCAP2L) Capture/Reload registers Timer 16-bit capture mode 16-bit auto-reload mode. Interrupt Registers: individual interrupt enable bits register. priorities each interrupt sources register.
Symbol EXF2
Function Timer overflow flag Timer overflow must cleared software. will when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 When Timer interrupt enabled, EXF2 will cause vector Timer interrupt routine. EXF2 must cleared software. EXF2 does cause interrupt up/down counter mode (DCEN Receive clock enable. When set, causes serial port Timer overflow pulses receive clock serial port Modes RCLK causes Timer overflow used receive clock. Transmit clock enable. When set, causes serial port Timer overflow pulses transmit clock serial port Modes TCLK causes Timer overflows used transmit clock. Timer external enable. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/Stop control Timer starts timer. Timer counter select Timer C/T2 timer function. C/T2 external event counter (falling edge triggered). Capture/Reload select. CP/RL2 causes captures occur negative transitions T2EX EXEN2 CP/RL2 causes automatic reloads occur when Timer overflows negative transitions occur T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
RCLK TCLK EXEN2 C/T2 CP/RL2
Data Memory
AT80F52 implements bytes on-chip RAM. upper bytes occupy parallel address space Special Function Registers. That means upper bytes have same addresses space physically separate from space. When instruction accesses internal location above address 7FH, address mode used instruction specifies whether accesses upper bytes space. Instructions that direct addressing access space.
example, following direct addressing instruction accesses location 0A0H (which P2).
0A0H, #data
Instructions that indirect addressing access upper bytes RAM. example, following indirect addressing instruction, where contains 0A0H, accesses data byte address 0A0H, rather than (whose address 0A0H).
@R0, #data
Note that stack operations examples indirect addressing, upper bytes data available stack space. 3-19
Timer
Timer Timer AT80F52 operate same Timer Timer AT89C51.
Timer
Timer 16-bit Timer/Counter that operate either timer event counter. type operation selected C/T2 T2CON (shown Table Timer three operating modes: capture, auto-reload down counting), baud rate generator. modes selected bits T2CON, shown Table Timer consists 8-bit registers, TL2. Timer function, register incremented every machine cycle. Since machine cycle consists oscillator periods, count rate 1/12 oscillator frequency. Table Timer Operating Modes
RCLK +TCLK CP/RL2 MODE 16-Bit Auto-Reload 16-Bit Capture Baud Rate Generator (Off)
show high cycle next cycle, count incremented. count value appears register during S3P1 cycle following which transition detected. Since machine cycles oscillator periods) required recognize 1-to-0 transition, maximum count rate 1/24 oscillator frequency. ensure that given level sampled least once before changes, level should held least full machine cycle.
Capture Mode
capture mode, options selected EXEN2 T2CON. EXEN2 Timer 16-bit timer counter which upon overflow sets T2CON. This then used generate interrupt. EXEN2 Timer performs same operation, 1to-0 transition external input T2EX also causes current value captured into RCAP2H RCAP2L, respectively. addition, transition T2EX causes EXF2 T2CON set. EXF2 bit, like TF2, generate interrupt. capture mode illustrated Figure
Auto-Reload Down Counter)
Timer programmed count down when configured 16-bit auto-reload mode. This feature invoked DCEN (Down Counter Enable) located T2MOD (see Table Upon reset, DCEN that timer will default count When DCEN set, Timer count down, depending value T2EX pin.
Counter function, register incremented response 1-to-0 transition corresponding external input pin, this function, external input sampled during S5P2 every machine cycle. When samples Figure Timer Capture Mode
C/T2
CONTROL C/T2 TRANSITION DETECTOR T2EX CONTROL EXEN2 EXF2 CAPTURE
OVERFLOW
RCAP2H RCAP2L TIMER INTERRUPT
3-20
AT80F52
AT80F52
Figure shows Timer automatically counting when DCEN this mode, options selected EXEN2 T2CON. EXEN2 Timer counts 0FFFFH then sets upon overflow. overflow also causes timer registers reloaded with 16-bit value RCAP2H RCAP2L. values Timer Capture ModeRCAP2H RCAP2L preset software. EXEN2 16-bit reload triggered either overflow 1-to-0 transition external input T2EX. This transition also sets EXF2 bit. Both EXF2 bits generate interrupt enabled. Setting DCEN enables Timer count down, shown Figure this mode, T2EX controls Figure Timer Auto Reload Mode (DCEN
C/T2 CONTROL C/T2 RCAP2H RCAP2L TRANSITION DETECTOR T2EX CONTROL EXEN2 EXF2 RELOAD TIMER INTERRUPT OVERFLOW
direction count. logic T2EX makes Timer count timer will overflow 0FFFFH bit. This overflow also causes 16-bit value RCAP2H RCAP2L reloaded into timer registers, TL2, respectively. logic T2EX makes Timer count down. timer underflows when equal values stored RCAP2H RCAP2L. underflow sets causes 0FFFFH reloaded into timer registers. EXF2 toggles whenever Timer overflows underflows used 17th resolution. this operating mode, EXF2 does flag interrupt.
Table T2MOD-Timer Mode Control Register
T2MOD Address 0C9H Addressable Symbol T2OE DCEN Function implemented, reserved future Timer Output Enable bit. When set, this allows Timer configured up/down counter. T2OE DCEN Reset Value XXXX XX00B
3-21
Figure Timer Auto Reload Mode (DCEN
(DOWN COUNTING RELOAD VALUE) 0FFH 0FFH TOGGLE EXF2
OVERFLOW C/T2 CONTROL C/T2 TIMER INTERRUPT RCAP2H RCAP2L COUNTING RELOAD VALUE) COUNT DIRECTION 1=UP 0=DOWN
T2EX
Figure Timer Baud Rate Generator Mode
TIMER OVERFLOW
NOTE: OSC. FREQ. DIVIDED SMOD1
C/T2 CONTROL C/T2 TCLK CLOCK RCLK CLOCK
RCAP2H RCAP2L TRANSITION DETECTOR T2EX CONTROL EXEN2 EXF2 TIMER INTERRUPT
3-22
AT80F52
AT80F52
Baud Rate Generator
Timer selected baud rate generator setting TCLK and/or RCLK T2CON (Table Note that baud rates transmit receive different Timer used receiver transmitter Timer used other function. Setting RCLK and/or TCLK puts Timer into baud rate generator mode, shown Figure baud rate generator mode similar auto-reload mode, that rollover causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software. baud rates Modes determined Timer overflow rate according following equation.
Timer Overflow Rate Modes Baud Rates
increments every state time oscillator frequency). baud rate formula given below.
Oscillator Frequency Modes 65536 (RCAP2H,RCAP2L) Baud Rate
Timer configured either timer counter operation. most applications, configured timer operation (CP/T2 timer operation different Timer when used baud rate generator. Normally, timer, increments every machine cycle 1/12 oscillator frequency). baud rate generator, however,
where (RCAP2H, RCAP2L) content RCAP2H RCAP2L taken 16-bit unsigned integer. Timer baud rate generator shown Figure This figure valid only RCLK TCLK T2CON. Note that rollover does will generate interrupt. Note too, that EXEN2 set, 1-to-0 transition T2EX will EXF2 will cause reload from (RCAP2H, RCAP2L) (TH2, TL2). Thus when Timer baud rate generator, T2EX used extra external interrupt. Note that when Timer running (TR2 timer baud rate generator mode, should read from written Under these conditions, Timer incremented every state time, results read write accurate. RCAP2 registers read should written because write might overlap reload cause write and/or reload errors. timer should turned (clear TR2) before accessing Timer RCAP2 registers.
Figure Timer Clock-Out Mode
(8-BITS) (8-BITS)
RCAP2L C/T2
RCAP2H
P1.0 (T2)
T2OE (T2MOD.1) TRANSITION DETECTOR P1.1 (T2EX)
EXF2
TIMER INTERRUPT
EXEN2
3-23
Programmable Clock
duty cycle clock programmed come P1.0, shown Figure This pin, besides being regular pin, alternate functions. programmed input external clock Timer/Counter output duty cycle clock ranging from operating frequency. configure Timer/Counter clock generator, C/T2 (T2CON.1) must cleared T2OE (T2MOD.1) must set. (T2CON.2) starts stops timer. clock-out frequency depends oscillator frequency reload value Timer capture registers (RCAP2H, RCAP2L), shown following equation.
Oscillator Fequency Clock-Out Frequency 65536 (RCAP2H,RCAP2L)
Table Interrupt Enable (IE) Register
(MSB) (LSB)
Enable enables interrupt. Enable disables interrupt.
Symbol
Position IE.7
Function Disables interrupts. interrupt acknowledged. each interrupt source individually enabled disabled setting clearing enable bit. Reserved. Timer interrupt enable bit. Serial Port interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit.
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
clock-out mode, Timer roll-overs will generate interrupt. This behavior similar when Timer used baud-rate generator. possible Timer baud-rate generator clock generator simultaneously. Note, however, that baud-rate clock-out frequencies cannot determined independently from another since they both RCAP2H RCAP2L.
UART
UART AT80F52 operates same UART AT89C52.
User software should never write unimplemented bits, because they used future AT89 products.
Figure Interrupt Sources
Interrupts
AT80F52 total interrupt vectors: external interrupts (INT0 INT1), three timer interrupts (Timers serial port interrupt. These interrupts shown Figure Each these interrupt sources individually enabled disabled setting clearing Special Function Register also contains global disable bit, which disables interrupts once. Note that Table shows that position IE.6 unimplemented. AT89C51, position IE.5 also unimplemented. User software should write these positions, since they used future AT89 products. Timer interrupt generated logical bits EXF2 register T2CON. Neither these flags cleared hardware when service routine vectored fact, service routine have determine whether EXF2 that generated interrupt, that will have cleared software. Timer Timer flags, TF1, S5P2 cycle which timers overflow. values then polled circuitry next cycle. However, Timer flag, TF2, S2P2 polled same cycle which timer overflows. 3-24
INT0
INT1
EXF2
AT80F52
AT80F52
Oscillator Characteristics
XTAL1 XTAL2 input output, respectively, inverting amplifier that configured on-chip oscillator, shown Figure Either quartz crystal ceramic resonator used. drive device from external clock source, XTAL2 should left unconnected while XTAL1 driven, shown Figure There requirements duty cycle external clock signal, since input internal clocking circuitry through divide-by-two flip-flop, minimum maximum voltage high time specifications must observed. restored normal operating level must held active long enough allow oscillator restart stabilize. Figure Oscillator Connections
XTAL2
XTAL1
Idle Mode
idle mode, puts itself sleep while onchip peripherals remain active. mode invoked software. content on-chip special functions registers remain unchanged during this mode. idle mode terminated enabled interrupt hardware reset. Note that when idle mode terminated hardware reset, device normally resumes program execution from where left off, machine cycles before internal reset algorithm takes control. On-chip hardware inhibits access internal this event, access port pins inhibited. eliminate possibility unexpected write port when idle mode terminated reset, instruction following that invokes idle mode should write port external memory.
Note:
Crystals Ceramic Resonators
Figure External Clock Drive Configuration
XTAL2
Power Down Mode
power down mode, oscillator stopped, instruction that invokes power down last instruction executed. on-chip Special Function Registers retain their values until power down mode terminated. only exit from power down hardware reset. Reset redefines SFRs does change on-chip RAM. reset should activated before
EXTERNAL OSCILLATOR SIGNAL
XTAL1
Status External Pins During Idle Power Down Modes
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External PSEN PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
3-25
Program Memory Lock Bits
AT80F52 three lock bits that left unprogrammed programmed obtain additional features listed following table.
value holds that value until reset activated. latched value must agree with current logic level that order device function properly.
Programming/Verifying QuickFlash
AT80F52 only programmed Atmel. Customer codes should submitted duplicate floppy disk uploaded Atmel's bulletin board site. code should Intel format. desired states Lock Bits should specified. Once programmed, code memory Lock Bits cannot erased reprogrammed. Please consult factory Atmel's representatives details submitting custom codes. Program Verify: lock bits have been programmed, programmed code data read back address data lines verification. lock bits cannot verified directly. Verification lock bits achieved observing that their features enabled. Reading Signature Bytes: signature bytes read same procedure normal verification locations 030H, 031H, 032H, except that P3.6 P3.7 must pulled logic low. values returned follows. (030H) indicates manufactured Atmel (031H) indicates QuickFlash (032H) indicates AT80F52
Lock Protection Modes
Program Lock Bits Protection Type program lock features. MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched reset, further programming QuickFlash memory disabled. Same mode verify also disabled. Same mode external execution also disabled.
When lock programmed, logic level sampled latched during reset. device powered without reset, latch initializes random
QuickFlash Verification Modes
Mode Read Code Data Read Signature Byte
PSEN
P2.6
P2.7
P3.6
P3.7
3-26
AT80F52
AT80F52
Figure Verifying QuickFlash Memory
AT80F52
ADDR. OOOOH/1FFFH QUICK FLASH VERIFICATION MODES TABLE P2.0 P2.4 P2.6 P2.7 P3.6 P3.7 XTAL DATA (USE PULLUPS)
3-20
XTAL1
PSEN
QuickFlash Verification Characteristics
70°C,
Symbol 1/tCLCL tAVQV tELQV tEHQZ Parameter Oscillator Frequency Address Data Valid ENABLE Data Valid Data Float After ENABLE
48tCLCL 48tCLCL 48tCLCL
Units
QuickFlash Verification Waveforms
P1.0 P1.7 P2.0 P2.4 PORT VERIFICATION ADDRESS
tAVQV
DATA
LOGIC LOGIC
LOGIC LOGIC
P2.7 (ENABLE)
tELQV
tEHQZ
3-27
Absolute Maximum Ratings*
Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-1.0V +7.0V Maximum Operating Voltage. 6.6V Output Current. 15.0 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics
values shown this table valid -40°C 85°C 5.0V 20%, unless otherwise noted.
Symbol VIL1 VIH1 VOL1 Parameter Input Voltage Input Voltage (EA) Input High Voltage Input High Voltage Output Voltage
Condition (Except
-0.5 -0.5
VCC-0.1 VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45
Units
(Except XTAL1, RST) (XTAL1, RST) (Ports 1,2,3)
VCC+0.9
Output (Port ALE, PSEN)
Voltage(1)
Output High Voltage (Ports 1,2,3, ALE, PSEN)
0.75 0.75 -650
VOH1
Output High Voltage (Port External Mode)
-800 -300
RRST
Logical Input Current (Ports 1,2,3) Logical Transition Current (Ports 1,2,3) Input Leakage Current (Port Reset Pulldown Resistor Capacitance Power Supply Current
0.45V 0.45
Test Freq. MHz, 25°C Active Mode, Idle Mode,
Power Down Mode
Notes:
Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: Maximum 8-bit port: Port Ports Maximum total output pins: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. Minimum Power Down
3-28
AT80F52
AT80F52
Characteristics
Under operating conditions, load capacitance Port ALE, PSEN load capacitance other outputs
External Program Data Memory Characteristics
Symbol Parameter Oscillator 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Oscillator Frequency Pulse Width Address Valid Address Hold After Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN Address Valid Address Valid Instruction PSEN Address Float Pulse Width Pulse Width Valid Data Data Hold After Data Float After Valid Data Address Valid Data Address Data Valid Transition Data Valid High Data Hold After Address Float High High tCLCL-20 3tCLCL-50 4tCLCL-75 tCLCL-20 7tCLCL-120 tCLCL-20 tCLCL+25 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 tCLCL-8 5tCLCL-55 tCLCL-10 tCLCL-13 3tCLCL-20 3tCLCL-45 Variable Oscillator 2tCLCL-40 tCLCL-13 tCLCL-20 4tCLCL-65 Units
3-29
External Program Memory Read Cycle
tLHLL tAVLL PSEN tPLAZ tLLAX PORT
tLLPL
tLLIV tPLIV
tPLPH
tPXAV tPXIZ tPXIX
INSTR
tAVIV PORT
External Data Memory Read Cycle
tLHLL tWHLH PSEN tLLDV tLLWL tAVLL PORT tLLAX tRLAZ
DATA
tRLRH
tRLDV
tRHDZ tRHDX
FROM INSTR
FROM
tAVWL tAVDV PORT
P2.0 P2.7 FROM FROM
3-30
AT80F52
AT80F52
External Data Memory Write Cycle
tLHLL tWHLH PSEN tLLWL tAVLL PORT tLLAX tQVWX tWLWH
tQVWH
DATA
tWHQX
FROM INSTR
FROM
tAVWL PORT
P2.0 P2.7 FROM FROM
External Clock Drive Waveforms
tCHCX
0.5V 0.1V 0.45V
tCHCX tCLCH tCHCL
tCLCX tCLCL
External Clock Drive
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Time Rise Time Fall Time 41.6 Units
3-31
Serial Port Timing: Shift Register Mode Test Conditions
values this table valid 5.0V Load Capacitance
Symbol Parameter tXLXL tQVXH tXHQX tXHDX tXHDV Serial Port Clock Cycle Time Output Data Setup Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge Input Data Valid Variable Oscillator 12tCLCL 10tCLCL-133 2tCLCL-117 10tCLCL-133 Units
Shift Register Mode Timing Waveforms
INSTRUCTION CLOCK
tXLXL tQVXH
WRITE SBUF
tXHQX
VALID VALID VALID VALID VALID
OUTPUT DATA CLEAR INPUT DATA
tXHDV
VALID VALID
tXHDX
VALID
Testing Input/Output Waveforms(1)
0.5V 0.9V TEST POINTS 0.45V 0.1V
Float Waveforms(1)
LOAD+ LOAD LOAD 0.1V 0.1V
Timing Reference Points
0.1V
0.1V
Note:
Inputs during testing driven 0.5V logic 0.45V logic Timing measurements made min. logic max. logic
Note:
timing purposes, port longer floating when change from load voltage occurs. port begins float when change from loaded VOH/VOL level occurs.
3-32
AT80F52
AT80F52
Ordering Information
Speed (MHz) Power Supply Ordering Code AT80F52-12AC AT80F52-12JC AT80F52-12PC AT80F52-12AI AT80F52-12JI AT80F52-12PI AT80F52-16AC AT80F52-16JC AT80F52-16PC AT80F52-16AI AT80F52-16JI AT80F52-16PI AT80F52-20AC AT80F52-20JC AT80F52-20PC AT80F52-20AI AT80F52-20JI AT80F52-20PI Package 40P6 40P6 40P6 40P6 40P6 40P6 Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type 40P6 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
3-33

AT80F52 low-power, high-performance CMOS 8-bit microcomputer with byte

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