Compatible with MCS-51Products 128K Bytes In-System Reprogrammable Fla

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Compatible with MCS-51Products 128K Bytes In-System Reprogrammable Fla

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AT89S4D12
Compatible with MCS-51Products 128K Bytes In-System Reprogrammable Flash data memory Bytes
Downloadable Flash Program Memory Endurance: 1,000 Write/Erase Cycles Sector Data Retention: Years Sector Programming: Bytes/Sector Single 3.3V Supply On-Chip oscillator Two-Level Program Memory Lock 256-Bytes Internal Programmable Lines Serial Peripheral Interface (SPI) Channel Serial Program Downloading Dual Data Pointer Registers
Description
AT89S4D12 low-voltage, highly integrated CMOS 8-bit microcomputer with bytes downloadable Flash program memory 128K bytes in-system reprogrammable Flash data memory. device manufactured using Atmel's high density Flash memory technology compatible with industry-standard MCS-51instruction set. 128K bytes on-chip Flash data memory accessed byte blocks. location used select active block. MOVX instruction used read write data memory. Both program data memory arrays programmed external programmer. downloadable Flash changed page (128 bytes) time accessible through serial peripheral interface port. Holding RESET active forces into slave input mode allows program memory written-from read-to unless Lock been activated. functional operations 128K bytes Flash data memory equivalent those AT29LV010A Flash memory device.
8-Bit Microcontroller with 132K Bytes Flash Data Memory AT89S4D12
Configurations
SOIC View
TEST1 RESET SDI/P1.1 SDO/P1.0 TEST2 P1.2/DTR P1.3/SCK P1.4/DSR
PLCC View
P1.1/SDI RESET TEST1 P1.2/DTR P1.3/SCK
P1.0/SDO TEST2
P1.4/DSR
0921A-A-12/97
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Block Diagram
128K Flash
ADDR. REGISTER
FLASH
REGISTER
STACK POINTER
PROGRAM ADDRESS REGISTER
BUFFER TMP2 TMP1
INCREMENTER
PROGRAM COUNTER
TIMING CONTROL
INSTRUCTION REGISTER
DPTR
PORT LATCH
PORT
PROGRAM LOGIC
12MHz
PORT DRIVERS
P1.0 P1.4
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AT89S4D12
AT89S4D12
Description
Supply voltage. Ground. Port Port 5-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins, they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because internal pullups. addition, P1.0, P1.1, P1.3 configured data output, data input shift clock input pins, shown following table. Port P1.0 P1.1 P1.3 Alternate Functions (data output channel) (data input channel) (clock input channel)
Special Function Registers
on-chip memory area called Special Function Register (SFR) space shown Table Note that addresses occupied, unoccupied addresses implemented chip. Read accesses these addresses will general return random data, write accesses will have indeterminate effect. User software should write these unlisted locations, since they used future products invoke features. that case, reset inactive values bits will always Memory Control Register MCON register contains RDY/BSY flag most significant Flash address A16, 128K bytes on-chip Flash data memory. Registers Control status bits Serial Peripheral Interface contained registers SPCR (shown Table SPSR (shown Table data bits contained SPDR register. Writing data register during serial data transfer sets Write Collision bit, WCOL, SPSR register. SPDR double buffered writing values SPDR changed Reset. Dual Data Pointer Registers facilitate data transfer, banks 16-bit Data Pointer Registers provided: address locations 85H. MCON selects selects DP1. user should always initialize appropriate value before accessing respective Data Pointer register.
Reset input. high this machine cycles while oscillator running resets device. TEST1 TEST1 during downloading Flash program data memory. This left unconnected tied ground during normal operation. TEST2 Test input. This user available function left unconnected tied ground.
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Table AT89S4D12 Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 0000000 SPDR XXXXXXXX PCON 0XXX0000 XXX11111 MCON XXXXX010 SPSR 00000000 00000000 SPCR 000X01XX 00000000 00000000 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H
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AT89S4D12
AT89S4D12
Table MCON-Memory Control Register
MCON Address Reset Value XXXX X010B
RDY/BSY
Symbol
Function Data Pointer Register Select. selects first bank Data Pointer Register, DP0, selects second bank, DP1. DataFlash Ready/Busy Flag. This serves RDY/BSY flag Read-Only mode during DataFlash write. RDY/BSY means that DataFlash ready programmed. While programming operations being executed, RDY/BSY equals automatically reset when programming completed. Memory Block Select. selects lower bytes DataFlash memory block. selects upper bytes DataFlash block.
RDY/BSY
Table SPCR-SPI Control Register
SPCR Address Reset Value 000X 01XXB
SPIE
DORD
CPOL
CPHA
SPR1
SPR0
Symbol SPIE DORD CPOL CPHA SPR0 SPR1
Function Interrupt Enable. This bit, enables interrupts: SPIE enable interrupts. SPIE disables interrupts. Enable. enables channel connects SDO, pins P1.0, P1.1, P1.3. disables channel. Data Order. DORD selects first data transmission. DORD selects first data transmission. Clock Polarity. When CPOL high when idle. When CPOL master device when transmitting. Please refer figure Clock Phase Polarity Control. Clock Phase. CPHA together with CPOL controls clock data relationship between master slave. Please refer figure Clock Phase Polarity Control. Clock Rate Select. These bits control rate device configured master. SPR1 SPR0 have effect slave. relationship between oscillator frequency, FOSC., follows: SPR1 SPR0 FOSC. divided
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Table SPSR-SPI Status Register
SPCR Address Reset Value 000X 0000B
SPIF
WCOL
Symbol SPIF
Function Interrupt Flag. When serial transfer complete, SPIF interrupt generated SPIE SPIF cleared reading status register with SPIF WCOL bits set, then accessing data register. Write Collision Flag. WCOL data register written during data transfer. During data transfer, result reading SPDR register incorrect, writing effect. WCOL (and SPIF bit) cleared reading status register with SPIF WCOL set, then accessing data register.
WCOL
Table SPDR-SPI Data Register
SPDR Address Reset Value unchanged
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Data Memory-Flash
AT89S4D12 implements 128K bytes on-chip Flash data storage bytes RAM. upper bytes occupy parallel space Special Function Registers. That means upper bytes have same addresses space physically separate from space. When instruction accesses internal location above address 7FH, address mode used instruction specifies whether accesses upper 128-bytes space. Instructions that direct addressing access space. example, following direct addressing instruction accesses location 086H (which SPDR). 086H, #data Instructions that indirect addressing access upper bytes RAM. example, following indirect addressing instruction, where contains 086H, accesses data byte address 086H, rather than SPDR (whose address 086H). @R0, #data Note that stack operations examples indirect addressing, upper bytes data available stack space. MOVX instructions used access Flash data memory. Flash write cycles self-timed typically take 128-byte page. progress Flash write monitored reading RDY/BSY (read-only) MCON. RDY/BSY means programming still progress RDY/BSY means Flash write cycle completed another write cycle initiated.
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AT89S4D12
AT89S4D12
Serial Peripheral Interface
serial peripheral interface (SPI) allows high-speed synchronous data transfer between AT89S4D12 master. AT89S4D12 features include following: Full-Duplex, 3-Wire Synchronous Data Transfer Frequency (max.) First First Data Transfer Four Programmable Rates Transmission Interrupt Flag Write Collision Flag Protection interconnection between master slave with shown following figure. clock input. Writing data register master starts clock generator, data written shifts MOSI into slave CPU. After shifting byte, clock generator stops, setting transmission flag (SPIF). interrupt enable (SPIE) set, interrupt requested. There four combinations phase polarity with respect serial data, which determined control bits CPHA CPOL. data transfer formats shown Figure Figure
Figure Block Diagram
P1.0
OSCILLATOR
8/16-BIT SHIFT REGISTER
DIVIDER ÷4÷16÷64÷128
READ DATA BUFFER
CLOCK (MASTER)
CLOCK CLOCK LOGIC
CONTROL LOGIC
P1.1
SELECT
SPR1 SPR0
P1.3
CONTROL
WCOL SPIF
DORD CPHA CPOL SPR1 SPR0
SPIE
STATUS REGISTER
CONTROL REGISTER
INTERRUPT INTERNAL REQUEST DATA
DORD
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Figure Master Slave Interconnection
MASTER
MISO
SLAVE
8-BIT SHIFT REGISTER
MOSI
8-BIT SHIFT REGISTER
CLOCK GENERATOR
Figure Transfer Format with CPHA
defined normally character just received. Figure Transfer Format with CPHA
defined normally previously transmitted character.
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AT89S4D12
AT89S4D12
Oscillator Characteristics
on-chip oscillator provided with minimum frequency maximum frequency over recommended operating conditions. Each instruction cycle takes oscillator cycles.
Program Memory Lock Bits
AT89S4D12 lock bits that left unprogrammed programmed obtain additional features listed following table. self-timed lock programming operation typically takes Once programmed, lock bits only unprogrammed with Chip Erase operation.
Lock Protection Modes(1)(2)
Program Lock Bits Notes: Protection Type internal memory lock feature. Programming Flash memory disabled. Same mode verify also disabled.
Unprogrammed Programmed
Flash Programming Specification
Both 128K bytes Data bytes Code flash memory arrays programmed using serial while RESET TEST1 pins pulled 3.3V (±10%). Both memory arrays organized 128-byte sectors programming written sector-by-sector, similar Atmel AT29LV010A. serial interface consists pins (serial shift clock), (serial input) (serial output). After RESET TEST1 high, Programming Enable instruction needs executed once before programming operations occur. During device programming, TEST2 should connected Ground. auto-erase cycle built into self-timed Page Write operation there need first execute Chip Erase instruction. Chip Erase operation self-timed typically takes Chip Erase turns content every flash memory location both Code Data arrays into FFH. Code Data memory arrays have separate address spaces: 0000H 0FFFH Code memory 00000H 2FFFFH Data memory. maximum serial clock (SCK) frequency used during flash programming should less than KHz. High time should minimum time should minimum. been completed, true data valid output data bits, next write cycle begin. DATA Polling begin time after write instruction been executed.
Toggle
Toggle provides another method detect completion programming cycle. During page write chip erase operation, successive attempts read data from memory will result output toggling between `0'. Once program cycle completed, output data will stop toggling valid data will presented. Examining toggle begin time during program cycle.
Ready/Busy
third method monitor progress programming provided RDY/BSY output signal. P1.4/DSR pulled during programming indicate BUSY pulled High again when programming done indicate READY.
Page Write
Code Data memory arrays programmed sector basis. byte data changed, data entire 128-byte sector must serially loaded into device using appropriate serial interface instruction. data byte that loaded during programming sector will indeterminate. AT89S4D12 automatically does sector erase turn whole sector into prior loading data into sector. erase command required. self-timed Page Write cycle typically takes (tWC).
DATA Polling
AT89S4D12 features DATA Polling indicate page write cycle. During write cycle, attempted serial read last byte written will result complement written datum Once write cycle
(continued)
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Once bytes sector loaded into device, they simultaneously programmed during self-timed programming cycle (tWC). After first data byte been loaded into device, successive bytes need entered within 300-µs time intervals. Page Write instruction detected 300-µs after last write instruction, load period will internal programming cycle will start. Address bits specify sector address Code Data memory arrays, respectively. valid sector address must entered during each write instruction. Address bits specify byte
address within sector. bytes loaded order, sequential loading required. Once programming operation been initiated, duration typically read operation will effectively polling operation.
Program Verify
lock bits have been programmed, programmed Code Data byte read back serial output SDO. state lock bits only verified indirectly observing that lock features enabled.
Serial Programming Instruction
Format Instruction Programming Enable Chip Erase Byte 10101100 Byte 01010011 Byte 11111111 Byte 11111111 Operation Enable Serial Programming after goes high. Chip erase both 128K memory arrays. Read data Code memory address A11:A0. Write data Code memory address A11:A0. Read data Data memory address A16:A0. Write data Data memory address A16:A0. LB1, program lock bits. Read device I.D. address A6:A0.
10101100
10000000
xxxxxxxx
xxxxxxxx
Program Lock Bits
10101100
111000
xxxxxxxx
Page Write Data Memory
Read Data Memory
1010000
Page Write Code Memory
0100000x
Read Code Memory
0010000x
xxxx
DDDDDDDD
xxxx
DDDDDDDD
DDDDDDDD
1100000
DDDDDDDD
xxxxxxxx
Read Signature Notes:
0011000x
xxxxxxxx
DDDDDDDD
A16:A0 Memory byte address `DDDDDDDD' Data input data output SDO. Don't care.
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AT89S4D12
AT89S4D12
Flash Memory Serial Programming Circuit
3.3V INSTRUCTION INPUT DATA OUTPUT CLOCK RDY/BUSY SDI/P1.1 SDO/P1.0 SCK/P1.3 DSR/P1.4 TEST2 RESET TEST1
Reading Signature Bytes
signature bytes read executing Read Signature command locations 31H. values returned follows: (30H) indicates manufactured Atmel (31H) indicates AT89S4D12
Serial Downloading Waveforms
SERIAL CLOCK INPUT SCK/P1.3 SERIAL DATA INPUT SDI/P1.1 SERIAL DATA OUTPUT SDO/P1.0
INSTRUCTION BYTE BYTE BYTE BYTE
INSTRUCTION BYTE BYTE BYTE BYTE tBLC MAX.
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Absolute Maximum Ratings*
Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-1.0V +7.0V Maximum Operating Voltage. 6.0V Output Current. 15.0 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics
values shown this table valid -40°C 85°C 3.0V 3.6V, unless otherwise noted.
Symbol VIH1 Parameter Input Voltage Input High Voltage Input High Voltage Output Voltage(1) (Except RST) (RST) Output High Voltage RRST Notes: Logical Input Current Logical Transition Current Reset Pulldown Resistor Capacitance Power Supply Current Test Freq. MHz, 25°C Active Mode 0.45V 0.75 -650 Condition -0.5 Units
Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: Maximum port: exceeds test condition, exceeed related specification. Pins guaranteed sink current greater than listed test conditions. Minimum Power Down
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AT89S4D12
AT89S4D12
Ordering Information
Speed (MHz) Power Supply 3.3V Ordering Code AT89S4D12-12JC AT89S4D12-12RC AT89S4D12-12JI AT89S4D12-12RI Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 28-Lead, Plastic Gull Wing Small Outline (SOIC)
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Compatible with MCS-51Products 128K Bytes In-System Reprogrammable Fla

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