MC68HC05BS8 TECHNICAL DATA !MOTOROLA HC05 MC68HC05BS8 M
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TECHNICAL DATA
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GENERAL DESCRIPTION DESCRIPTION INPUT/OUTPUT PORTS MEMORY REGISTERS RESETS INTERRUPTS TIMERS PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CORE INSTRUCTION POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS
MC68HC705BS8
GENERAL DESCRIPTION DESCRIPTION INPUT/OUTPUT PORTS MEMORY REGISTERS RESETS INTERRUPTS TIMERS PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CORE INSTRUCTION POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BS8
MC68HC05BS8 MC68HC705BS8
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
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Conventions
Register mnemonics defined paragraphs describing them. overbar used designate active-low signal, RESET. Unless otherwise stated, blank cells register diagram indicate that either unused reserved; shaded cells indicate that described following paragraphs; used indicate undefined state reset).
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SECTION CORE INSTRUCTION SECTION POWER MODES SECTION OPERATING MODES SECTION ELECTRICAL SPECIFICATIONS SECTION MECHANICAL SPECIFICATIONS APPENDIX MC68HC705BS8 Comments: Have found errors? please comment:
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TABLE CONTENTS
Paragraph Number TITLE Page Number
GENERAL DESCRIPTION
Features.1-1
DESCRIPTION
Descriptions.2-1 Assignment.2-2
INPUT/OUTPUT PORTS
Input/Output Programming .3-1 Port C.3-2 RSPWM Counter Reset.3-2 PC0:5 Keyboard Interrupts .3-2 Software Supported M-Bus .3-3
MEMORY REGISTERS
4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 Registers .4-1 RAM.4-1 (MC68HC05BS8) .4-1 EPROM (MC68HC705BS8).4-1 EEPROM .4-2 EEPROM Control Register.4-2 EEPROM Options Register.4-3 Read Procedure.4-3 Erase Procedure .4-4 Programming Procedure .4-4
MC68HC05BS8
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TITLE
Page Number
RESETS INTERRUPTS
RESETS .5-1 5.1.1 Power-On Reset (POR) .5-1 5.1.2 RESET Pin.5-2 5.1.3 Voltage Reset (LVR) .5-2 5.1.4 Computer Operating Properly (COP) Reset .5-3 INTERRUPTS.5-3 5.2.1 Non-maskable Software Interrupt (SWI) .5-5 5.2.2 Maskable Hardware Interrupts.5-5 5.2.2.1 External Interrupt (IRQ).5-5 5.2.2.2 Sync Signal Processor Interrupt.5-7 5.2.2.3 M-Bus Interrupts.5-7 5.2.2.4 Timer Interrupts.5-8 5.2.2.5 Core Timer Interrupts .5-9 5.2.2.6 Keyboard Interrupt.5-10
TIMERS
PROGRAMMABLE TIMER.6-1 6.1.1 Counter .6-3 6.1.2 Output Compare Register.6-4 6.1.3 Input Capture Registers.6-4 6.1.4 Timer Control Register.6-5 6.1.5 Timer Status Register (TSR) .6-6 6.1.6 Programmable Timer Timing Diagrams .6-7 CORE TIMER .6-10 6.2.1 CTimer Counter Register.6-10 6.2.2 CTimer Control Status Register.6-10 6.2.3 Watchdog Reset.6-12
PULSE WIDTH MODULATION
General Purpose Pulse Width Modulator .7-1 7.1.1 General Purpose Pulse Width Modulator Register (GPWM) .7-2 Raster Positioning Pulse Width Modulator .7-2 7.2.1 Raster Positioning Pulse Width Modulator Register (RSPWM) .7-4
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MC68HC05BS8
Paragraph Number
TITLE
Page Number
M-BUS SERIAL INTERFACE
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 M-Bus Interface Features .8-1 M-Bus Protocol .8-2 START Signal.8-3 Slave Address Transmission .8-3 Data Transfer.8-4 Repeated START Signal .8-4 STOP Signal .8-4 Arbitration Procedure .8-4 Clock Synchronization .8-5 Handshaking .8-5 M-Bus Registers .8-6 M-Bus Address Register (MADR) .8-6 M-Bus Frequency Register (MFDR).8-6 M-Bus Control Register (MCR) .8-7 M-Bus Status Register (MSR).8-8 M-Bus Data Register (MDR) .8-9 Programming Considerations .8-11 Initialization .8-11 Generation START Signal First Byte Data Transfer.8-11 Software Responses after Transmission Reception Byte .8-11 Generation STOP Signal.8-12 Generation Repeated START Signal .8-13 Slave Mode .8-13 Arbitration Lost .8-13 Software Supported M-Bus Interface.8-14
SYNC SIGNAL PROCESSOR
9.2.1 9.2.2 9.10 9.10.1 Introduction .9-1 Polarity Correction .9-2 Separate Vertical Sync Input.9-2 Separate Horizontal Composite Sync Input.9-2 Sync Detection .9-3 Free-running Pseudo Sync Signal Generator.9-3 Sync Separation .9-4 Vertical Sync Pulse Reshaper .9-5 Sync Signal Counters .9-5 VSYNC Interrupt.9-6 Sampling Pulse Output .9-7 Registers .9-7 Sync Signal Control Status Register (SSCSR) .9-7
MC68HC05BS8
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TITLE
Page Number
9.10.2 Vertical Frequency Register (VFR) .9-9 9.10.3 Line Frequency Registers (LFRs) .9-9 9.10.4 Interrupt Line Count Register (ILCR) .9-10 9.10.5 Sampling Pulse Register (SPR).9-10 9.11 System Operation.9-10
CORE INSTRUCTION
10.1 Registers .10-1 10.1.1 Accumulator .10-1 10.1.2 Index register .10-2 10.1.3 Program counter (PC).10-2 10.1.4 Stack pointer (SP).10-2 10.1.5 Condition code register (CCR).10-2 10.2 Instruction .10-3 10.2.1 Register/memory Instructions .10-4 10.2.2 Branch instructions .10-4 10.2.3 manipulation instructions .10-4 10.2.4 Read/modify/write instructions.10-4 10.2.5 Control instructions .10-4 10.2.6 Tables.10-4 10.3 Addressing modes.10-11 10.3.1 Inherent.10-11 10.3.2 Immediate .10-11 10.3.3 Direct .10-11 10.3.4 Extended.10-12 10.3.5 Indexed, offset .10-12 10.3.6 Indexed, 8-bit offset .10-12 10.3.7 Indexed, 16-bit offset .10-12 10.3.8 Relative .10-13 10.3.9 set/clear .10-13 10.3.10 test branch.10-13
POWER MODES
11.1 11.2 11.3 11.4 STOP Mode.11-1 WAIT Mode.11-1 Data Retention Mode .11-3 Watchdog Timer Considerations.11-3
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MC68HC05BS8
Paragraph Number
TITLE
Page Number
OPERATING MODES
12.1 12.2 12.3 User Mode (Normal Operation) .12-2 Self-Check Mode .12-2 Bootstrap Mode .12-4
ELECTRICAL SPECIFICATIONS
13.1 13.2 13.3 13.4 13.5 13.6 13.7 Maximum Ratings .13-1 Thermal Characteristics.13-1 Electrical Characteristics .13-2 Control Timing .13-3 Pulse Width Modulator Timing .13-4 M-Bus Timing.13-5 Sync Signal Processor Timing .13-6
MECHANICAL SPECIFICATIONS
14.1 44-pin Package.14-2
MC68HC705BS8
A.3.1 A.3.2 A.4.1 A.4.2 A.6.1 Features. Memory Map. Modes Operation User Mode Bootstrap Mode. EPROM Programming Program Control Register (PCR) EPROM Programming Sequence Assignments Electrical Specifications. Maximum Ratings
MC68HC05BS8
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MC68HC05BS8
LIST FIGURES
Figure Number 10-1 10-2 11-1 12-1 12-2 12-3 TITLE Page Number
MC68HC05BS8/MC68HC705BS8 Block Diagram .1-2 Assignment 44-pin Package .2-2 Port Circuitry .3-2 Memory .4-5 Power-On Reset RESET Timing.5-2 Interrupt Stacking Order .5-4 External Interrupt Circuit Timing .5-6 Programmable Timer Block Diagram.6-2 Timer State Timing Diagram Reset .6-8 Timer State Timing Diagram Input Capture .6-8 Timer State Timing Diagram Output Compare .6-9 Timer State Diagram Timer Overflow .6-9 Core Timer Block Diagram .6-11 GPWM Timing Example .7-1 GPWM Output Configuration.7-2 RSPWM Timing Example .7-3 RSPWM Block Diagram.7-3 M-Bus Interface Block Diagram .8-2 M-Bus Transmission Signal Diagram .8-3 Clock Synchronization .8-5 Flowchart M-Bus Interrupt Routine.8-10 Software Supported M-Bus Interrupt.8-14 Sync Signal Polarity Correction .9-3 Sync Separator.9-4 VTTL Pulse Widths Different Input Signal Formats .9-5 Vertical Frequency Counter Timing .9-6 Example operation .9-11 Programming model .10-1 Stacking order .10-2 STOP WAIT Flowchart.11-2 Flowchart Mode Entering .12-1 Self-Check Mode Timing .12-2 MC68HC05BS8 Self-Test Circuit.12-3
MC68HC05BS8
MOTOROLA
Figure Number 13-1 13-2 14-1
TITLE
Page Number
Timing 13-4 M-Bus Timing 13-5 44-pin Package (Case 824A-01). 14-2 MC68HC705BS8 Memory Map.A-2 Assignments 44-pin package.A-5
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MC68HC05BS8
LIST TABLES
Table Number 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 12-1 12-2 13-1 13-2 13-3 13-4 13-5 TITLE Page Number
Functions .3-1 Erase Mode Select .4-2 Register Outline.4-6 Reset/Interrupt Vector Addresses .5-4 Reset Rates .6-12 M-Bus Prescaler .8-6 Vertical Frame Frequencies .9-9 instruction.10-5 Register/memory instructions.10-5 Branch instructions .10-6 manipulation instructions.10-6 Read/modify/write instructions .10-7 Control instructions.10-7 Instruction .10-8 M68HC05 opcode map.10-10 Mode Selection.12-2 Self-Check Report .12-4 Electrical Characteristics MC68HC05BS8 .13-2 Control Timing .13-3 M-Bus Interface Input Signal Timing.13-5 M-Bus Interface Output Signal Timing.13-5 Sync Signal Processor Timing.13-6 MC68HC705BS8 Operating Mode Entry Conditions.
MC68HC05BS8
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MC68HC05BS8
GENERAL DESCRIPTION
MC68HC05BS8 HCMOS microcontroller member MC68HC05 Family low-cost single-chip microcontrollers. particularly suitable multi-sync computer monitor controller. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, EEPROM, I/O, Timers, Watchdog, M-Bus Serial Interface System, PWM, Sync Signal Processor. MC68HC705BS8 EPROM version MC68HC05BS8. references MC68HC05BS8 apply equally MC68HC705BS8, unless otherwise stated. References specific MC68HC705BS8 italicized text, also, quick reference, they summarized Appendix
Features
Fully static chip design featuring industry standard 8-bit M68HC05 core Power saving Stop Wait modes bytes bytes stack) 10K-bytes MC68HC05BS8 10K-bytes EPROM MC68HC705BS8 bytes EEPROM bidirectional lines keyboard interrupts Core timer with watchdog reset M-Bus (I2C) Serial Interfaces (one full H/W, with hardware support) Single channel 6-bit general purpose Single channel 7-bit raster positioning 16-bit programmable timer with TCAP TCMP Sync signal processor
I2C-bus proprietary Philips interface
MC68HC05BS8
GENERAL DESCRIPTION
MOTOROLA
voltage reset (LVR) Available 44-pin package
USER ROM/EPROM BYTES PORT
SELF-CHECK/BOOTSTRAP BYTES
BYTES
PORT
ACCUMULATOR
M68HC05
INDEX REGISTER
KEYBOARD INTERRUPT PORT M-BUS INTERRUPT PC6/SCL2 PC7/SDA2
STACK POINTER
PROGRAM COUNTER
RESET RESET
CONDITION CODE REGISTER
WATCHDOG CORE TIMER
GENERAL PURPOSE
GPWM
RASTER POSITIONING 16-BIT TIMER
RCLK
OSC1 OSC2 TCAP TCMP
M-BUS INTERFACE CIRCUIT
EEPROM BYTES POWER CHARGE PUMP
SYNC SIGNAL PROCESSOR
HSYNC VSYNC CSYNC HTTL VTTL
Figure MC68HC05BS8/MC68HC705BS8 Block Diagram
MOTOROLA
GENERAL DESCRIPTION
MC68HC05BS8
DESCRIPTION
This section provides description functional pins MC68HC05BS8 microcontroller.
Descriptions
44-pin
NAME VDD,
DESCRIPTION Power supplied using these pins. positive power supply; ground. user mode this external hardware interrupt IRQ. choices interrupt triggering sensitivity available through Option register: negative-edge sensitive triggering, negative-level sensitive triggering. bootstrap mode MC68HC705BS8, this EPROM programming voltage input pin. active RESET input required start-up, used reset internal state provide orderly software start-up procedure.
IRQ/VPP
RESET
OSC1, OSC2
These pins provide connections on-chip oscillator. oscillator driven AT-crystal circuit ceramic resonator with maximum frequency 4.4MHz. OSC1 also driven external oscillator external crystal/resonator circuit used.
36pF
OSC1
OSC2
4.2MHz
36pF
Example showing crystal connections. These eight lines comprise port state software programmable. port lines configured input during power-on external reset.
PA0-PA7
33-26
MC68HC05BS8
DESCRIPTION
MOTOROLA
NAME
44-pin
DESCRIPTION These eight lines comprise port state software programmable. port lines configured input during power-on external reset. also used RSPWM counter reset input when input counter reset enable GPWM register (bit $0010). These eight lines comprise port state software programmable. port lines configured input during power-on external reset. PC0-PC5 become keyboard interrupt input pins when corresponding bits Keyboard Interrupt register ($001E). respectively, when used software supported M-Bus Interface. These hardware M-Bus interface data clock lines. This input controls input capture function 16-bit free-running timer. This output indicates when timer compare successful. This output General purpose PWM. These excursive outputs Raster Positioning This input clock drive RSPWM counter. These input pins video sync signals from host computer. This Composite sync signal input from host computer. This output sample signal from Sync Signal Processor. These output from HSYNC VSYNC inputs signals separated from CSYNC input.
PB0-PB7
25-18
PC0-PC7
17-10
SDA, TCAP TCMP GPWM RSA, RCLK HSYNC, VSYNC CSYNC HTTL, VTTL
Assignment
VTTL RCLK GPWM TCMP TCAP
HTTL CSYNC VSYNC HSYNC OSC2 OSC1 RESET
Figure Assignment 44-pin Package
MOTOROLA
DESCRIPTION
MC68HC05BS8
INPUT/OUTPUT PORTS
MC68HC05BS8 lines, arranged three 8-bit ports (Port Each line individually programmable either input output, under software control Data Direction registers. Port also shares with keyboard interrupt software supported M-Bus functions. avoid glitches output pins, data should written Port Data register before writing "1"s corresponding Data Direction register bits pins output mode.
Input/Output Programming
Bidirectional port lines programmed input output under software control. direction pins determined state corresponding port data direction register (DDR). Each port associated DDR. port configured output corresponding logic one. configured input corresponding cleared logic zero. power-on reset, DDRs cleared, configuring port pins inputs. data direction registers capable being written read MCU. During programmed output state, read data register actually reads value output data latch pin. operation standard port hardware shown schematically Figure 3-1. This summarized Table which shows effect reading from writing various circumstances.
Table Functions
Function input mode. Data written into output data latch. Data written into output data latch output pin. state read. output mode. output data latch read. Note: internal signal.
MC68HC05BS8
INPUT/OUTPUT PORTS
MOTOROLA
DATA DIRECTION REGISTER
INTERNAL MC68HC05 CONNECTIONS
LATCHED OUTPUT DATA
OUTPUT
INPUT REGISTER
INPUT
Figure Port Circuitry
Port
These standard M68HC05 bidirectional ports, each comprising data register data direction register. three 8-bit ports. Reset does affect state data registers, clears data direction registers, thereby returning port pins input mode. Writing sets corresponding port output mode.
RSPWM Counter Reset
addition normal function, software selectable input reset signal Raster Positioning Pulse Width Modulator counter. reset pulse requires active high signal.
PC0:5 Keyboard Interrupts
keyboard interrupt inputs available port pins PC5. Each enabled keyboard interrupt setting corresponding keyboard interrupt enable register (bits $001E). When set, corresponding port will configured input pin, regardless DDRC setting, internal pull-up resistor connected pin.
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05BS8
interrupt signal latched, should cleared writing KBIC register (bit $001E) interrupt service routine. This should cleared after debounced, otherwise unwanted keyboard interrupt signals generated. keyboard interrupt negative-edge sensitive only, interrupt service routine specified contents memory locations $3FF0 $3FF1.
Address Register $001E KBIC KBE5 KBE4 KBE3 KBE2 KBE1 State reset
KBE0 0000 0000
KBIC Keyboard Interrupt Clear (set) Clear keyboard interrupt latch.
KBE5:0 Keyboard Interrupt Enable (set) Enable keyboard interrupt corresponding bit. Disable keyboard interrupt corresponding bit.
(clear)
Software Supported M-Bus
used respectively when configured software supported M-Bus interface. This M-Bus interface operated software emulation, with hardware interrupt circuit connected PC7.
MC68HC05BS8
INPUT/OUTPUT PORTS
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INPUT/OUTPUT PORTS
MC68HC05BS8
MEMORY REGISTERS
MC68HC05BS8/MC68HC705BS8 16K-byte memory consisting registers, user ROM/EPROM, user RAM, EEPROM, self-check/bootstrap shown Figure 4-1.
Registers
I/O, control status registers MC68HC05BS8 located within first 64-byte block memory (address $0000 $003F).
user consists bytes memory, from $0040 $013F. This shared with byte stack area. stack begins $00FF counts down $00C0.
Note:
Using stack area data storage temporary work locations requires care prevent data from being overwritten stacking from interrupt subroutine call.
(MC68HC05BS8)
user consists 10K-bytes memory, from $1800 $3FDF.
EPROM (MC68HC705BS8)
user EPROM consists 10K-bytes memory, from $1800 $3FDF.
MC68HC05BS8
MEMORY REGISTERS
MOTOROLA
EEPROM
EEPROM consists bytes, from $0200 $03FF. charge pump built chip operation EEPROM. Programming erasing controlled writing EEPROM Control register address $0007.
4.5.1
EEPROM Control Register
Address EEPCR $0007 State reset
EEOSC EER1
EER0 EELAT EEPGM 0000 0000
EEOSC EEPROM Charge Pump Oscillator Enable (set) Internal oscillator turned clock EEPROM charge pump. requires time tRCON stabilize. (Min. 1µs). Internal oscillator turned off. EEPROM charge pump clocked internal clock.
(clear)
EER1, EER0 EEPROM Erase Mode Select Bits These bits select three erase modes. Refer Table below.
Table Erase Mode Select
EER1 EER0 ERASE MODE erase Byte erase Block erase (block block Bulk erase (block block
EEPROM memory space divided into byte blocks. Block located address $0200-$02FF, block located $0300-$03FF. Providing EELAT EEPGM bits "1", EER1 EER0 bits indicate whether access EEPROM erase programming purpose. Block protect function applies block EEPROM memory space. EELAT EEPROM Programming Latch Control (set) EEPROM address data configured programming (writes EEPROM cause address data latched). EEPROM programming mode cannot read when this set. EEPROM address data configured normal reads. EER1, EER0, EEPGM forced "0"s.
(clear)
MOTOROLA
MEMORY REGISTERS
MC68HC05BS8
EEPGM EEPROM Programming Power Enable (set) Programming power switched EEPROM array. EELAT1 then EEPGM cannot set. Programming power switched EEPROM array.
(clear)
4.5.2
EEPROM Options Register
Address EEOPR $0200 EEPRT State reset unaffected
EEPRT EEPROM Protect (set) Block ($300-$3FF) configured read/write. Block ($300-$3FF) configured read only.
(clear)
When this erased "1", writing block possible until next external power-on reset occurs. Voltage Reset (set) voltage reset function disabled. voltage reset function enabled.
(clear)
This does control EEPROM operation, enables/disables function. When enabled, will reset drops below VLVR. When this changed, value will have effect until next external power-on reset.
4.5.3
Read Procedure
read data from EEPROM, EELAT must cleared. EEPGM, EER1, EER0 bits will forced zero. EEPROM read were normal ROM. charge pump generator since EEPGM zero. read performed while ELAT set, data will read $FF.
MC68HC05BS8
MEMORY REGISTERS
MOTOROLA
4.5.4
Erase Procedure
There three types ERASE operation mode (see Table 4-1): byte erase, block erase, bulk erase. perform byte erase operation, EELAT=1, EER1=0, EER0=1, write data address erase, EEPGM time tEBYTE.
Note:
perform block erase operation, EELAT=1, EER1=1, EER0=0, write data address block, EEPGM time tEBLOCK. perform bulk erase operation, EELAT=1, EER1=1, EER0=0, write data address EEPROM map, EEPGM time tEBULK. Erase operation part block possible EEPRT programmed "0".
4.5.5
Programming Procedure
program content EEPROM, EELAT bits, write data desired address, EEPGM bit. After required programming delay tPROG, EELAT must cleared, which also resets EEPGM. During programming operation, access EEPROM will return $FF. program second byte, EELAT must cleared before set, programming will have effect.
MOTOROLA
MEMORY REGISTERS
MC68HC05BS8
$0000 Bytes $003F $0040 $00C0 $00FF
Stack Bytes
User Bytes $013F Used (192) $0200 EEPROM Bytes $03FF
Used (4.25K)
$1600 Self-Check/Bootstrap Program Bytes $17FF $1800
Port Data Register Port Data Register Port Data Register Used Port Data Direction Register Port Data Direction Register Port Data Direction Register EEPROM Register Core Timer Control Status Register Core Timer Register Sync Signal Control Status Register Vfreq Register Line Frequency High Register Line Frequency Register Interrupt Line Count Register Sampling Pulse Register General Purpose Pulse Width Modulator Register Raster Positioning Pulse Width Modulator Register Timer Control Register Timer Status Register Input Capture High Register Input Capture Register Output Compare High Register Output Compare Register Counter High Register Counter Register Alternate Counter High Register Alternate Counter Register EPROM Programming Control Register Option Register Keyboard Interrupt Register Used Used Used
User ROM/EPROM 10K-Bytes
$3FDF $3FE0 $3FEF $3FF0 $3FFF
Self-Check/Bootstrap Vectors Bytes User Vectors Bytes
$3FF0 $3FF2 $3FF4 $3FF6 $3FF8 $3FFA $3FFC $3FFE
KEYBOARD M-BUS CTIMER TIMER VSYNC RESET
Used M-Bus Address Register M-Bus Frequency Divider Register M-Bus Control Register M-Bus Status Register M-Bus Data Register Used Used EEPROM Options Register
$0200
Figure Memory
MC68HC05BS8
MEMORY REGISTERS
MOTOROLA
Table Register Outline
Register Name Port data Port data
Address $0000 $0001 $0002 $0003
State reset unaffected unaffected unaffected
Port data used Port data direction Port data direction Port data direction EEPROM control Core timer control status Core timer Sync signal control status Vfreq Line frequency high Line frequency Interrupt line counter Sampling pulse General Raster positioning Timer control Timer status Input capture high Input capture Output compare high Output compare Counter high Counter Alternate counter high Alternate counter
$0004 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 $0005 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0000 0000 $0006 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0000 0000 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B CTOF EEOSC EER1 RTIF CTOFE RTIE EER0 EELAT EEPGM 0000 0000 SIN1 SIN0 0000 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0010
VPOL HPOL VDET HDET SOUT INSRT VSIE LF11 LF10
GPW5 GPW4 GPW3 GPW2 GPW1 GPW0 0000 0000
RSPW6 RSPW5 RSPW4 RSPW3 RSPW2 RSPW1 RSPW0 0000 0000 ICIE IC15 OC15 TC15 AC15 OCIE IC14 OC14 TC14 AC14 TOIE IC13 OC13 TC13 AC13 IC12 OC12 TC12 AC12 IC11 OC11 TC11 AC11 IC10 OC10 TC10 AC10 IEDG OLVL 0000 00u1 uuu0 0000 unaffected unaffected
unaffected unaffected
EPROM programming control
Option Keyboard interrupt used
$001C
$001D $001E $001F INTO KBIC
Reserved
ELAT
0000 0000
0100 0000
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0 0000 0000
MOTOROLA
MEMORY REGISTERS
MC68HC05BS8
Table Register Outline
Register Name
Address $0020 $0038 $0039 $003A $003B $003C $003D $003E $003F
State reset
used M-Bus address M-Bus frequency divider M-Bus control M-Bus status M-Bus data used used
MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 MIEN MASS MSTA TXAK SIFC SIIC
0000 0000000 0000 0000 0000
RXAK 1000 0001 undefined
EEPROM options
$0200
EEPRT
unaffected
MC68HC05BS8
MEMORY REGISTERS
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MEMORY REGISTERS
MC68HC05BS8
RESETS INTERRUPTS
section describes reset interrupt functions available MC68HC05BS8.
RESETS
MC68HC05BS8 reset four ways: initial power-on reset function, (POR) active input RESET pin, (RESET) watchdog timer reset, (COPR) Voltage Reset, (LVR)
these resets will cause program starting address, specified contents memory locations $3FFE $3FFF, cause interrupt mask (I-bit) Condition Code register set.
5.1.1
Power-On Reset (POR)
power-on reset occurs when positive transition detected supply voltage, VDD. power-on reset used strictly power-up conditions, should used detect drops power supply voltage. There provision power-down reset. power-on circuitry provides 4064 tCYC delay from time that oscillator becomes active. external RESET 4064 tCYC time out, processor remains reset condition until RESET goes high. user must ensure that risen point where operate properly prior time 4064 cycles have elapsed. there doubt, external RESET should remain until such time that risen minimum operating voltage specified.
MC68HC05BS8
RESETS INTERRUPTS
MOTOROLA
5.1.2
RESET
RESET input used reset provide orderly software start-up procedure. When using external reset, RESET must stay minimum 1.5tCYC. RESET contains internal Schmitt Trigger part input improve noise immunity.
tVDDR THRESHOLD (TYPICALLY 1-2V)
OSC2 PIN1 tOXOV tCYC INTERNAL CLOCK2 4064 tCYC
INTERNAL ADDRESS BUS2
3FFE
3FFF
3FFE
3FFE
3FFF
INTERNAL DATA BUS2
CODE =1.5tCYC
CODE
RESET NOTES: OSC2 meant represent frequency. only used represent time. Internal clock, internal address bus, internal data signals available externally. Next rising edge internal clock after rising edge RESET initiates reset sequence.
Figure Power-On Reset RESET Timing
5.1.3
Voltage Reset (LVR)
When function enabled, internal reset generated drops below VLVR. (See Section value VLVR.) This reset function enabled/disabled programming erasing EEPROM Options register ($0200). Refer Section 4.5.2.
MOTOROLA
RESETS INTERRUPTS
MC68HC05BS8
5.1.4
Computer Operating Properly (COP) Reset
MC68HC05BS8 contains watchdog timer that automatically times this timer reset (cleared) within specific amount time program reset sequence.
Note:
time-out prevented periodically writing address $3FF0.
watchdog timer allowed time-out, internal reset generated reset MCU. Because internal reset signal used, comes reset same operating mode when time-out generated. reset function enabled after reset, disabled writing Option register address $001D. Once disabled, cannot enabled except reset function. Section 6.2.3 more information watchdog timer.
INTERRUPTS
MC68HC05BS8 interrupted different sources maskable hardware interrupt non-maskable software interrupt: Software Interrupt Instruction (SWI) External signal Sync Signal Processor (SSP) Programmable Timer (TIMER) Core Timer (CTIMER) M-Bus Interface (MBUS) Keyboard (KBI)
interrupt mask (I-bit) set, maskable interrupts (internal external) disabled. Clearing I-bit enables interrupts. Interrupts cause processor save register contents stack interrupt mask (I-bit) prevent additional interrupts. instruction causes register contents recovered from stack normal processing resume. Unlike reset, hardware interrupts cause current instruction execution halted, considered pending until current instruction complete. current instruction already fetched being operated When current instruction complete, processor checks pending hardware interrupts. interrupts masked (CCR I-bit clear) processor proceeds with interrupt processing; otherwise, next instruction fetched executed. Table shows relative priority possible interrupt sources.
MC68HC05BS8
RESETS INTERRUPTS
MOTOROLA
$00C0 (BOTTOM STACK) $00C1 UNSTACKING ORDER $00C2 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE) STACKING ORDER $00FD $00FE $00FF (TOP STACK)
Figure Interrupt Stacking Order
Table Reset/Interrupt Vector Addresses
Register SSCR Flag Name CTOF RTIF Interrupt Reset Software External Interrupt VSYNC Timer Overflow Output Compare Input Capture Core Timer Overflow Core Timer Interrupt M-Bus Keyboard Interrupt RESET TIMER Vector Address $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9 $3FF6-$3FF7 Priority highest
CTCSR
CTIMER MBUS
$3FF4-$3FF5 $3FF2-$3FF3 $3FF0-$3FF1 lowest
MOTOROLA
RESETS INTERRUPTS
MC68HC05BS8
5.2.1
Non-maskable Software Interrupt (SWI)
software interrupt (SWI) executable instruction non-maskable interrupt: execute regardless state I-bit CCR. I-bit zero (interrupt enabled), executed after interrupts that were pending when fetched, before interrupts generated after fetched. interrupt service routine address specified contents memory locations $3FFC $3FFD.
5.2.2
Maskable Hardware Interrupts
interrupt mask (I-bit) set, maskable interrupts (internal external) masked. Clearing I-bit allows interrupt processing occur.
Note:
internal interrupt latch cleared first part interrupt service routine; therefore, external interrupt pulse could latched serviced soon I-bit cleared.
5.2.2.1
External Interrupt (IRQ)
external interrupt software configured "negative-edge" "negative-level" sensitive triggering INTO Option register.
Address Option register $001D INTO State reset
INTO (set) Negative-edge sensitive triggering IRQ. Negative-level sensitive triggering IRQ.
(clear)
When signal external interrupt pin, IRQ, satisfies condition selected, external interrupt occurs. actual processor interrupt generated only interrupt mask condition code register also cleared. When interrupt recognized, current state processor pushed onto stack interrupt mask condition code register set. This masks further interrupts until present serviced. service routine address specified contents $3FFA $3FFB. interrupt logic recognizes negative edge transitions pulses (special case negative edges) external interrupt line. Figure shows both block diagram timing interrupt line (IRQ) processor. first method used pulses interrupt line spaced enough apart serviced. minimum time between pulses equal number cycles required execute interrupt service routine plus cycles. Once pulse occurs,
MC68HC05BS8
RESETS INTERRUPTS
MOTOROLA
INTO External Interrupt Request
I-BIT (CCR)
Power-On Reset
External Reset External Interrupt being serviced (read vectors)
Interrupt Function Diagram
EDGE SENSITIVE TRIGGER CONDITION tILIH tILIL minimum pulse width tILIH internal period. period tILIL should less than number tCYC cycles takes execute interrupt service routine plus tcyc cycles.
tILIL
LEVEL SENSITIVE TRIGGER CONDITION after servicing interrupt remains low, then next interrupt recognized. Normally used with pull-up resistors wired-OR connection.
Wired ORed Interrupt signals
Interrupt Mode Diagram
Figure External Interrupt Circuit Timing
MOTOROLA
RESETS INTERRUPTS
MC68HC05BS8
next pulse should occur until software exited routine occurs). second configuration shows several interrupt lines wired-OR perform interrupt processor. Thus, interrupt lines remain after servicing interrupt, next interrupt recognized.
Note:
internal interrupt latch cleared first part service routine; therefore, (and only one) external interrupt pulse could latched during tILIL serviced soon I-bit cleared.
5.2.2.2
Sync Signal Processor Interrupt
will process Sync Signal Processor VSYNC interrupt following conditions satisfied: I-bit cleared, VSIE Interrupt Line Count register (ILCR) set, value horizontal line counter matches value ILCR. This interrupt will vector interrupt service routine located address specified contents $3FF8 $3FF9. VSYNC interrupt latch will cleared automatically fetching these vectors. Refer Section detailed description Sync Signal Processor.
5.2.2.3
M-Bus Interrupts
hardware M-Bus interrupt enabled when M-Bus Interrupt Enable (MIEN) M-Bus Control register set, provided interrupt mask Condition Code register cleared. interrupt service routine address specified contents memory location $3FF2 $3FF3.
Address M-Bus Status Register $001A MAAS State reset
RXAK 1000 0001
M-Bus Interrupt (set) M-Bus interrupt occurred. M-Bus interrupt occurred.
(clear)
When this set, interrupt generated MIEN set. This when following events occurs: Completion byte data transfer. falling edge clock set.
MC68HC05BS8
RESETS INTERRUPTS
MOTOROLA
match calling address with specific address slave mode MAAS set. loss arbitration set. This must cleared software interrupt routine. Data Transfer Complete (set) byte transfer been completed. byte being transfer.
(clear)
MAAS Addressed Slave
(set)
Currently addressed slave. currently addressed.
(clear)
Then needs check accordingly. Writing M-Bus Control register clears this bit. Arbitration Lost (set) Lost arbitration master mode. arbitration lost.
(clear)
Software M-Bus Interrupt (set) Signals pins satisfy "start" condition "soft" M-Bus protocol. This cannot SIIC cleared. interrupt generated only I-bit also cleared. "soft" M-Bus interrupt.
(clear)
Refer Section detailed description M-Bus Interface.
5.2.2.4
Timer Interrupts
There three interrupt sources from 16-bit free-running counter timer.
Address Timer Status Register $0013 State reset uuu0 0000
MOTOROLA
RESETS INTERRUPTS
MC68HC05BS8
Input Capture Flag This when proper edge been sensed input capture edge detector. cleared reading (with set) followed accessing Input Capture register ($0015). Output Compare Flag This when Output Compare register matches Counter register. cleared reading (with set) then accessing Output Compare register ($0017). Timer Overflow Flag This during counter transition from $FFFF $0000. cleared reading (with set) followed reading counter ($0019). three timer interrupt flags have corresponding enable bits (ICIE, OCIE, TOIE) found Timer Control register (TCR) location $12. Reset clears enable bits preventing interrupt from occurring. actual processor interrupt generated only interrupt mask condition code register also cleared. When interrupt recognized, current state machine pushed onto stack interrupt mask condition code register set. This masks further interrupts until present serviced. service routine address specified contents $FFF6 $FFF7. Refer section detailed description 16-bit Counter Timer.
5.2.2.5
Core Timer Interrupts
There interrupt sources, RTIF bits Multi-Function Timer Control Status Register. interrupt service routine address specified contents memory location $3FF4 $3FF5.
Address CTimer Control Status Register $0008 CTOF State reset 0000 0011
RTIF CTOFE RTIE
CTOF Timer Overflow (set) CTimer counter overflow occurred. CTimer counter overflow occurred.
(clear)
This when 8-bit ripple counter overflows from $00; timer overflow interrupt will occur, CTOFE set. CTOF cleared writing bit.
MC68HC05BS8
RESETS INTERRUPTS
MOTOROLA
RTIF Real Time Interrupt Flag (set) real time interrupt occurred. real time interrupt occurred.
(clear)
Refer Section detailed description CTimer.
5.2.2.6
Keyboard Interrupt
Keyboard interrupt functions available PC0-PC5. Each port individually configured keyboard interrupt function register $0010. Once configured, interrupt recognized high transition (negative edge) sensed I-bit also cleared. interrupt service routine specified contents memory locations $3FF0 $3FF1.
MOTOROLA 5-10
RESETS INTERRUPTS
MC68HC05BS8
TIMERS
PROGRAMMABLE TIMER
timer consists 16-bit free-running counter driven fixed divide-by-four prescaler. This timer used many purposes, including input waveform measurements while simultaneously generating output waveform. Pulse widths vary from several microseconds many seconds. Figure shows block diagram Programmable Timer. Because timer 16-bit architecture, registers input capture output compare functions pairs 8-bit registers (high byte byte). Generally, assessing byte specific timer function allows full control that function. However, access high byte inhibits that specific timer function until byte also accessed.
Note:
I-bit condition code register should while manipulating both high byte register specific timer function ensure that interrupt does occur.
8-bit registers associated with programmable timer. Timer Control Register (TCR) Timer Status Register (TSR) Input Capture Register Output Compare Register Counter Register Alternate Counter Register High byte $14, byte High byte $16, byte High byte $18, byte High byte $1A, byte
description each register provided following paragraphs.
MC68HC05BS8
TIMERS
MOTOROLA
MC68HC05BS8 INTERNAL
BUFFER
INTERNAL PROCESSOR CLOCK
OUTPUT COMPARE REGISTER
FREE RUNNING COUNTER ALTERNATE COUNTER REGISTER
INPUT CAPTURE REGISTER
OUTPUT COMPARE CIRCUIT
EDGE INPUT
OVERFLOW DETECT CIRCUIT
EDGE DETECT REGISTER
TCAP
OUTPUT LEVEL
TIMER STATUS REG. ($13) TIMER CONTROL REG. ($12)
IEDG OLVL
RESET
TCMP
OUTPUT LEVEL REGISTER
ICIE
OCIE
TOIE
INTERRUPT CIRCUIT
Figure Programmable Timer Block Diagram
MOTOROLA
TIMERS
MC68HC05BS8
6.1.1
Counter
Counter Register location Alternate Counter Register High byte $18, byte High byte $1A, byte
element programmable timer 16-bit, free-running counter counter register, preceded prescaler that divides internal processor clock four. prescaler gives timer resolution 0.95µs internal clock 4.2MHz. counter incremented during portion internal clock. Software read counter time without affecting value. double-byte, free-running counter read from either locations, (counter register) (counter alternate register). Reading only least significant byte (LSB) free-running counter ($19 $1B) receives count value time read. most significant byte (MSB) ($18 $1A) read first, ($19 $1B) transferred buffer. This buffer value remains fixed after first read, even read several times. This buffer accessed when ($19 $1B) read, thus, completes read sequence complete counter value. Reading Timer Counter register byte after reading timer Status Register clears timer overflow flag (TOF), reading Counter Alternate register does affect TOF. Therefore, counter alternate register read time without risk missing timer overflow interrupts cleared TOF. free-running counter preset $FFFC during reset always read-only register. During power-on reset, counter also preset $FFFC begins running after oscillator start-up delay. value free-running counter repeats every 262144 internal clock cycles. when counter overflows (from $FFFF $0000); this will cause interrupt TOIE (bit TCR) set. some timing control applications desirable reset counter under software control. When byte counter ($19 $1B) written counter reset value $FFFC. divide-by-4 prescaler also reset counter resumes normal counting operation. flags enable bits remain unaltered this operation. access previously been made high byte free-running counter ($18 $1A), then reset counter operation terminates access sequence.
MC68HC05BS8
TIMERS
MOTOROLA
6.1.2
Output Compare Register
Address OCMPH OCMPL $0016 $0017 OC15 OC14 OC13 OC12 OC11 OC10 State reset
unaffected unaffected
16-bit Output Compare register used several purposes, such indicating when period time elapsed. bits readable writable affected timer hardware reset. compare function needed, Output Compare register used storage locations. contents Output Compare register continually compared with contents free-running counter and, match found, output compare flag (OCF) Timer Status register set. Output Compare register' value should changed after each successful comparison establish elapsed time-out. interrupt also accompany successful output compare provided interrupt enable (OCIE) set. (The free-running counter updated every four internal clock cycles.) After processor write cycle Output Compare register containing ($16), output compare function inhibited until ($17) also written. user must write both bytes (locations) written first. write made only ($17) will inhibit compare function. processor write either byte Output Compare register without affecting other byte. minimum time required update Output Compare register function program rather than internal hardware. Because output compare flag Output Compare register defined power affected reset, care must taken when initializing output compare functions with software. following procedure recommended: write Output Compare register High-byte inhibit further compares; read Timer Status register initialize clearing OCF; write Output Compare register Low-byte enable output compare function.
6.1.3
Input Capture Registers
Address ICAPH ICAPL $0014 $0015 IC15 IC14 IC13 IC12 IC11 IC10 State reset unaffected unaffected
`Input Capture' technique whereby external signal (connected TCAP pin) used trigger read free-running counter. this possible relate timing external signal internal counter value, hence elapsed time.
MOTOROLA
TIMERS
MC68HC05BS8
8-bit registers that make 16-bit input capture register, read-only, used latch value free-running counter after corresponding input capture edge detector senses valid transition. level transition that triggers counter transfer defined corresponding input edge (IEDG). Reset does affect contents input capture register. result obtained from input capture will greater than value free-running counter rising edge internal clock preceding external transition. This delay required internal synchronization. Resolution count free-running counter, which four internal clock cycles. free-running counter contents transferred input capture register each valid signal transition whether input capture flag (ICF) clear. input capture register always contains free-running counter value that corresponds most recent input capture.After read input capture register ($14), counter transfer inhibited until ($15) also read. This characteristic causes time used input capture software routine interaction with main program determine minimum pulse period. read input capture register ($15) does inhibit free-running counter transfer since they occur opposite edges internal clock.
6.1.4
Timer Control Register
Address $0012 ICIE OCIE TOIE IEDG State reset
OLVL 0000 00u1
read/write register containing five control bits. Four bits control interrupts associated with each four flag bits found Timer Status register. other controls which edge significant input capture edge detector. Timer Control register free-running counter only sections timer affected reset. Definition each follows: ICIE Input Capture Interrupt Enable (set) Input Capture interrupt enabled. Input Capture interrupt disabled.
(clear)
OCIE Output Compare Interrupt Enable (set) Output Compare interrupt enabled. Output Compare interrupt disabled.
(clear)
MC68HC05BS8
TIMERS
MOTOROLA
TOIE Timer Overflow Interrupt Enable (set) Timer Overflow interrupt enabled. Timer Overflow interrupt disabled.
(clear) IEDG Input Edge (set)
TCAP positive-going edge sensitive. TCAP negative-going edge sensitive.
(clear)
When IEDG set, positive-going edge TCAP will trigger transfer free-running counter value input capture registers. When clear, negative-going edge triggers transfer. OLVL Output Level Voltage Latch
(set)
High output TCMP counter compare true. output TCMP counter compare true.
(clear)
When OLVL high output level will clocked into output level register next successful output compare TCMP pin.
6.1.5
Timer Status Register (TSR)
Address $0013 State reset uuu0 0000
Timer Status register contains status bits above three interrupt conditions ICF, OCF, TOF. Accessing timer status register satisfies first condition required clear status bits. remaining step access register corresponding status bit. Input Capture Flag (set) valid input capture occurred. input capture occurred.
(clear)
This when selected polarity edge detected input capture edge detector; input capture interrupt will generated, ICIE set, cleared reading then Input Capture register ($15)
MOTOROLA
TIMERS
MC68HC05BS8
Output Compare Flag (set) valid output compare occurred Output Compare register. output compare occurred Output Compare register.
(clear)
will when Output Compare register contents match that free-running counter; output compare interrupt will generated, OCIE set. cleared reading then Output Compare register ($17). Timer Overflow Flag (set) Timer Overflow occurred. timer overflow occurred.
(clear)
This when free-running counter overflows from $FFFF $0000; timer overflow interrupt will occur, TOIE (bit Timer Control register $12) set. cleared reading counter register ($19). When using timer overflow function reading free-running counter random times measure elapsed time, problem occur whereby timer overflow flag unintentionally cleared timer status register read written when set, free-running counter read, purpose servicing flag. Reading alternate counter register instead counter register will avoid this potential problem.
6.1.6
Programmable Timer Timing Diagrams
relationships between internal clock signals, counter contents status flag bits shown following diagrams. should noted that signals labelled `internal' (processor clock, timer clocks Reset) available user.
MC68HC05BS8
TIMERS
MOTOROLA
INTERNAL PROCESSOR CLOCK INTERNAL RESET
INTERNAL TIMER CLOCKS
COUNTER BIT)
$FFFC
$FFFD
$FFFE
$FFFF
RESET
(external POR)
Notes: RESET affects only Counter register Timer Control register.
Figure Timer State Timing Diagram Reset
INTERNAL PROCESSOR CLOCK
INTERNAL TIMER CLOCKS
COUNTER BIT)
$F123
$F124
$F125
$F126
$F127
INPUT EDGE
(SEE NOTE)
INTERNAL CAPTURE LATCH INPUT CAPTURE REGISTER
$????
$F125
INPUT CAPTURE FLAG Note: input edge occurs shaded area from timer state other timer state input capture flag during next state T11.
Figure Timer State Timing Diagram Input Capture
MOTOROLA
TIMERS
MC68HC05BS8
INTERNAL PROCESSOR CLOCK
INTERNAL TIMER CLOCKS
COUNTER BIT)
$F455
$F456
Note
$F457
$F458
$F459
OUTPUT COMPARE REGISTER
writes $F457
Note
$F457
COMPARE REGISTER LATCH
Note
OUTPUT COMPARE Flag TCMP
Note:
write compare registers take place time, compare only occurs timer state T01. Thus 4-cycle difference exist between write compare register actual compare. output compare flag timer state that follows comparison match ($F547 this example).
Figure Timer State Timing Diagram Output Compare
INTERNAL PROCESSOR CLOCK
INTERNAL TIMER CLOCKS
COUNTER BIT)
$FFFE
$FFFF
$0000
$0001
$0002
TIMER OVERFLOW FLAG (TOF)
Note: timer state (transition counter from $FFFF $0000). cleared read timer status register during internal processor clock high time followed read counter register.
Figure Timer State Diagram Timer Overflow
MC68HC05BS8
TIMERS
MOTOROLA
CORE TIMER
Core Timer 15-stage multi-functional ripple counter which provides miscellaneous function MC68HC05BS8 MCU. includes timer overflow function, real-time interrupt, watchdog. seen Figure 6-6, Timer driven internal clock divided four with fixed prescaler. This signal drives 8-bit ripple counter. value this 8-bit ripple counter read time accessing Ctimer Counter register (CTCR) address $09. timer overflow function implemented last stage this counter, giving possible interrupt rate E/1024. Four additional stages produces resulting clock E/16384, driving Real Time Interrupt circuit. circuit consists three divider stages with selector. output circuit further divided eight drive optional Watchdog Timer circuit. rate selector bits, CTOF enable bits flags located CTimer Control Status register (CTCSR) location $08.
6.2.1
CTimer Counter Register
Address CTCR $0009 State reset 0000 0000
Core Timer Counter register read-only register which contains current value 8-bit ripple counter. This counter clocked fOP/4 used various functions including software capture. Extended time periods attained using function increment temporary storage location thereby simulating 16-bit more) counter. During Power-on reset (POR) cycle, CTimer counters first cleared, counters then count 4064 cycles before cleared again. After this 4064 cycles, circuit releases device from reset. this point, RESET asserted, timer will start counting from zero normal device operation will begin. RESET asserted anytime during operation (other than POR), counter chain will cleared.
6.2.2
CTimer Control Status Register
Address CTCSR $0008 CTOF State reset 0000 0011
RTIF CTOFE RTIE
CTOF CTimer Overflow (set) 8-bit ripple timer overflow occurred. 8-bit ripple timer overflow occurred.
(clear)
MOTOROLA 6-10
TIMERS
MC68HC05BS8
Internal Internal Processor Clock CTCR ($0009) Core Timer Counter Register
fop/2
fop/210
7-bit Counter
Select Circuit Overflow Detect Circuit
CTCSR ($0008) CTimer Control Status Reg.
CTOF RTIF CTOFE RTIE
Watchdog Resetable Timer (÷8) Interrupt Circuit
Interrupt Logic
Reset Logic
Figure Core Timer Block Diagram
This when 8-bit ripple counter overflows from $00; timer overflow interrupt will occur, TOFE (bit set. cleared writing bit.
MC68HC05BS8
TIMERS
MOTOROLA 6-11
RTIF Real Time Interrupt Flag (set) real time interrupt occurred. real time interrupt occurred.
(clear)
When RTIF set, interrupt request generated RTIE set. clock frequency that drives circuit E/1213. rate selectable bits. RTIF cleared writing bit. CTOFE CTimer Overflow Interrupt Enable (set) interrupt enabled. interrupt disabled.
(clear)
RTIE Real Time Interrupt Enable
(set)
Real time interrupt enabled. Real time interrupt disabled.
(clear)
RT1, Rate Select watchdog Section 6.2.3 watchdog reset.
6.2.3
Watchdog Reset
(Computer Operating Properly) watchdog timer function implemented using output selected output. minimum reset rates determined CTimer Control Status register. circuit times out, internal reset generated reset vector fetched $3FFE $3FFF). Preventing time-out achieved periodically writing address $3FF0. reset function enabled after reset, disabled writing (bit Option Register address $001D. Once disabled, cannot enabled except reset function. Also, STOP mode cannot entered when watchdog enabled.
Table Reset Rates
Frequency, =2.1MHz Minimum Reset Rate (RTI Divide Ratio Minimum Rate 1/(fOP/Divide Ratio/7) 7.81ms 54.7ms 15.6ms 109ms 31.2ms 219ms 62.5ms 438ms should only changed immediately after watchdog timer been reset.
MOTOROLA 6-12
TIMERS
MC68HC05BS8
PULSE WIDTH MODULATION
MC68HC05BS8 independent PWMs; general purpose (GPWM) raster positioning (RSPWM). They controlled registers located $0010 $0011.
General Purpose Pulse Width Modulator
GPWM consists comparator 6-bit free-running counter driven internal clock. counter runs from rolls over back $00. Whenever GPWM value GPWM register greater than running counter, output GPWM will "high" (See Figure 7-1).
GPWM
GPWM data 01000 Internal clock 2MHz 23.5µs Frame rate=32KHz 31.5µs
Figure GPWM Timing Example
reduce occurrence fast logic switching edges PCB, GPWM output connected output chip resistor nominal value this way, with controls filter capacitor connected externally directly output. further advantage that logic signal only overcome modest on-chip capacitances thus supply current spikes significantly reduced. GPWM output configured open drain output setting GPWM register. should noted that diode associated with P-channel device still connected output therefore normal voltage limitations apply, i.e. VDD. Figure shows schematic GPWM output.
MC68HC05BS8
PULSE WIDTH MODULATION
MOTOROLA
GPWMR
GPWM
GPWM logic
Protection
Figure GPWM Output Configuration
7.1.1
General Purpose Pulse Width Modulator Register (GPWM)
Address GPWMR $0010 State reset
GPW5 GPW4 GPW3 GPW2 GPW1 GPW0 0000 0000
Open Drain Enable (set) GPWM output configured open drain output. GPWM output configured direct drive output.
(clear)
GPW5:0 Data These bits contain pulse width modulator data GPWM.
Raster Positioning Pulse Width Modulator
RSPWM consists comparator 7-bit counter clocked positive edge clock from RCLK pin, reset active high signal from pin. RSPWM output will after counter reset, high when counter value matches value RSPWM register. Figure shows example timings.
MOTOROLA
PULSE WIDTH MODULATION
MC68HC05BS8
Counter value matches RSPWM register
Counter reset (PB7) RSPWM counter RSPWM output
Figure RSPWM Timing Example
output pins RSPWM. They connected such that, them output waveform, while other always zero. This controlled Raster Polarity (RSP) RSPWM register. must configured input port GPWMR must before used input RSPWM reset signal. Figure shows block diagram RSPWM.
RSPWMR ($0011)
RSPW6:0
RSPWM logic
RCLK RSPWM counter
GPWMR
Figure RSPWM Block Diagram
MC68HC05BS8
PULSE WIDTH MODULATION
MOTOROLA
When used raster position control, RCLK clock signal which synchronized with frequency multiples horizontal sync signal. counter reset signal horizontal back signal. Both these signals will normally come from circuit.
7.2.1
Raster Positioning Pulse Width Modulator Register (RSPWM)
Address RSPWMR $0011 State reset
RSPW6 RSPW5 RSPW4 RSPW3 RSPW2 RSPW1 RSPW0 0000 0000 State reset
Address GPWMR $0010
GPW5 GPW4 GPW3 GPW2 GPW1 GPW0 0000 0000
Raster Polarity
(set)
output zero. RSPWM waveform output RSB. output zero. RSPWM waveform output RSA.
(clear)
RSPW6:0 RSPWM Data These bits contain pulse width modulator data RSPWM. RSPWM output remains after counter reset, turns high when counter value matches this value. Clear Reset Enable (set) configured reset input RSPWM. should also "0". normal operation.
(clear)
MOTOROLA
PULSE WIDTH MODULATION
MC68HC05BS8
M-BUS SERIAL INTERFACE
MC68HC05BS8 M-Bus Serial Interface; full hardware, other software supported. Section Section details full hardware M-Bus interface. Section details software supported M-Bus. M-Bus (Motorola Bus) two-wire, bidirectional serial which provides simple, efficient data exchange between devices. fully compatible with standard. This two-wire minimizes interconnection between devices eliminates need address decoders; resulting less traces economic hardware structure. This suitable applications requiring communications short distance among number devices. maximum data rate 100Kbit/s. maximum communication length number devices that connected limited maximum capacitance 400pF. M-Bus system true multi-master bus, including arbitration prevent data collision more masters intend control simultaneously. used rapid testing alignment products external connections assembly-line computer.
M-Bus Interface Features
Compatible with standard Multi-master operation software programmable serial clock frequencies Software selectable acknowledge Interrupt driven byte-by-byte data transfer Arbitration lost driven interrupt with automatic mode switching from master slave Calling address identification interrupt Generate/detect start, stop acknowledge signals Repeated START signal generation busy detection
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA
Internal Control register
MIEN MSTA TXAK
Status register
MAAS RXAK
Frequency divider register
Address register
Interrupt
M-Bus interrupt Address comparator
control
M-Bus clock generator sync logic shift register shift register
START, STOP detector arbitration
START, STOP generator timing sync
control
control
control
Figure M-Bus Interface Block Diagram
M-Bus Protocol
Normally, standard communication composed four parts, START signal, slave address transmission, data transfer, STOP signal. They described briefly following sections illustrated Figure 8-2.
MOTOROLA
M-BUS SERIAL INTERFACE
MC68HC05BS8
Acknowledge
acknowledge
START signal
STOP signal
Acknowledge
acknowledge
START signal
repeated START signal
STOP signal
Figure M-Bus Transmission Signal Diagram
8.2.1
START Signal
When free, i.e., master device occupying (both lines logic high), master initiate communication sending START signal. shown Figure 8-2, START signal defined high transition while high. This signal denotes beginning data transfer (each data transfer contain several bytes data) wakes slaves.
8.2.2
Slave Address Transmission
first byte data transfer immediately following START signal slave address transmitted master. This seven bits long calling address followed bit. dictates slave desired direction data transfer. Only slave with matched address will respond sending back acknowledge pulling clock; Figure 8-2.
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA
8.2.3
Data Transfer
Once successful slave addressing achieved, data transfer proceed byte byte direction specified sent calling master. Each data byte bits long. Data changed only when must held stable when high shown Figure 8-2. clock pulse data transfer, transferred first. Each data byte followed acknowledge bit. Hence, complete data byte transfer requires clock pulses. slave receiver does acknowledge master, line should left high slave, master then generate STOP signal abort data transfer START signal (repeated START) commence calling. master receiver does acknowledge slave transmitter after byte transmission, means "end data" slave. slave shall release line master generate STOP START signal.
8.2.4
Repeated START Signal
shown Figure 8-2, repeated START signal generate START signal without first generating STOP signal terminate communication. This used master communicate with another slave with same slave different mode (transmit/receive mode) without releasing bus.
8.2.5
STOP Signal
master terminate communication generating STOP signal free bus. However, master generate START signal followed calling command without generating STOP signal first. This called repeat START. STOP signal defined high transition while logical high; Figure 8-2.
8.2.6
Arbitration Procedure
This interface circuit true multi-master system which allows more than master connected. more masters control same time, clock synchronization procedure determines clock. clock period equal longest clock period among masters; clock high period shortest among masters. data arbitration procedure determines priority. master will lose arbitration transmits logic while others transmit logic "0", losing master will immediately switch over slave receive mode stops data clock outputs. transition from master slave mode will
MOTOROLA
M-BUS SERIAL INTERFACE
MC68HC05BS8
generate STOP condition. Meanwhile, software will hardware indicate loss arbitration.
8.2.7
Clock Synchronization
Since wire-AND logic performed line, high transition line will affect devices connected bus. devices start counting their period once device's clock gone low, will hold line until clock high state reached. However, change high this device clock change state line, another device clock still period. Therefore synchronized clock will held device which releases logic high last place. Devices with shorter periods enter high wait state during this time (see Figure 8-3). When devices concerned have counted their period, synchronized clock line will released high. them will start counting their high periods. first device complete high period will again pull line low.
WAIT
Start counting high period
SCL1
SCL2
Internal counter reset
Figure Clock Synchronization
8.2.8
Handshaking
clock synchronization mechanism used handshake data transfer. Slave device hold after completion byte transfer bits). such case, will halt clock force master clock wait state until slave releases line.
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA
M-Bus Registers
There five registers used M-Bus interface, these discussed following paragraphs.
8.3.1
M-Bus Address Register (MADR)
Address $0039 MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 State reset 0000 0000
MAD1-MAD7 slave address bits M-Bus module.
8.3.2
M-Bus Frequency Register (MFDR)
Address $003A State reset 0000 0000
FD0-FD4 used clock rate selection. serial clock frequency equal clock divided divider shown Table 8-1.
Table M-Bus Prescaler
DIVIDER DIVIDER 1088 1408 1536 1792 2176 2816 3072 3584 4352
MOTOROLA
M-BUS SERIAL INTERFACE
MC68HC05BS8
4MHz external crystal operation (2MHz internal operating frequency), serial clock frequency M-Bus ranges from 460Hz 90,909Hz.
8.3.3
M-Bus Control Register (MCR)
Address $003B MIEN MSTA TXAK SIFC SIIC State reset 0000 0000
Register definitions: M-Bus Enable (set) M-Bus interface system enabled. M-Bus interface system disabled.
(clear)
MIEN M-Bus Interrupt Enable (set) M-Bus interrupt enabled. M-Bus interrupt disabled.
(clear)
This enables MSR) M-Bus interrupts. MSTA Master/Slave Select (set) M-Bus master mode operation. M-Bus slave mode operation.
(clear)
Upon reset, this cleared. When this changed from START signal generated bus, master mode selected. When this changed from STOP signal generated operation mode changes from master slave. master mode, clear immediately followed this generates repeated START signal without generating STOP signal. Transmit/Receive Mode Select (set) M-Bus transmit mode. M-Bus receive mode.
(clear)
TXAK Acknowledge Enable (set) send acknowledge signal. Send acknowledge signal clock bit.
(clear)
cleared, acknowledge signal will sent clock after receiving byte data. set, acknowledge signal response. This active control bit.
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA
8.3.4
M-Bus Status Register (MSR)
Address $003C MAAS RXAK State reset 1000 0001
bits software clearable; while other bits read only. Data Transfer Complete (set) byte transfer been completed. byte being transfer.
(clear)
When set, (M-Bus interrupt) also set. M-Bus interrupt generated MIEN set. MAAS Addressed Slave (set) Currently addressed slave. currently addressed.
(clear)
This MAAS when specific address (M-Bus Address register) matches calling address. When MAAS set, (M-Bus interrupt) also set. interrupt generated MIEN set. Then needs check accordingly. Writing M-Bus Control register clears this bit. Busy (set) M-Bus busy. M-Bus idle.
(clear)
This indicates status bus. When START signal detected, set. When STOP signal detected, cleared. Arbitration Lost (set) Lost arbitration master mode. arbitration lost.
(clear)
This arbitration lost flag when M-Bus master loses arbitration during master transmission mode. When set, (M-Bus interrupt) also set. This must cleared software.
MOTOROLA
M-BUS SERIAL INTERFACE
MC68HC05BS8
Slave Select (set) Read from slave, from calling master Write slave from calling master.
(clear)
When MAAS set, command calling address sent from master latched into this bit. checking this bit, then select slave transmit/receive mode configuring M-Bus Control register. M-Bus Interrupt (set) M-Bus interrupt occurred. M-Bus interrupt occurred.
(clear)
When this set, interrupt generated MIEN set. This when following events occurs: Completion byte data transfer. falling edge clock set. match calling address with specific address slave mode MAAS set. loss arbitration set. This must cleared software interrupt routine. RXAK Receive Acknowledge (set) acknowledgment signal detected. Acknowledgment signal detected after bits data transmitted.
(clear)
cleared, indicates acknowledge signal been received after completion bits data transmission bus. set, acknowledge signal been detected clock. This active status flag.
8.3.5
M-Bus Data Register (MDR)
Address $003D State reset uuuu uuuu
master transmit mode, data written into this register sent automatically, with most significant first. master receive mode, reading this register initiates receiving next byte data. slave mode, same function applies after been addressed.
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA
Clear
Master Mode?
TX/RX?
Arbitration Lost? Clear
Last byte transmitted?
Last byte read?
Generate STOP signal
MAAS=1?
RXAK=0?
Last byte read? TXAK=1
MAAS=1? TX/RX? from receiver? mode Dummy read mode Write
Write
SRW=1?
Generate STOP signal
Read from
Write
Figure Flowchart M-Bus Interrupt Routine
MOTOROLA 8-10
M-BUS SERIAL INTERFACE
MC68HC05BS8
8.4.1
Programming Considerations Initialization
Reset will M-Bus Control register default status. Before interface used transfer serial data, following initialization procedure must carried out. Update Frequency Divider Register (MFDR) select frequency. Update M-Bus Address Register (MADR) define slave address. M-Bus Control Register (MCR) enable M-Bus interface system. Modify bits M-Bus Control Register (MCR) select Master/Slave mode, Transmit/Receive mode, interrupt enable not.
8.4.2
Generation START Signal First Byte Data Transfer
After completion initialization procedure, serial data transmitted selecting master transmit mode. device connected multi-master system, state M-Bus busy (MBB) must tested check serial free. free (MBB=0), START condition first byte (the slave address) sent. example program which generates START signal transmits first data byte (slave address) shown below: CHFLAG BRSET 5,MSR,CHFLAG 4,MCR 5,MCR #CALLING DISABLE INTERRUPT CHECK STATUS REGISTER. SET, WAIT UNTIL CLEAR TRANSMIT MODE MASTER MODE i.e. GENERATE START CONDITION CALLING ADDRESS TRANSMIT CALLING ADDRESS ENABLE INTERRUPT
TXSTART
BSET BSET
8.4.3
Software Responses after Transmission Reception Byte
Upon completion transmission reception data byte, data transferring (MCF) will set, indicating byte communication been finished. M-Bus interrupt (MIF) will also generate M-Bus interrupt interrupt enabled. Software must clear
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA 8-11
interrupt routine first. cleared reading M-Bus Data Register (MDR) receive mode writing transmit mode. Software serve M-Bus main program monitoring interrupt disabled. following example software response master transmit mode interrupt routine (see Figure 8-4). BCLR BRCLR BRCLR BRSET 4,MCR,RECEIVE 0,MSR,END DATABUF 1,MSR 5,MCR,SLAVE CLEAR FLAG CHECK MSTA FLAG, BRANCH SLAVE MODE CHECK MODE FLAG, BRANCH RECEIVE MODE CHECK FROM RECEIVER ACK, TRANSMISSION NEXT BYTE DATA TRANSMIT DATA
TRANSMIT
8.4.4
Generation STOP Signal
data transfer ends with STOP signal generated master device. master transmit mode simply generate STOP signal after data have been transmitted. following example showing STOP condition generated master transmit mode. MASTX BRSET 0,MSR,END TXCNT BCLR EMASTX DATABUF TXCNT EMASTX 5,MCR ACK, BRANCH VALUE FROM TRANSMITTING COUNTER MORE DATA, BRANCH NEXT BYTE DATA TRANSMIT DATA DECREASE TXCNT EXIT GENERATE STOP CONDITION RETURN FROM INTERRUPT
master receiver wants terminate data transfer, must inform slave transmitter acknowledging last byte data. This achieved setting transmit acknowledge (TXAK) before reading last byte data. Before reading last byte data, STOP signal must generated first. following example showing STOP signal generated master receive mode. MASR DECA RXCNT ENMASR RXCNT NXMAR LAST BYTE READ CHECK LAST BYTE READ LAST LAST SECOND
MOTOROLA 8-12
M-BUS SERIAL INTERFACE
MC68HC05BS8
LAMAR
BSET
3,MCR NXMAR 5,MCR RXBUF
LAST SECOND, DISABLE TRANSMITTING LAST ONE, GENERATE 'STOP' SIGNAL READ DATA STORE
ENMASR BCLR NXMAR
8.4.5
Generation Repeated START Signal
data transfer, master still wants communicate bus, generate another START signal followed another slave address without first generating STOP signal. program example shown. RESTART BCLR BSET 5,MCR 5,MCR #CALLING ANOTHER START (RESTART) GENERATED THESE CONSECUTIVE INSTRUCTIONS CALLING ADDRESS TRANSMIT CALLING ADDRESS
8.4.6
Slave Mode
slave service routine, master addressed slave (MAAS) should tested check calling address been received (Figure 8-4). MAAS set, software should transmit/receive mode select (MTX MCR) according command (SRW). Writing clears MAAS automatically. data transfer then initiated writing dummy read from MDR. slave transmit routine, received acknowledge (RXAK) must tested before transmitting next byte data. RXAK, indicates data signal from master receiver, slave transmitter must then switch from transmit mode receive mode software dummy read must follow release line that master generate STOP signal.
8.4.7
Arbitration Lost
more than master want acquire simultaneously, only master others will lose arbitration. losing device immediately switches slave receive mode M-Bus hardware. data output line stopped, internal transmit clock still runs until data byte transmission. interrupt occurs when this dummy byte transmission
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA 8-13
accomplished with MAL=1 MSTA=0. master attempts start transmission while being controlled another master, transmission will inhibited; MSTA will changed from without generating STOP condition; interrupt will generated indicate that attempt acquire failed. Considering these cases, slave service routine should test first, software should clear set.
Software Supported M-Bus Interface
Port pins designed with hardware interrupt circuit software supported M-Bus interface detect "Start" condition M-Bus protocol. This interrupt uses same interrupt vector hardware M-Bus interrupts, address $3FF2 $3FF3. user responsible determining source M-Bus interrupt interrupt service routine reading flags.
SIIC
PC6/SCL2
PC7/SDA2
interrupt request
Reset SIFC
START PC7/SDA2
STOP
PC6/SCL2
Figure Software Supported M-Bus Interrupt
MOTOROLA 8-14
M-BUS SERIAL INTERFACE
MC68HC05BS8
software supported M-Bus interrupt related control status bits following registers:
Address $003B MIEN MSTA TXAK SIFC SIIC State reset 0000 0000 State reset
Address $003C
MAAS
RXAK 1000 0001
SIFC Software M-Bus Interrupt Flag Clear (set) Clear software supported M-Bus interrupt flag MSR. effect.
(clear)
SIIC Software M-Bus Enable (set) satisfies "Start" condition M-Bus protocol, will M-Bus interrupt will generated. pins configured standard operation.
(clear)
Software Supported M-Bus Interrupt Flag (set) Software M-Bus interrupt occurred. software M-Bus interrupt occurred.
(clear)
MC68HC05BS8
M-BUS SERIAL INTERFACE
MOTOROLA 8-15
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MOTOROLA 8-16
M-BUS SERIAL INTERFACE
MC68HC05BS8
SYNC SIGNAL PROCESSOR
This section describes operation module MC68HC05BS8.
Introduction
functions include following: Polarity correction Sync separation Sync pulse reshaping Sync pulse detection Horizontal line counting Vertical frequency counting Free running signals generation
addition, interrupt generated each vertical frame user specified horizontal line number. accepts composite signals from video processor separate sync inputs from host computer. separate sync inputs, HTTL output identical incoming horizontal sync with negative sync polarity. VTTL output triggered leading edge incoming sync pulse, sync pulse reshaper will correct pulse width certain time period regardless incoming sync width. Reassembled sync pulses inserted HTTL signal during vertical sync period composite sync input. HSYNC, VSYNC, CSYNC inputs have internal filters improve noise immunity. pulse that shorter than internal clock periods will regarded glitch, will ignored.
Note:
quoted timings this section based internal frequency 2MHz, i.e. tCYC =0.5µs, unless otherwise stated.
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA
Polarity Correction
polarity correction block sync signal processor accepts input sync signals converts them negative polarity signals, regardless polarity inputs. following describes methodologies used polarity correction.
9.2.1
Separate Vertical Sync Input
test polarity input sync signal, duration pulse examined. period longer than specific value (512µs 1024tCYC), case positive polarity input sync, input sync will inverted before output. negative polarity input sync signal, anticipated that duration pulse would shorter than specific value, input sync signal passes through output without inversion. This polarity correction continuous process, error margin equal maximum permissible sync pulse width specified (512µs 1024tCYC). power-up system reset, negative polarity input assumed.
9.2.2
Separate Horizontal Composite Sync Input
Since input HSYNC either pure horizontal sync signal composite sync signal, different methodologies used polarity correction.
Unlike polarity correction VSYNC, both high pulse pulse sync signal HSYNC examined. pulse, either active high low, longer than certain period (8µs tCYC), will regarded long pulse. there consecutive long pulses, input sync signal will confirmed positive polarity sync signal, will inverted. there consecutive high long pulses, will confirmed negative polarity sync signal. operation this module also continuous, error margin equal period pre-set number (default horizontal sync pulses. power-up system reset, negative polarity input assumed.
MOTOROLA
SYNC SIGNAL PROCESSOR
MC68HC05BS8
Positive polarity pure horizontal sync signal
Negative polarity pure horizontal sync signal
Positive polarity composite sync signal
Negative polarity composite sync signal
Figure Sync Signal Polarity Correction
Sync Detection
sync detector determines whether incoming sync signal active. Both sync high pulse widths must within specific values regarded active. respective HDET and/or VDET flags will HSYNC VSYNC signals active.
Free-running Pseudo Sync Signal Generator
active sync signals detected, free-running sync signal generator will enabled. generates pseudo vertical sync 63.78Hz (1/(tCYC 31360)) pseudo horizontal sync 57.14KHz (1/(tCYC 35)). This free running sync signals replaces inactive sync signals inputs will VTTL HTTL pins pins selected VTTL HTTL function. both vertical horizontal sync signals detected (VDET HDET set), SOUT must order output processed signals.
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA
Sync Separation
Figure block diagram Sync Separator which includes duration counters high pulses, counter number valid horizontal sync pulses, register hold number horizontal lines frame, logic block horizontal vertical sync pulse separation, comparator, sync pulse insertion circuit.
load Csync Horizontal Line counter reset count Horizontal Line Register
pulse duration counter Csync
Comparator equal Vertical Sync separation logic
High pulse duration counter
finish
Sync insertion circuit
Hsync
Vsync
Figure Sync Separator pulse duration counter examines pulse width incoming composite sync signal. within horizontal sync pulse limit (8µs tCYC), horizontal sync pulse detected, horizontal line counter advanced. pulse wider than limit, vertical sync pulse detected, content Horizontal line counter loaded into Horizontal Line register. pulse duration counter then resets Horizontal line counter. High Pulse Duration Counter examines high pulse width incoming composite sync signal. longer than specific value (8µs tCYC), vertical sync pulse finished "finish" signal will given Sync Separation Logic. Sync Separation Logic passes Csync signal Hsync output until there "equal" signal from comparator. Hsync output will then output reassembled waveform Sync Insertion Circuit emulate Hsync pulses, Vsync output "low" coming falling edge Csync signal. After "finish" signal been sensed, Vsync output fixed "high", Hsync output follows Csync input again.
MOTOROLA
SYNC SIGNAL PROCESSOR
MC68HC05BS8
Vertical Sync Pulse Reshaper
vertical sync pulse width VTTL output formatted Vertical Sync Pulse Reshaper, such that, it's falling edge follows input signal's falling edge, it's rising edge falling edge input horizontal sync signal (HSYNC). Notice that, input signal composite signal, VTTL pulse width will longer, there falling edge during vertical sync pulse period. Figure shows different VTTL pulse widths different input signal formats.
VSYNC HSYNC Re-shaped VTTL output CSYNC with pulses during pulse period Re-shaped VTTL output CSYNC without pulses during pulse period Re-shaped VTTL output
Figure VTTL Pulse Widths Different Input Signal Formats
Sync Signal Counters
There counters (horizontal line counter vertical frequency counter) count number horizontal sync pulses number system clock cycles between vertical sync pulses. These data read check signal frequencies used determine video mode. Notice that value vertical frequency counter will subtracted before loading into Vertical Frequency register. this way, 9-bit register cover vertical frequency ranged from 42Hz 130Hz. Figure shows more detailed block diagram these counters. Figure shows vertical frequency counter timings. indicates that there will count error reading from register same vertical frequency.
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA
VSYNC Counter signal reset case case Counter advances rising edge clock value counter will loaded into register before reset. Vertical Frequency Counter clocked clock. Because asynchronous nature between VSYNIN, register will have more count case than case Counter resets cycles after falling edge VSYNIN
Figure Vertical Frequency Counter Timing
VSYNC Interrupt
will process Sync Signal Processor VSYNC interrupt following conditions satisfied: I-bit cleared, VSIE Interrupt Line Count register (ILCR) set, value horizontal line counter matches value ILCR. This interrupt will vector interrupt service routine located address specified contents $3FF8 $3FF9. VSYNC interrupt latch will cleared automatically fetching these vectors. This allows interrupt generated each vertical frame after certain number lines (0-127) check status monitor conditions.
MOTOROLA
SYNC SIGNAL PROCESSOR
MC68HC05BS8
Sampling Pulse Output
circuit responsible generating signal Video Chip set. signal sampling signal, which outputs positive pulse Vsync pulse, outputs another positive pulse when value Sampling Pulse register matches horizontal line counter. pulse width equal horizontal line period.
9.10
Registers
There registers associated with Sync Signal Processor, these described below.
9.10.1
Sync Signal Control Status Register (SSCSR)
VPOL HPOL VDET HDET SOUT INSRT SIN1 SIN0 State reset 0000 0000
Address $000A
VPOL Vertical Sync Input Polarity (set) VSYNC input positive polarity. VSYNC input negative polarity.
(clear)
Vertical Sync Input Polarity flag indicates polarity incoming signal VSYNC input. HPOL Horizontal Sync Input Polarity (set) HSYNC input positive polarity. HSYNC input negative polarity.
(clear)
Horizontal Sync Input Polarity flag indicates polarity incoming signal HSYNC input. VDET Vertical Sync Signal Detect (set) active vertical sync detected VSYNC input. vertical sync signal VSYNC input; internal generated Vsync VTTL.
(clear)
This when active vertical sync signal detected VSYNC pin. cleared, indicates there active signal, VTTL will output internally generated Vsync signal. active vertical sync signal defined
VDET (VSYNC pulse width 1024tCYC) (15.36x103tCYC VSYNC period 48.128x103tCYC)
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA
HDET Horizontal Sync Signal Detect (set) active horizontal sync detected HSYNC input. horizontal sync signal HSYNC input; internal generated Hsync HTTL.
(clear)
This when active horizontal sync signal detected HSYNC pin. cleared, indicates there active signal, HTTL will output internally generated Hsync signal. active horizontal sync signal defined
HDET=(HSYNC pulse width 16tCYC) (HSYNC period 128tCYC) line frame 4096) (VDET=0)]
SOUT Sync Output Select (set) processed VSYNC HSYNC inputs VTTL HTTL. internally generated sync signals VTTL HTTL.
(clear)
When cleared, outputs VTTL HTTL internally generated signals. When set, outputs processed input signals. This only both VDET HDET logic 1's, will cleared automatically VDET HDET logic "1". Reset clears this bit. INSRT Hsync Insertion (set) inserted pulses. HTTL will always follow HSYNC input. composite sync inputs, emulated sync pulses will inserted into HTTL signal during vertical sync pulse.
(clear)
separate sync inputs, when this Hsync Insertion cleared, sync pulses will continue Hsync signal during vertical sync pulse. composite sync input, when this cleared, emulated sync pulses will inserted into HTTL during vertical sync pulse. both cases, when this set, there will inserted pulses, HTTL will always follow HSYNC input. Reset clears this bit. SIN1:SIN0 Sync Input Source These bits selects source input sync signals. Reset clears these bits.
SIN1
SIN0
Sync input source Separated sync signal through VSYNC HSYNC inputs. Composite sync signal through HSYNC input. Composite sync signal through CSYNC input.
MOTOROLA
SYNC SIGNAL PROCESSOR
MC68HC05BS8
9.10.2
Vertical Frequency Register (VFR)
Address $000B State reset 0000 0000
This 9-bit (the LFHR $0C) read only register used calculate vertical frame frequency. 10-bit counter counts number internal clocks between VSYNC pulses. counted value will then transferred this register. data corresponds period vertical frame. This register read determine frame frequency valid, determine video mode. Note that data valid only VDET= frame frequency calculated 1/((VFR±1 240)x16tCYC). Table shows sample values Vertical Frequency register, numbers hexadecimal.
Table Vertical Frame Frequencies
$004 $005 $006 $007 Min. Freq. 127.6 127.0 126.5 126.0 Max. Freq. 128.6 128.1 127.6 127.0 $1FA $1FB $1FC $1FD Min. Freq. 41.8 41.8 41.7 41.7 Max. Freq. 41.9 41.8 41.8 41.8
9.10.3
Line Frequency Registers (LFRs)
Address LFHR LFLR $000C $000D LF11 LF10 State reset 0000 0000 0000 0000
This 12-bit read only register pair contains number lines each vertical frame. internal line counter counts number horizontal sync pulses between vertical sync pulses then transfers counted value this register. data read determine line frequency valid, determine video mode. Note that data valid only HDET=VDET= ninth Vertical Frequency register (VFR).
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA
9.10.4
Interrupt Line Count Register (ILCR)
Address ILCR $000E VSIE State reset 0000 0010
This read/write register containing line number which Vertical Sync Interrupt generated. Interrupt will generated VSIE set, cleared, internal line counter value matches setting this register after Vsync pulse. Vsync Interrupt Vectors $3FF8 $3FF9, interrupt latch cleared fetching interrupt vectors. VSIE Vsync Interrupt Enable This enables disables Vsync interrupt. (set) Vsync interrupt enabled. Vsync interrupt disabled.
(clear)
LC6:0 Line Count Vsync Interrupt These bits store line number which Vsync Interrupt will occur. number ranged from 127.
9.10.5
Sampling Pulse Register (SPR)
Address $000F State reset 0000 0010
This read/write register contains line number which sampling pulse output generated. line number ranged from 127. Sampling pulses produced when there Vsync pulse, this register matches horizontal line counter.
9.11
System Operation
sync processor accepts sync signals from main computer; signals either separate Hsync Vsync composite sync through HSYNC input. Polarity correction performed before sync signals further into system. sync pulse detection blocks will continuously monitor signal, active. signal active, circuit will switch output internally generated clock signal. This will protect circuits behind from being damaged inactive signal.
MOTOROLA 9-10
SYNC SIGNAL PROCESSOR
MC68HC05BS8
Figure shows example operation.
START
HDET, VDET=1?
Valid sync signal found video mode SOUT
Delay sync signals stable detection
SIN1, SIN0=?
SIN1, SIN0=0,
SIN1, SIN0=1, Send signal video chip Sync-On-Green signal
valid sync signals found
ILCR desired
Continue with corresponding program
Continue with main program
Figure Example operation
MC68HC05BS8
SYNC SIGNAL PROCESSOR
MOTOROLA 9-11
THIS PAGE LEFT BLANK INTENTIONALLY
MOTOROLA 9-12
SYNC SIGNAL PROCESSOR
MC68HC05BS8
CORE INSTRUCTION
This section provides description core registers, instruction addressing modes MC68HC05BS8.
10.1
Registers
contains five registers, shown programming model Figure 10-1. interrupt stacking order shown Figure 10-2.
Accumulator Index register Program counter Stack pointer Condition code register Carry borrow Zero Negative Interrupt mask Half carry
Figure 10-1 Programming model
10.1.1
Accumulator
accumulator general purpose 8-bit register used hold operands results arithmetic calculations data manipulations.
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-1
Increasing memory address Condition code register Accumulator Index register Program counter high Program counter Return
Stack Interrupt Decreasing memory address
Unstack
Figure 10-2 Stacking order
10.1.2
Index register
index register 8-bit register, which contain indexed addressing value used create effective address. index register also used temporary storage area.
10.1.3
Program counter (PC)
program counter 16-bit register, which contains address next byte fetched.
10.1.4
Stack pointer (SP)
stack pointer 16-bit register, which contains address next free location stack. During reset reset stack pointer (RSP) instruction, stack pointer location $00FF. stack pointer then decremented data pushed onto stack incremented data pulled from stack.
When accessing memory, most significant bits permanently 0000000011. These bits appended least significant register bits produce address within range $00C0 $00FF. Subroutines interrupts (decimal) locations. locations exceeded, stack pointer wraps around overwrites previously stored information. subroutine call occupies locations stack; interrupt uses five locations.
10.1.5
Condition code register (CCR)
5-bit register which four bits used indicate results instruction just executed, fifth indicates whether interrupts masked. These bits individually tested program, specific actions taken result their state. Each explained following paragraphs. Half carry This during operations indicate that carry occurred between bits
MOTOROLA 10-2
CORE INSTRUCTION
MC68HC05BS8
Interrupt When this set, maskable interrupts masked. interrupt occurs while this set, interrupt latched remains pending until interrupt cleared. Negative When set, this indicates that result last arithmetic, logical, data manipulation negative. Zero When set, this indicates that result last arithmetic, logical, data manipulation zero. Carry/borrow When set, this indicates that carry borrow arithmetic logical unit (ALU) occurred during last arithmetic operation. This also affected during test branch instructions during shifts rotates.
10.2
Instruction
basic instructions. They grouped into five different types follows: Register/memory Read/modify/write Branch manipulation Control
following paragraphs briefly explain each type. instructions within given type presented individual tables. This uses instructions available M146805 CMOS family plus more: unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication contents accumulator index register (X). high-order product then stored index register low-order product stored accumulator. detailed definition instruction shown Table 10-1.
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-3
10.2.1
Register/memory Instructions
Most these instructions operands. first operand either accumulator index register. second operand obtained from memory using addressing modes. jump unconditional (JMP) jump subroutine (JSR) instructions have register operand. Refer Table 10-2 complete list register/memory instructions.
10.2.2
Branch instructions
These instructions cause program branch particular condition met; otherwise, operation performed. Branch instructions two-byte instructions. Refer Table 10-3.
10.2.3
manipulation instructions
clear writable that resides first bytes memory space (page port data data direction registers, timer serial interface registers, control/status registers portion on-chip reside page additional feature allows software test branch state within these locations. set, clear, test branch functions implemented with single instructions. test branch instructions, value tested also placed carry condition code register. Refer Table 10-4.
10.2.4
Read/modify/write instructions
These instructions read memory location register, modify test contents, write modified value back memory register. test negative zero (TST) instruction exception this sequence reading, modifying writing, since does modify value. Refer Table 10-5 complete list read/modify/write instructions.
10.2.5
Control instructions
These instructions register reference instructions used control processor operation during program execution. Refer Table 10-6 complete list control instructions.
10.2.6
Tables
Tables instruction types listed above follow. addition there complete alphabetical listing instructions (see Table 10-7), opcode instruction M68HC05 family (see Table 10-8).
MOTOROLA 10-4
CORE INSTRUCTION
MC68HC05BS8
Table 10-1 instruction
Multiplies eight bits index register eight Description bits accumulator places 16-bit result concatenated accumulator index register. Cleared affected Condition affected codes affected Cleared Source Addressing mode Cycles Bytes Opcode Form Inherent Operation
Table 10-2 Register/memory instructions
Addressing modes Immediate Mnemonic Direct Extended Indexed offset) Cycles Opcode Opcode Bytes Indexed (8-bit offset) Cycles Opcode Bytes Indexed (16-bit offset) Cycles Bytes
Cycles
Cycles
Function Load from memory Load from memory Store memory Store memory memory memory carry Subtract memory Subtract memory from with borrow memory with memory with Exclusive memory with Arithmetic compare with memory Arithmetic compare with memory test memory with (logical compare) Jump unconditional Jump subroutine
Cycles
Opcode
Opcode
Opcode
Bytes
Bytes
Bytes
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-5
Table 10-3 Branch instructions
Relative addressing mode Opcode Bytes Cycles
Function Branch always Branch never Branch higher Branch lower same Branch carry clear (Branch higher same) Branch carry (Branch lower) Branch equal Branch equal Branch half carry clear Branch half carry Branch plus Branch minus Branch interrupt mask clear Branch interrupt mask Branch interrupt line Branch interrupt line high Branch subroutine
Mnemonic (BHS) (BLO) BHCC BHCS
Table 10-4 manipulation instructions
Addressing modes set/clear test branch Opcode Bytes Cycles Opcode Bytes Cycles
Function Branch Branch clear Clear
Mnemonic BRSET (n=0-7) BRCLR (n=0-7) BSET (n=0-7) BCLR (n=0-7)
MOTOROLA 10-6
CORE INSTRUCTION
MC68HC05BS8
Table 10-5 Read/modify/write instructions
Addressing modes Inherent Mnemonic Cycles Opcode Inherent Cycles Opcode Opcode Direct Indexed offset) Cycles Cycles Opcode Bytes Indexed (8-bit offset) Cycles Opcode Bytes
Bytes
Bytes
Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test negative zero Multiply
Bytes
Table 10-6 Control instructions
Inherent addressing mode Opcode Bytes Cycles
Function Transfer Transfer carry Clear carry interrupt mask Clear interrupt mask Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait
Mnemonic STOP WAIT
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-7
Table 10-7 Instruction
Addressing modes Condition codes
Mnemonic BCLR BHCC BHCS BRCLR BRSET BSET
Address mode abbreviations
set/clear test branch Direct Extended Inherent Immediate Indexed offset) Indexed, byte offset Indexed, byte offset Relative implemented
Condition code symbols
Half carry (from Interrupt mask Negate (sign bit) Zero Carry/borrow Tested true, cleared otherwise affected Load from stack Cleared
MOTOROLA 10-8
CORE INSTRUCTION
MC68HC05BS8
Table 10-7 Instruction (Continued)
Addressing modes Condition codes
Mnemonic STOP WAIT
Address mode abbreviations
set/clear test branch Direct Extended Inherent Immediate Indexed offset) Indexed, byte offset Indexed, byte offset Relative implemented
Condition code symbols
Half carry (from Interrupt mask Negate (sign bit) Zero Carry/borrow Tested true, cleared otherwise affected Load from stack Cleared
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-9
Control High
MOTOROLA 10-10
0011
High
NEGA
manipulation 0000 0001 0100 NEGX
Branch 0010 0111
Read/modify/write 0101 0110 1000
1001
1010
1011
Register/memory 1100 1101 1110
1111
BRSET0
BSET0
BRCLR0
BCLR0
BRSET1
BSET1 COMA LSRA
COMX LSRX
BRCLR1
BCLR1
BRSET2
BSET2
BRCLR2
BCLR2 RORA ASRA LSLA ROLA DECA
RORX ASRX LSLX ROLX DECX
BRSET3
BSET3
BRCLR3
BCLR3
BRSET4
BSET4
BHCC
BRCLR4
BCLR4
BHCS
BRSET5
BSET5
BRCLR5
BCLR5 INCA TSTA STOP
INCX TSTX
BRSET6
BSET6
BRCLR6
BCLR6
BRSET7
BSET7 CLRA
CLRX
Table 10-8 M68HC05 opcode
CORE INSTRUCTION
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
BRCLR7
BCLR7
WAIT
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Abbreviations address modes registers
Legend 1111 Mnemonic
Opcode hexadecimal Opcode binary implemented Bytes Cycles Address mode
Indexed offset) Indexed, byte (8-bit) offset Indexed, byte (16-bit) offset Relative Accumulator Index register
set/clear test branch Direct Extended Inherent Immediate
MC68HC05BS8
0000
10.3
Addressing modes
different addressing modes provide programmers with flexibility optimize their code situations. various indexed addressing modes make possible locate data tables, code conversion tables scaling tables anywhere memory space. Short indexed accesses single byte instructions; longest instructions (three bytes) enable access tables throughout memory. Short absolute (direct) long absolute (extended) addressing also included. byte direct addressing instructions access data bytes most applications. Extended addressing permits jump instructions reach memory locations. term `effective address' (EA) used describing various addressing modes. effective address defined address from which argument instruction fetched stored. addressing modes processor described below. Parentheses used indicate `contents location register referred example, (PC) indicates contents location pointed (program counter). arrow indicates replaced colon indicates concatenation bytes. additional details graphical illustrations, refer M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual M68HC05 Applications Guide.
10.3.1
Inherent
inherent addressing mode, information necessary execute instruction contained opcode. Operations specifying only index register accumulator, well control instruction, with other arguments included this mode. These instructions byte long.
10.3.2
Immediate
immediate addressing mode, operand contained byte immediately following opcode. immediate addressing mode used access constants that change during program execution (e.g. constant used initialize loop counter). PC+1; PC+2
10.3.3
Direct
direct addressing mode, effective address argument contained single byte following opcode byte. Direct addressing allows user directly address lowest bytes memory with single two-byte instruction. (PC+1); PC+2 Address high Address (PC+1)
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-11
10.3.4
Extended
extended addressing mode, effective address argument contained bytes following opcode byte. Instructions with extended addressing mode capable referencing arguments anywhere memory with single three-byte instruction. When using Motorola assembler, user need specify whether instruction uses direct extended addressing. assembler automatically selects short form instruction. (PC+1):(PC+2); PC+3 Address high (PC+1); Address (PC+2)
10.3.5
Indexed, offset
indexed, offset addressing mode, effective address argument contained 8-bit index register. This addressing mode access first memory locations. These instructions only byte long. This mode often used move pointer through table hold address frequently referenced location. PC+1 Address high Address
10.3.6
Indexed, 8-bit offset
indexed, 8-bit offset addressing mode, effective address contents unsigned 8-bit index register unsigned byte following opcode. Therefore operand located anywhere within lowest memory locations. This addressing mode useful selecting element element table.
10.3.7
X+(PC+1); PC+2 Address high Address X+(PC+1) where carry from addition (PC+1)
Indexed, 16-bit offset
indexed, 16-bit offset addressing mode, effective address contents unsigned 8-bit index register unsigned bytes following opcode. This address mode used manner similar indexed, 8-bit offset except that this three-byte instruction allows tables anywhere memory. with direct extended addressing, Motorola assembler determines shortest form indexed addressing. X+[(PC+1):(PC+2)]; PC+3 Address high (PC+1)+K; Address X+(PC+2) where carry from addition (PC+2)
MOTOROLA 10-12
CORE INSTRUCTION
MC68HC05BS8
10.3.8
Relative
relative addressing mode only used branch instructions. relative addressing, contents 8-bit signed byte (the offset) following opcode added only branch conditions true. Otherwise, control proceeds next instruction. span relative addressing from -126 +129 from opcode address. programmer need calculate offset when using Motorola assembler, since calculates proper offset checks that within span branch. PC+2+(PC+1); branch taken; otherwise PC+2
10.3.9
set/clear
set/clear addressing mode, cleared part opcode. byte following opcode specifies address byte which specified cleared. read/write first locations memory, including I/O, selectively cleared with single two-byte instruction. (PC+1); PC+2 Address high Address (PC+1)
10.3.10
test branch
test branch addressing mode combination direct addressing relative addressing. tested condition (set clear) included opcode. address byte tested single byte immediately following opcode byte (EA1). signed relative 8-bit offset third byte (EA2) added specified cleared specified memory location. This single three-byte instruction allows program branch based condition readable first locations memory. span branch from -125 +130 from opcode address. state tested also transferred carry condition code register. (PC+1); PC+2 Address high Address (PC+1) PC+3+(PC+2); branch taken; otherwise PC+3
MC68HC05BS8
CORE INSTRUCTION
MOTOROLA 10-13
THIS PAGE LEFT BLANK INTENTIONALLY
MOTOROLA 10-14
CORE INSTRUCTION
MC68HC05BS8
POWER MODES
MC68HC05BS8 low-power operating modes: STOP mode WAIT mode. These modes help reduce power required stopping various internal clocks and/or on-chip oscillator. flow STOP WAIT modes shown Figure 11-1.
11.1
STOP Mode
STOP instruction places lowest power consumption mode. STOP mode internal oscillator turned off, halting internal processing. When enters STOP mode, I-bit Condition Code Register will cleared automatically. This enables external hardware interrupt "wake-up" MCU. other registers memory remain unchanged. input/output lines remain unchanged. brought STOP mode only hardware interrupt externally generated reset (POR RESET). When exiting STOP mode internal oscillator will resume after 4064 internal processor clock cycle oscillator stabilization delay.
Note:
STOP mode cannot entered watchdog timer running.
11.2 WAIT Mode
WAIT instruction places power mode. WAIT mode internal processor clock halted, suspending processor internal activity. Other internal clocks remain active, permitting interrupts generated from sub-systems, reset generated from Watchdog Timer. Timer used generate periodic exit from WAIT mode. Execution WAIT instruction automatically clears I-bit Condition Code Register, that hardware interrupt "wake-up" MCU. other registers, memory, input/output lines remain their previous states.
MC68HC05BS8
POWER MODES
MOTOROLA 11-1
STOP
WAIT
Stop external oscillator; Stop internal timer clock; Reset start-up delay.
External oscillator active Internal timer clock active
Stop internal processor clock, Clear I-bit
Stop internal processor clock, Clear I-bit
External reset? External reset?
External reset?
Internal reset?
Restart external oscillator; Stabilization delay.
External reset? Internal interrupt?
Start-up delay?
Restart internal processor clock
Fetch reset vector Service interrupt Stack I-bit Vector interrupt routine
Figure 11-1 STOP WAIT Flowchart
MOTOROLA 11-2
POWER MODES
MC68HC05BS8
11.3
Data Retention Mode
contents registers retained supply voltages 2.0V This called data-retention mode where data held, device guaranteed operate. RESET must held during data-retention mode.
11.4
Watchdog Timer Considerations
Watchdog Timer enabled default after reset, disabled writing Option register (bit address $1D). Once enabled, execution STOP instruction will executed WAIT instruction. That STOP mode cannot entered Watchdog Timer enabled. Watchdog Timer enabled, will reset when times out. system that must have intentional uses WAIT mode, care must taken prevent such situations from happening during normal operations arranging timely interrupts r
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