28F800C3, 28F160C3, 28F320C3 (x16) Flexible SmartVoltage Technolo
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Intel® Advanced+ Boot Block Flash Memory (C3)
28F800C3, 28F160C3, 28F320C3 (x16)
Flexible SmartVoltage Technology read/program/erase fast production programming 1.65 Option Reduces overall system power High Performance access time Optimized Architecture Code Plus Data Storage Eight Kword blocks, bottom parameter boot Kword blocks Fast program suspend capability Fast erase suspend capability Flexible Block Locking Lock/unlock block Full protection power-up Write Protect (WP#) hardware block protection Power Consumption typical read typical standby with Automatic Power Savings feature Extended Temperature Operation
128-bit Protection Register unique device identifier user programmable cells Extended Cycling Capability -Minimum 100,000 block erase cycles Software -Supported Intel's Advanced Flash File Managers Intel® VFM, Intel® FDI, etc. -Code data storage same memory device -Robust Power Loss Recovery Data Loss Prevention -Common Flash Interface Standard Surface Mount Packaging -48-Ball µBGA*/VFBGA -64-Ball Easy packages -48-TSOP package ETOXVIII (0.13 Flash Technology Mbit ETOXVII (0.18 Flash Technology -16, Mbit ETOXVI (0.25 Flash Technology Mbit
Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured Intel's latest 0.13 0.18 technologies, represents feature-rich solution low-power applications. device incorporates low-voltage capability read, program, erase) with high-speed, low-power operation. Flexible block locking allows block independently locked unlocked. this Intel® Flash Data Integrator (Intel® FDI) software have cost-effective, flexible, monolithic code plus data storage solution. Intel® Advanced+ Boot Block Flash Memory (C3) products available 48-lead TSOP, 48ball CSP, 64-ball Easy packages. Additional information this product family obtained from Intel® Flash website:
Order Number: 290645, Revision: 2005
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2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Contents
Introduction.7 Nomenclature Conventions
Functional Overview Product Overview Block Diagram Memory
Package Information mBGA* Package.12 TSOP Package Easy Package
Ballout Signal Descriptions 48-Lead TSOP Package 64-Ball Easy Package Signal Descriptions
Maximum Ratings Operating Conditions. Absolute Maximum Ratings Operating Conditions
Electrical Specifications Current Characteristics Voltage Characteristics.24
Characteristics Read Characteristics Write Characteristics. Erase Program Timings Test Conditions Device Capacitance
Power Reset Specifications Active Power (Program/Erase/Read). Automatic Power Savings (APS) Standby Power Deep Power-Down Mode. Power Reset Considerations 8.5.1 Power-Up/Down Characteristics 8.5.2 Connected System Reset 8.5.3 VCC, Transitions 8.5.4 Reset Specifications Power Supply Decoupling.
Device Operations
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Operations 9.1.1 Read 9.1.2 Write 9.1.3 Output Disable 9.1.4 Standby. 9.1.5 Reset
10.0 Modes Operation. 10.1 Read Mode 10.1.1 Read Array. 10.1.2 Read Identifier 10.1.3 Query 10.1.4 Read Status Register. 10.1.4.1 Clear Status Register. Program Mode 10.2.1 12-Volt Production Programming. 10.2.2 Suspending Resuming Program. Erase Mode 10.3.1 Suspending Resuming Erase
10.2
10.3
11.0 Security Modes Flexible Block Locking 11.1.1 Locking Operation. 11.1.1.1 Locked State 11.1.1.2 Unlocked State. 11.1.1.3 Lock-Down State. 11.2 Reading Block-Lock Status. 11.3 Locking Operations during Erase Suspend 11.4 Status Register Error Checking 11.5 128-Bit Protection Register. 11.5.1 Reading Protection Register. 11.5.2 Programming Protection Register. 11.5.3 Locking Protection Register. 11.6 Program Erase Voltages 11.6.1 Program Protection. Write State Machine States. Flow Charts Common Flash Interface. Query Structure Output. Query Structure Overview Block Status Register Query Identification String. Device Geometry Definition Intel-Specific Extended Query Table Additional Information Ordering Information. 11.1
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Revision History
Date Revision 05/12/98 Version -001 Original version 48-Lead TSOP package diagram change µBGA package diagrams change 32-Mbit ordering information change (Section Query Structure Output Table Change (Table Primary-Vendor Specific Extended Query Table Change Optional Features Command Support change (Table Protection Register Address Change IPPD test conditions clarification (Section 4.3) µBGA package side mark information clarification (Section Byte-Wide Protection Register Address change Specification change (Section 4.3) Maximum Specification change (Section 4.3) ICCS test conditions clarification (Section 4.3) Added Command Sequence Error Note (Table Datasheet renamed from Volt Advanced Boot Block, 16-, 32-Mbit Flash Memory Family. Added tBHWH /tBHEH tQVBL (Section 4.6) Programming Protection Register clarification (Section 3.4.2) Removed references configurations Removed reference 40-Lead TSOP from front page Added Easy package (Section 1.2) Removed references Locking Operations Flowchart changed (Appendix Added tWHGL (Section 4.6) Primary Vendor-Specific Extended Query changed (Appendix ICCD changed Table added note indicating VCCMax 32-Mbit device Added specifications 0.18 micron product offerings throughout document Added 64Mbit density Changed references 32Mbit 80ns devices 70ns devices reflect faster product offering. 10/12/00 -010 Changed VccMax=3.3V reference indicate that affected product 0.25µm 32Mbit device. Minor text edits throughout document. Added 1.8v operation documentation where applicable Added TSOP `Pin-1' indicator information Changed references pinout diagrams from `GND' `Vssq' 7/20/01 -011 Added `Vssq' Descriptions Information Removed references characteristics table Corrected 64Mb package Ordering Information from 48-uBGA 48-VFBGA Corrected `bottom' parameter block sizes device 4KWords Minor text edits throughout document 10/02/01 2/05/02 -012 -013 Added specifications 0.13 micron product offerings throughout document Corrected Iccw Ippw Icces /Ippes values. Added mechanicals 16Mb 64Mb Minor text edits throughout document. Description
07/21/98
-002
10/03/98
-003
12/04/98 12/31/98 02/24/99
-004 -005 -006
06/10/99
-007
03/20/00 04/24/00
-008 -009
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Date Revision
Version Updated 64Mb product offerings. Updated 16Mb product offerings.
Description
4/05/02
-014
Revised corrected Characteristics Table. Added mechanicals Easy BGA. Minor text edits throughout document.
3/06/03 10/01/03 5/20/04 9/1/04 9/14/04 9/27/04 1/26/05
-016 -017 -018 -019 -020 -021 -022
Complete technical update. Corrected information Device Geometry Details table, address 0x34. Updated layout datasheet. Fixed typo Standby power cover page. Added lead-free line items Table "Product Information Ordering Matrix" page Added specification 0.13 micron device. Added 0.13 micron Table "Product Information Ordering Matrix" page Converted datasheet template. Deleted Description Table Deleted Note Figure Removed ordering information, removed ordering information. Removed reference title page only. Added software verbiage title page. Corrected Lead Width measurement uBGA Package Drawing Dimensions, page
5/16/05
-023
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Introduction
This datasheet contains specifications Intel® Advanced+ Boot Block Flash Memory (C3) device family, hereafter called flash memory device. These flash memories features such instant block locking protection registers that used enhance security systems.
Nomenclature
Byte Word Kword Mword Hexadecimal prefix Binary prefix bits bits 1024 words 1,048,576 words 1024 bits 1024 bytes 1,048,576 bits 1,048,576 bytes Automatic Power Savings Chip Scale Package Command User Interface Time Programmable Protection Register Protection Register Data Protection Lock Register Reserved Future Status Register Status Register Data Write State Machine
Conventions
terms signal often used interchangeably refer external signal connections package; chip scale package (CSP) term ball used. Group Membership Brackets: Square brackets will used designate group membership define group signals with similar function (i.e. A[21:1], SR[4:1]) Set: When referring registers, term means logical Clear: When referring registers, term clear means logical Block: group bits words) that erase simultaneously with block erase instruction. Main Block: block that contains Kwords. Parameter Block: block that contains Kwords.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Functional Overview
This section provides overview Intel® Advanced+ Boot Block Flash Memory (C3) device features architecture.
Product Overview
flash memory device provides high-performance asynchronous reads packagecompatible densities with data bus. Individually-erasable memory blocks optimally sized code data storage. Eight Kword parameter blocks located boot block either bottom device's memory map. rest memory array grouped into Kword main blocks. device supports read-array mode operations various voltages (1.8 erase program operations VPP. With option, tied together simple, ultra-low-power design. addition voltage flexibility, dedicated input provides complete data protection when VPPLK. Intel® Advanced+ Boot Block Flash Memory (C3) device features 128-bit protection register enabling security techniques data protection schemes through combination factory-programmed user-programmable data registers. Zero-latency locking/unlocking memory block provides instant complete protection critical system code data. Additional block lock-down capability provides hardware protection where software commands alone cannot change block's protection status. command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence issued initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. device offers three low-power saving features: Automatic Power Savings (APS), standby mode, deep power-down mode. device automatically enters mode following read cycle completion. Standby mode begins when system deselects flash memory deasserting Chip Enable, CE#. deep power-down mode begins when Reset Deep PowerDown, asserted, which deselects memory places outputs high-impedance state, producing ultra-low power savings. Combined, these three power-savings features significantly enhanced power consumption flexibility.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
Block Diagram
Flash Memory Device Block Diagram
0-DQ15
VCCQ Output Buffer Input Buffer
Outp ulti
Status Register
ster
Identifier Register
Logic
Power Reduction Control
Data Comparator
Command User Interface
A[MAX:MIN]
Y-Decoder Input Buffer -KWor Para mete
Y-Gating/Sensing -KWor Para mete KWord
Write State Machine KWord
Program/Erase Voltage Switch
Address Latch
X-Decoder
Address Counter
Memory
Intel® Advanced+ Boot Block Flash Memory (C3) device asymmetrically blocked, which enables system code data integration within single flash device. bulk array divided into Kword main blocks that store code data, Kword boot blocks facilitate storage boot code frequently changing small parameters. Table "Top Boot Memory Map" page Table "Bottom Boot Memory Map" page details.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Size (KW)
Boot Memory
8-Mbit Memory Addressing (Hex) 7F0007FFFF 7E0007EFFF 7D0007DFFF 7C0007CFFF 7B0007BFFF 7A0007AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 10000-17FFF 8000-0FFFF 0000-07FFF Size (KW) 16-Mbit Memory Addressing (Hex) FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) 32-Mbit Memory Addressing (Hex) 1FF0001FFFFF 1FE0001FEFFF 1FD0001FDFFF 1FC0001FCFFF 1FB0001FBFFF 1FA0001FAFFF 1F90001F9FFF 1F80001F8FFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) 64-Mbit Memory Addressing (Hex)
3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 10000-17FFF 08000-0FFFF 00000-07FFF
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Size (KW)
Bottom Boot Memory
8-Mbit Memory Addressing (Hex) 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 16-Mbit Memory Addressing (Hex) F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32-Mbit Memory Addressing (Hex) 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 64-Mbit Memory Addressing (Hex) 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
Package Information
µBGA* Package
µBGA* Package Drawing Dimensions
Discrete 8/16/32/64M, .25,.18, .13u ubga/VFBGA
Ball Corner
Ball Corner
View Bump Side down
Bottom View -Bump side
Seating Plan
Note: Drawing scale
Side View
Dimensions Symbol Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length (.25) Package Body Length (.25/.18/.13) (.25/.18/.13) Package Body Length (.18) Package Body Width (.25) Package Body Width (.25/.18/.13) (.18/.13) Package Body Width (.25) Package Body Width (.18) Pitch Ball (Lead) Count Ball (Lead) Count Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along (.25) Corner Ball Distance Along (.25/.18/.13) (.18/.13) Corner Ball Distance Along (.18) Corner Ball Distance Along (.25) Corner Ball Distance Along (.25/.18/.13) (.18/.13) Corner Ball Distance Along (.25) Corner Ball Distance Along (.18)
0.150 0.325 7.810 7.186 7.600 6.400 6.864 10.750 8.900
Millimeters 1.000 0.665 0.375 7.910 7.286 7.700 6.500 6.964 10.850 9.000 0.750 1.330 1.018 1.225 1.375 1.607 3.550 2.625
0.0059
Inches
0.0394
0.425 8.010 7.386 7.800 6.600 7.064 10.860 9.100
0.0128 0.2829 0.2992 0.2520 0.2702 0.4232 0.3504
0.0262 0.0148 0.2868 0.3031 0.2559 0.2742 0.4272 0.3543 0.0295 0.0524 0.0401 0.0482 0.0541 0.0633 0.1398 0.1033
0.0167 0.2908 0.3071 0.2598 0.2781 0.4276 0.3583
1.230 0.918 1.125 1.275 1.507 3.450 2.525
0.100 1.430 1.118 1.325 1.475 1.707 3.650 2.725
0.0484 0.0361 0.0443 0.0502 0.0593 0.1358 0.0994
0.0039 0.0563 0.0440 0.0522 0.0581 0.0672 0.1437 0.1073
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
TSOP Package
TSOP Package Drawing Dimensions
Notes
Detail
Seating Plane
Detail
A5568-
Dimensions
Family: Thin Small -Line Package Symbol Package Height Standoff Package Body Thickness Lead Width Lead Thickness Plastic Body Length Package Body Width Lead Pitch Terminal Dimension Lead Length Lead Count Lead Angle Seating Plane Coplanarity Lead Package Offset 0.150 0.250 0.050 0.950 0.150 0.100 1.000 0.200 0.150 1.050 0.300 0.200 Millimeters 1.200 0.002 0.037 0.006 0.004 0.717 0.465 0.039 0.008 0.006 0.724 0.472 0.0197 0.780 0.020 0.787 0.024 0.100 0.350 0.006 0.010 0.004 0.014 0.795 0.028 0.041 0.012 0.008 0.732 0.480 Notes Inches 0.047 Notes
18.200 18.400 18.600 11.800 12.000 12.200 0.500 19.800 20.000 20.200 0.500 0.600 0.700
Notes: dimple package denotes dimples, then larger dimple denotes will always upper left corner package, reference product mark.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
Easy Package
Easy Package Drawing Dimension
Ball Corner Ball Corner
View Ball side down
Bottom View Ball Side
Seating Plane
Note: Drawing scale
Side View
Dimensions Table
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along Symbol Millimeters 0.250 0.330 9.900 12.900 0.780 0.430 10.000 13.000 1.000 1.500 3.000 0.530 10.100 13.100 1.200 Notes Inches 0.0098 0.0130 0.3898 0.5079 0.0307 0.0169 0.3937 0.5118 0.0394 0.0591 0.1181 0.0209 0.3976 0.5157 0.0472
1.400 2.900
0.100 1.600 3.100
0.0551 0.1142
0.0039 0.0630 0.1220
Note: Package dimensions reference only. These dimensions estimates based size, subject change.
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Ballout Signal Descriptions
device available 48-lead TSOP, 48-ball BGA, 48-ball µBGA, Easy packages. Figure page Figure page Figure page respectively.
Figure
48-Lead TSOP Package
48-Lead TSOP Package
Advanced+ Boot Block 48-Lead TSOP VIEW
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
Mark Pin-1 Indicator 48-Lead 8-Mb, 16-Mb 32-Mb TSOP
Current ark:
ark:
Note:
topside marking Intel Advanced Advanced Boot Block TSOP products will convert white triangle indicator. Products without white triangle will continue dimple indicator. There other changes package size, materials, functionality, customer handling, manufacturability. Product will continue meet Intel stringent quality requirements. Products affected Intel Ordering Codes shown Table 48-Lead TSOP
Extended Mbit Extended Mbit Extended Mbit Extended
Table
TE28F320C3TD70 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110
TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
48-Ball µBGA* 48-Ball Chip Scale Package (Top View, Ball Down)1,2,3
VCCQ
Notes: Shaded connections indicate upgrade address connections. Intel recommends routing this area. denotes Mbit; denotes Mbit; denotes Mbit. Unused address balls populated.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure
64-Ball Easy Package
64-Ball Easy Package1,2
A19(1) A20(1) A21(1) DQ11 A22(2) VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ VCCQ A22(2) VSSQ VSSQ DQ14 DQ10 A21(1) A20(1) A19(1)
View Ball Side Down
Bottom View Ball Side
Notes: 1.A19 denotes Mbit; denotes Mbit; denotes Mbit. Unused address balls populated.
Table
Symbol
Signal Descriptions
Signal Descriptions
Type Description ADDRESS INPUTS memory addresses. Address internally latched during program erase cycle.
A[MAX:0]
Input
Mbit: AMAX= Mbit: AMAX Mbit: AMAX Mbit: AMAX
DATA INPUTS/OUTPUTS: Inputs data commands during write cycle; outputs data during read cycles. Inputs commands Command User Interface when active. Data internally latched. data pins float tri-state when chip de-selected outputs disabled. CHIP ENABLE: Active-low input. Activates internal control logic, input buffers, decoders sense amplifiers. active low. high de-selects memory device reduces power consumption standby levels. OUTPUT ENABLE: Active-low input. Enables device's outputs through data buffers during Read operation.
DQ[15:0]
Input/ Output
Input
Input
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Symbol
Signal Descriptions
Type Description RESET/DEEP POWER-DOWN: Active-low input.
Input
When logic low, device reset/deep power-down mode, which drives outputs High-Z, resets Write State Machine, minimizes current levels (ICCD). When logic high, device standard operation. When transitions from logic-low logic-high, device resets blocks locked defaults read array mode.
WRITE ENABLE: Active-low input. controls writes device. Address data latched rising edge pulse. WRITE PROTECT: Active-low input.
Input
Input
When logic low, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software. When logic high, lock-down mechanism disabled blocks previously locked-down locked unlocked locked through software. After goes low, blocks previously marked lock-down revert lock-down state. Section 11.0, "Security Modes" page details block locking.
PROGRAM/ERASE Power Supply: Operates input logic levels control complete device protection. Supplies power accelerated Program Erase operations range. leave this floating. Lower VPPLK protect contents against Program Erase commands. in-system Read, Program Erase operations. this configuration, drop 1.65 allow resistor diode drop from system supply. Apply faster program erase production environment. Applying only done maximum 1000 cycles main blocks 2500 cycles boot blocks. connected total hours maximum. Section 11.6 details voltage configurations. DEVICE CORE Power Supply: Supplies power device operations. OUTPUT Power Supply: Output-driven source voltage. This ball tied directly operating within range. Ground: internal circuitry. ground inputs must connected. Use: this ball. This ball must connected power supplies, signals other balls,; must left floating. Connect
Input/ Power
VCCQ
Power Power Power
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Warning:
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These ratings stress ratings only. Operation beyond "Operating Conditions" recommended, extended exposure beyond "Operating Conditions" affect device reliability.
NOTICE: Specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Parameter
Maximum Rating
Notes
Extended Operating Temperature During Read During Block Erase Program Temperature under Bias Storage Temperature Voltage (except VPP) with Respect Voltage (for Block Erase Program) with Respect VCCQ Supply Voltage with Respect Output Short Circuit Current +125 -0.5 +3.7 -0.5 +13.5 -0.2 +3.6 1,2,3
Notes: 1.Minimum voltage -0.5 input/output pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins +0.5 which, during transitions, overshoot +2.0 periods 2.Maximum voltage overshoot +14.0 periods 3.VPP Program voltage normally 1.65 V-3.6 Connection 11.4 V-12.6 supply done maximum 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. connected total hours maximum. 4.Output shorted more than second. more than output shorted time.
Table
Operating Conditions
Temperature Voltage Operating Conditions
Symbol Parameter Notes Units
VCC1 VCC2 VCCQ1 VCCQ2 VCCQ3 VPP1
Operating Temperature Supply Voltage Supply Voltage
1.65
Volts
Volts
Supply Voltage
1.65
Volts
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Temperature Voltage Operating Conditions
Symbol Parameter Notes Units
VPP2 Cycling Block Erase Cycling
11.4 100,000
12.6
Volts Cycles
Notes: 1.VCC VCCQ must share same supply when they VCC1 range. 2.VCCMax 0.25µm 32-Mbit devices. 3.Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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Intel® Advanced+ Boot Block Flash Memory (C3)
Electrical Specifications
Current Characteristics
Table
Current Characteristics (Sheet
V-3.6 V-3.6 V-2.85 1.65 V-2.5 V-3.3 V-2.5 Unit Test Conditions
Parameter
VCCQ Note
Input Load Current
VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ during Program/ Erase Suspend VCCQ
Output Leakage Current Standby Current 0.13 0.18 Micron Product
ICCS
Standby Current 0.25 Micron Product Power-Down Current 0.13 0.18 Micron Product
ICCD
Power-Down Current 0.25 Product Read Current 0.13 0.18 Micron Product Read Current 0.25 Micron Product
VCCMax VCCQ VCCQMax VCCQ
1,2,3
ICCR
1,2,3
VCCMax VCCQ VCCQMax VIH, =VIL MHz, IOUT=0 Inputs =VPP1, Program Progress VPP2 (12v) Program Progress VPP1, Erase Progress VPP2 (12v) Erase Progress
IPPD
Deep PowerDown Current
ICCW
Program Current
ICCE
Erase Current
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Table
Current Characteristics (Sheet
V-3.6 V-3.6 V-2.85 1.65 V-2.5 V-3.3 V-2.5 Unit Test Conditions
Parameter
VCCQ Note
ICCES/ ICCWS
Erase Suspend Current 0.13 0.18 Micron Product 1,4,5 Erase Suspend Current 0.25 Micron Product Read Current
VIH, Erase Suspend Progress
0.05 0.05
0.05 0.05
=VPP1, Program Progress VPP2 (12v) Program Progress VPP1, Erase Progress VPP2 (12v) Erase Progress VPP1, Program Erase Suspend Progress VPP2 (12v) Program Erase Suspend Progress
IPPR
0.05
IPPW
Program Current
0.05
IPPE
Erase Current
IPPES/ IPPWS Erase Suspend Current
Notes: 1.All currents unless otherwise noted. Typical values nominal VCC, 2.The test conditions VCCMax, VCCQMax, VCCMin, VCCQMin refer maximum minimum VCCQ voltage listed each column. VCCMax 0.25µm 32-Mbit devices. 3.Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation (CMOS inputs). 4.Sampled, 100% tested. 5.ICCES ICCWS specified with device de-selected. device read while erase suspend, current draw ICCES ICCR. device read while program suspend, current draw ICCWS ICCR.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Voltage Characteristics
Voltage Characteristics
V-3.6 V-3.6 V-2.85 1.65 V-2.5 V-3.3 V-2.5 Unit Test Conditions
Parameter
VCCQ Note
Input Voltage Input High Voltage Output Voltage Output High Voltage LockOut Voltage during Program Erase Operations Prog/ Erase Lock Voltage VCCQ Prog/ Erase Lock Voltage
-0.4
0.22 VCCQ +0.3V
-0.4 VCCQ 0.4V -0.1
VCCQ +0.3V
-0.4 VCCQ 0.4V -0.1
VCCQ +0.3V
VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100 Complete Write Protection
-0.1
VPPLK VPP1 VPP2
VCCQ -0.1V 1.65 11.4 12.6
VCCQ 0.1V 1.65 11.4 12.6
VCCQ 0.1V 1.65 11.4 12.6
VLKO
VLKO2
Notes: Erase Program inhibited when VPPLK guaranteed outside valid ranges VPP1 VPP2. 2.Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum.
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Table
Characteristics
Read Characteristics
Read Operations-8-Mbit Density
Density Product (ns) (ns) (ns) (ns) (ns) (ns) Mbit (ns) (ns) (ns) (ns)
Parameter
Note
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First
1,3,4 1,3,4 2,3,4 2,3,4 2,3,4 2,3,4
2,3,4
Notes: 1.OE# delayed tELQV-tGLQV after falling edge without impact tELQV. 2.Sampled, 100% tested. 3.See Figure "Read Operation Waveform" page 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
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Table
Read Operations-16-Mbit Density
Density Product Mbit
V-3.6 (ns) (ns)
V-3.6 (ns) (ns)
V-3.6 (ns) (ns) V-3.6 (ns) (ns)
V-3.6V (ns) (ns) V-3.6V (ns) (ns)
Notes
Parameter
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First
1,3,4 1,3,4 2,3,4 2,3,4 2,3,4 2,3,4
2,3,4
Notes: 1.OE# delayed tELQV-tGLQV after falling edge without impact tELQV. 2.Sampled, 100% tested. 3.See Figure "Read Operation Waveform" page Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
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Table
Read Operations-32-Mbit Density
Density Product Mbit
V-3.6 (ns) (ns)
V-3.6 (ns) (ns)
V-3.3 (ns) (ns) V-3.3 (ns) (ns)
V-3.3 (ns) (ns) V-3.3 (ns) (ns)
Notes
Parameter
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First
1,3,4 1,3,4 2,3,4 2,3,4 2,3,4 2,3,4
2,3,4
Notes: 1.OE# delayed tELQV-tGLQV after falling edge without impact tELQV. 2.Sampled, 100% tested. 3.See Figure "Read Operation Waveform" page Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Read Operations 64-Mbit Density
Density Product Parameter Note V-3.6 V-3.6 Mbit Unit
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First
1,3,4 1,3,4 2,3,4 2,3,4 2,3,4 2,3,4 2,3,4
Notes: 1.OE# delayed tELQV-tGLQV after falling edge without impact tELQV. 2.Sampled, 100% tested. 3.See Figure "Read Operation Waveform" page 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
Figure
Read Operation Waveform
Address Data [D/Q] RST#
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Table
Write Characteristics
Write Operations-8-Mbit Density
Density Product Parameter Note (ns) (ns) (ns) (ns) (ns) 70ns Mbit
tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL
High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going
2,4,5 2,4,5 2,4,5 2,4,5 2,4,5 3,4,5
Notes: 1.Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. 2.Refer Table "Command Operations" page valid DIN. 3.Sampled, 100% tested. 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. 5.See Figure "Write Operations Waveform" page
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Table
Write Operations-16-Mbit Density
Density Product Mbit Unit
Parameter
Note
tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL
High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going
1,4,5 2,4,5 2,4,5 2,4,5 2,4,5 1,4,5 3,4,5
Notes: 1.Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. 2.Refer Table "Command Operations" page valid DIN. 3.Sampled, 100% tested. 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. 5.See Figure "Write Operations Waveform" page
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Table
Write Operations-32-Mbit Density
Density Product Mbit Unit
Parameter
Note
tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL
High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width
1,4,5
Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going
2,4,5 2,4,5 2,4,5 2,4,5 1,4,5 3,4,5
Notes: 1.Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. 2.Refer Table "Command Operations" page valid DIN. 3.Sampled, 100% tested. 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. 5.See Figure "Write Operations Waveform" page 6.VCCMax 32-Mbit 0.25 Micron product.
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Table
Write Operations-64-Mbit Density
Density Mbit Note Unit
Symbol
Parameter
Product
tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL
High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going
1,4,5 2,4,5 2,4,5 2,4,5 2,4,5 1,4,5 3,4,5
Notes: 1.Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. 2.Refer Table "Command Operations" page valid DIN. 3.Sampled, 100% tested. 4.See Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. 5.See Figure "Write Operations Waveform" page
Figure
Write Operations Waveform
Address Data [D/Q]
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Table
Erase Program Timings
Erase Program Timings
Symbol Parameter Note 1.65 V-3.6 11.4 V-12.6 Unit
tBWPB tBWMB
4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time 0.13 0.18 Micron Product
0.10
0.30
0.03 0.24
0.12
tWHQV1 tEHQV1
Word Program Time 0.25 Micron Product 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency
tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHRH1 tEHRH1 tWHRH2 tEHRH2
Notes: 1.Typical values measured nominal voltages. 2.Excludes external system-level overhead. 3.Sampled, 100% tested.
Figure
Test Conditions
Input/Output Reference Waveform
VCCQ Input
Note:
VCCQ/2
Test Points
VCCQ/2
Output
Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst-case speed conditions when VCCMin.
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Figure
Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
Note:
Table component values.
Table
Test Configuration Component Values Worst-Case Speed Conditions
Test Configuration (pF)
VCCQMin Standard Test
Note:
includes capacitance.
Device Capacitance
Table
Device Capacitance
Symbol Unit Condition
COUT
Input Capacitance Output Capacitance
VOUT
Sampled, 100% tested.
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Power Reset Specifications
Intel® flash devices have tiered approach power savings that significantly reduce overall system power consumption. Automatic Power Savings (APS) feature reduces power consumption when device selected idle. deasserted, flash enters standby mode, where current consumption even lower. deasserted, flash enter deep powerdown mode ultra-low current consumption. combination these features minimize memory power consumption, therefore, overall system power consumption.
Active Power (Program/Erase/Read)
With logic-low level logic-high level, device active mode. Refer Characteristic tables current values. Active power largest contributor overall system power consumption. Minimizing active current could have profound effect system power consumption, especially battery-operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data read from memory array address lines idle, circuitry places device mode where typical current comparable ICCS. flash stays this static state with outputs valid until location read.
Standby Power
When logic-high level (VIH), flash memory standby mode, which disables much device's circuitry substantially reduces power consumption. Outputs placed high-impedance state independent status signal. transitions logichigh level during Erase Program operations, device will continue perform operation consume corresponding active power until operation completed. System engineers should analyze breakdown standby time versus active time quantify respective power consumption each mode their specific application. This approach will provide more accurate measure application-specific power energy requirements.
Deep Power-Down Mode
deep power-down mode activated when VIL. During read modes, going deselects memory places outputs high-impedance state. Recovery from deep powerdown requires minimum time tPHQV read operations, tPHWL/tPHEL write operations. During program erase modes, transitioning aborts in-progress operation. memory contents address being programmed block being erased longer valid data integrity been compromised abort. During deep power-down, internal circuits switched low-power savings mode (RP# transitioning turning power device clears Status Register).
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8.5.1
Power Reset Considerations
Power-Up/Down Characteristics
prevent condition that result spurious write erase operation, Intel recommends power-up VCCQ together. Conversely, VCCQ must power-down together. Intel also recommends that power-up with after reached VCCmin. Conversely, must powerdown with slightly before VCC. VCCQ and/or connected supply, then must attain VCCmin before applying VCCQ VPP. Device inputs must driven before supply voltage reaches VCCmin. Power supply transitions must only occur when low.
8.5.2
Connected System Reset
during system reset important with automated program/erase devices since system reads from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. Intel recommends connecting system RESET# signal allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when voltages above VLKO. Because both must command write, driving either signal will inhibit writes device. architecture provides additional protection since alteration memory contents only occur after successful completion two-step command sequences. device also disabled until brought VIH, regardless state control inputs. holding device reset during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
8.5.3
VCC, Transitions
latches commands issued system software altered transitions actions. default state upon power-up, after exit from reset mode after transitions above VLKO (Lockout voltage), read-array mode. After program Block-Erase operation complete (even after transitions down VPPLK), must reset read-array mode Read Array command access flash-memory array desired.
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8.5.4
Table
Reset Specifications
Reset Specifications
Symbol Parameter Unit Notes
tPLPH tPLRH1 tPLRH2
Reset during Read tied VCC, this specification applicable) Reset during Block Erase Reset during Program
Notes: 1.If tPLPH device still reset this guaranteed. 2.If asserted while Block Erase Word Program operation executing, reset will complete within 3.Sampled, 100% tested.
Figure
Reset Operations Waveforms
PLPH Reset during Read Mode
PHQV PHWL PHEL
Abort Complete
PLRH
PHQV PHWL PHEL
PLPH Reset during Program Block Erase, PLPH PLRH
Abort Deep Complete PowerDown
PLRH
PHQV PHWL PHEL
PLPH
Reset Program Block Erase, PLPH PLRH
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers should consider following three supply current issues:
Standby current levels (ICCS) Read current levels (ICCR) Transient peaks produced falling rising edges CE#.
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Transient current magnitudes depend device outputs' capacitive inductive loading. Twoline control proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have ceramic capacitor connected between each GND, between VSS. These high-frequency, inherently low-inductance capacitors should placed close possible package leads.
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Device Operations
Intel® Advanced+ Boot Block Flash Memory (C3) device uses automated algorithms simplify Program Erase operations. allows 100% CMOS-level control inputs fixed power supplies during erasure programming. internal completely automates Program Erase operations while signals start operation Status Register reports device status. handles interface data address latches well system status requests during operation.
Operations
Intel® Advanced+ Boot Block Flash Memory (C3) device performs read, program, erase operations in-system through local microcontroller. Four control pins (CE#, OE#, WE#, RP#) manage data flow flash device. Table page summarizes these operations.
Table
Operations
Mode DQ[15:0]
Read Write Output Disable Standby Reset
Note:
Don't Care (VIL VIH)
DOUT High-Z High-Z High-Z
9.1.1
Read
When performing read cycle, must asserted; must deasserted. device selection control; when active low, enables flash memory device. data output control; when low, data output DQ[15:0]. Figure "Read Operation Waveform" page
9.1.2
Write
write cycle occurs when both low; high. Commands issued Command User Interface (CUI). does occupy addressable memory location. Address data latched rising edge pulse, whichever occurs first. Figure "Write Operations Waveform" page
9.1.3
Output Disable
With logic-high level (VIH), device outputs disabled. DQ[15:0] placed high-impedance state.
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9.1.4
Standby
Deselecting device bringing logic-high level (VIH) places device standby mode, which substantially reduces device power consumption without latency subsequent read accesses. standby, outputs placed high-impedance state independent OE#. deselected during Program Erase operation, device continues consume active power until Program Erase operation complete.
9.1.5
Reset
From read mode, time tPLPH deselects memory, places output drivers highimpedance state, turns internal circuits. After return from reset, time tPHQV required until initial read-access outputs valid. delay (tPHWL tPHEL) required after return from reset before write cycle initiated. After this wake-up interval, normal operation restored. resets read-array mode, Status Register 0x80, blocks locked. Figure "Reset Operations Waveforms" page taken time tPLPH during Program Erase operation, operation will aborted; memory contents aborted location (for program) block (for erase) longer valid, since data partially erased written. abort process goes through following sequence: When goes low, device shuts down operation progress, process which takes time tPLRH complete. After time tPLRH, part will either reset read-array mode asserted during tPLRH) enter reset mode deasserted after tPLRH). Figure "Reset Operations Waveforms" page both cases, after returning from aborted operation, relevant time tPHQV tPHWL/tPHEL must observed before Read Write operation initiated, discussed previous paragraph. However, this case, these delays referenced tPLRH rather than when goes high. with automated device, important assert during system reset. When system comes reset, processor reads from flash memory. Automated flash memories provide status information when read during Program Block-Erase operations. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel® flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
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10.0
10.1
Modes Operation
Read Mode
flash memory four read modes (read array, read identifier, read status, query) write modes (program erase). Three additional modes (erase suspend program, erase suspend read, program suspend read) available only during suspended operations. Table "Command Operations" page Table "Command Codes Descriptions" page summarize commands used these modes. Appendix "Write State Machine States" page comprehensive chart showing state transitions.
10.1.1
Read Array
When transitions from (reset) VIH, device defaults read-array mode will respond read-control inputs (CE#, address inputs, OE#) without additional commands. When device read array mode, four control signals control data output.
must logic high (VIH) must logic (VIL) must logic (VIL) must logic high (VIH)
addition, address desired location must applied address pins. device read-array mode, would case after Program Erase operation, Read Array command (0xFF) must issued before array reads occur.
10.1.2
Read Identifier
read-identifier mode outputs three types information: manufacturer/device identifier, block locking status, protection register. device switched this mode issuing Read Identifier command (0x90). Once this mode, read cycles from addresses shown Table retrieve specified information. return read-array mode, issue Read Array command (0xFF).
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Table
Device Identification Codes
Address1 Item Base Offset Data Description
Manufacturer
Block
0x00
0x0089 0x88C0 0x88C1 0x88C2 8-Mbit Boot Device 8-Mbit Bottom Boot Device 16-Mbit Boot Device 16-Mbit Bottom Boot Device 32-Mbit Boot Device 32-Mbit Bottom Boot Device 64-Mbit Boot Device 64-Mbit Bottom Boot Device Block unlocked Block locked Block locked-down Block locked down
Device
Block
0x01
0x88C3 0x88C4 0x88C5 0x88CC 0x88CD
Block Lock Status2
Block
0x02
Lock Data Register Data
Block Lock-Down Status2 Protection Register Lock Status Protection Register
Block Block Block
0x02 0x80 0x81 0x88
Multiple reads required read entire 128-bit Protection Register.
Notes: 1.The address constructed from base address plus offset. example, read Block Lock Status block number bottom boot device, address 0x0F8000 plus offset (0x02), i.e. 0x0F8002. Then examine data determine block locked. 2.See Section 11.2, "Reading Block-Lock Status" page valid lock status.
10.1.3
Query
query mode outputs Common Flash Interface (CFI) data after issuing Read Query Command (0x98). data structure contains information such block size, density, command set, electrical specifications. Once this mode, read cycles from addresses shown Appendix "Common Flash Interface," retrieve specified information. return read-array mode, issue Read Array command (0xFF).
10.1.4
Read Status Register
Status Register indicates status device operations success/failure that operation. Read Status Register (0x70) command causes subsequent reads output data from Status Register until another command issued. return reading from array, issue Read Array (0xFF) command. Status Register bits output DQ[7:0]. upper byte, DQ[15:8], outputs 0x00 when Read Status Register command issued.
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contents Status Register latched falling edge (whichever occurs last) which prevents possible errors that might occur Status Register contents change while being read. must toggled with each subsequent status read, Status Register will indicate completion Program Erase operation. When active, SR[7] will indicate status WSM; remaining bits Status Register indicate whether successful performing preferred operation Table "Status Register Definition" page
10.1.4.1
Clear Status Register
Status Register bits through clear bits cannot clear Status Register bits Because bits indicate various error conditions, these bits cleared only through Clear Status Register (0x50) command. allowing system software control resetting these bits, several operations performed (such cumulatively programming several addresses erasing multiple blocks sequence) before reading Status Register determine error occurred during that series. Clear Status Register before beginning another command sequence. Read Array command must issued before data read from memory array. Resetting device also clears Status Register.
10.2
Program Mode
Programming executed using two-write cycle sequence. Program Setup command (0x40) issued CUI, followed second write that specifies address data programmed. will execute sequence internally timed events program preferred bits addressed location, then verify bits sufficiently programmed. Programming memory results specific bits within address location being changed "0." users attempt program "1"s, memory cell contents change error occurs. Status Register indicates programming status. While program sequence executes, status "0." Status Register polled toggling either OE#. While programming, only valid commands Read Status Register, Program Suspend, Program Resume. When programming complete, program-status bits must checked. programming operation unsuccessful, SR[4] indicate program failure. SR[3] set, then within acceptable limits, execute program command. SR[1] set, program operation attempted locked block operation aborted. Status Register should cleared before attempting next operation. instruction follow after programming completed; however, prevent inadvertent Status Register reads, sure reset read-array mode.
10.2.1
12-Volt Production Programming
When between 1.65 program erase current drawn through pin.
Note:
driven logic signal, 1.65 That must remain above 1.65 perform in-system flash modifications.
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When connected power supply, device draws program erase current directly from pin. This eliminates need external switching transistor control VPP. Figure page shows examples flash power supplies configured various usage models. mode enhances programming performance during short period time typically found manufacturing processes; however, intended extended use. apply during Program Erase operations maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Stressing device beyond these limits cause permanent damage.
10.2.2
Suspending Resuming Program
Program Suspend command halts in-progress program operation that data read from other locations memory. Once programming process starts, issuing Program Suspend command requests that suspend program sequence predetermined points program algorithm. device continues output Status Register data after Program Suspend command issued. Polling SR[7] SR[2] will determine when program operation been suspended (both will "1"). program-suspend latency specified with tWHRH1/tEHRH1. Read-Array command issued read data from blocks other than that which suspended. only other valid commands while program suspended Read Status Register, Read Identifier, Query, Program Resume. After Program Resume command issued flash memory, will continue with programming process SR[2] SR[7] will automatically cleared. device automatically outputs Status Register data when read (see Figure "Program Suspend Resume Flowchart" page after Program Resume command issued. must remain same level used program while program-suspend mode. must also remain VIH.
10.3
Erase Mode
erase block, issue Erase Set-up Erase Confirm commands CUI, along with address identifying block erased. This address latched internally when Erase Confirm command issued. Block erasure results bits within block being "1." Only block erased time. will execute sequence internally timed events program bits within block "0," erase bits within block "1," then verify that bits within block sufficiently erased. While erase executes, status "0." When Status Register indicates that erasure complete, check erase-status verify that Erase operation successful. Erase operation unsuccessful, SR[5] Status Register will "1," indicating erase failure. within acceptable limits after Erase Confirm command issued, will execute erase sequence; instead, SR[5] Status Register indicate erase error, SR[3] identify that supply voltage within acceptable limits. After Erase operation, clear Status Register (0x50) before attempting next operation. instruction follow after erasure completed; however, prevent inadvertent statusregister reads, Intel recommends that place flash read-array mode after erase complete.
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10.3.1
Suspending Resuming Erase
Since Erase operation requires order seconds complete, Erase Suspend command provided allow erase-sequence interruption read data from-or program data another block memory. Once erase sequence started, issuing Erase Suspend command suspends erase sequence predetermined point erase algorithm. Status Register indicates if/when Erase operation been suspended. Erase-suspend latency specified tWHRH2/tEHRH2. Read Array Program command issued read/program data from/to blocks other than that which suspended. This nested Program command subsequently suspended read another location. only valid commands while Erase suspended Read Status Register, Read Identifier, Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block, Lock-Down Block. During erase-suspend mode, device placed pseudo-standby mode taking VIH, which reduces active current consumption. Erase Resume continues erase sequence when VIL. Similar standard Erase operation, Status Register must read cleared before next instruction issued.
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Table
Command Operations
First Cycle Command Notes Oper Addr Data Oper Addr Data Second Cycle
Read Array Read Identifier Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program
Write Write Write Write Write Write Write Write Write Write Write Write Write
0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0x20 0xB0 0xD0 0x60 0x60 0x60 0xC0 Write Write Write Write 0x01 0xD0 0x2F Write Write Read Read Read
"Don't Care" Status Reg. Data
Prog Addr Prog Data
Block Addr
Identifier Addr. Identifier Data
Query Addr. Query Data
Notes: 1.Following Read Identifier Query commands, read operations output device identification data query information, respectively. Section 10.1.2 Section 10.1.3. 2.Either 0x40 0x10 command valid, Intel standard 0x40. 3.When writing commands, upper data [DQ8-DQ15] should either VIH, minimize current draw.
operations defined Table "Bus Operations" page
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Table
Code (HEX)
Command Codes Descriptions
Device Mode Command Description
Read Array
This command places device read-array mode, which outputs array data data pins. This two-cycle command. first cycle prepares program operation. second cycle latches addresses data information initiates execute Program algorithm. flash outputs Status Register data when toggled. Read Array command required after programming read array data. Section 10.2, "Program Mode" page This two-cycle command. prepares Erase Confirm command. next command Erase Confirm command, then will both SR.4 SR.5 "1," place device into read-Status Register mode, wait another command. Section 10.3, "Erase Mode" page previous command Erase Set-Up command, then will close address data latches begin erasing block indicated address pins. During program/erase, device will respond only Read Status Register, Program Suspend Erase Suspend commands, will output Status Register data when toggled. Program Erase operation previously suspended, this command will resume that operation. previous command Block Unlock Set-Up, will latch address unlock block indicated address pins. block been previously Lock-Down, this operation will have effect. (See Section 11.1) Issuing this command will begin suspend currently executing Program/Erase operation. Status Register will indicate when operation been successfully suspended setting either program-suspend SR[2] erase-suspend SR[6] status SR[7] (ready). will continue idle SUSPEND state, regardless state inputcontrol pins except RP#, which will immediately shut down remainder chip driven VIL. Sections 3.2.5.1 3.2.6.1. This command places device into read-Status Register mode. Reading device will output contents Status Register, regardless address presented device. device automatically enters this mode after Program Erase operation been initiated. Section 10.1.4, "Read Status Register" page block-lock status SR[1], Status SR[3], program status SR[4], erasestatus SR[5] bits Status Register "1," cannot clear them "0." Issuing this command clears those bits "0." This command puts device into read-identifier mode that reading device will output manufacturer/device codes block-lock status. Section 10.1.2, "Read Identifier" page This command prepares block-locking changes. next command Block Unlock, Block Lock, Block Lock-Down, then will both program erase-Status Register bits indicate command-sequence error. Section 11.0, "Security Modes" page previous command Lock Set-Up, will latch address lock block indicated address pins. (See Section 11.1) previous command Lock-Down Set-Up command, will latch address lock-down block indicated address pins. (See Section 11.1) This command puts device into CFI-Query mode that reading device will output Common Flash Interface information. Section 10.1.3 Appendix "Common Flash Interface". This two-cycle command. first cycle prepares program operation protection register. second cycle latches addresses data information initiates execute Protection Program algorithm protection register. flash outputs Status Register data when toggled. Read Array command required after programming read array data. Section 11.5. Operates same Program Set-up command. (See 0x40/Program Set-Up) Unassigned commands should used. Intel reserves right redefine these codes future functions.
Program Set-Up
Erase Set-Up
Erase Confirm Program/Erase Resume Unlock Block
Program Suspend Erase Suspend
Read Status Register Clear Status Register Read Identifier Block Lock, Block Unlock, Block Lock-Down Set-Up Lock-Block Lock-Down Query
Protection Program Set-Up Alt. Prog Set-Up Invalid/ Reserved
Note:
Appendix "Write State Machine States" mode transition information.
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Table
WSMS
Status Register Definition
VPPS
NOTES:
SR[7] WRITE STATE MACHINE STATUS (WSMS) Ready Busy SR[6] ERASE-SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed SR[5] ERASE STATUS (ES) Error Block Erase Successful Block Erase SR[4] PROGRAM STATUS (PS) Error Programming Successful Programming
Before checking program erase- status bits, check Write State Machine first determine Word Program Block Erase completion. When Erase Suspend issued, halts execution sets both WSMS bits "1." remains until Erase Resume command issued. When this "1," applied maximum number erase pulses block still unable verify successful block erasure. When this "1," attempted failed program word/byte. status does provide continuous indication level. interrogates level only after Program Erase command sequences have been entered informs system been switched also checked before operation verified WSM. status guaranteed report accurate feedback between VPPLK VPP1Min. When Program Suspend issued, halts execution sets both WSMS bits "1." remains until Program Resume command issued. Program Erase operation attempted locked blocks, this WSM. operation specified aborted device returned read status mode. This reserved future should masked when polling Status Register.
SR[3] STATUS (VPPS) Detect, Operation Abort
SR[2] PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR[1] BLOCK LOCK STATUS Prog/Erase attempted locked block; Operation aborted. operation locked blocks SR[0] RESERVED FUTURE ENHANCEMENTS
Note:
Command-Sequence Error indicated when SR[4], SR[5], SR[7] set.
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11.0
11.1
Security Modes
Flexible Block Locking
Intel® Advanced+ Boot Block Flash Memory (C3) device offers instant, individual blocklocking scheme that allows block locked unlocked with latency, enabling instant code data protection. This locking scheme offers levels protection. first level allows software-only control block locking (useful data blocks that change frequently), while second level requires hardware interaction before locking changed (useful code blocks that change infrequently). following sections will discuss operation locking system. term "state [abc]" will used specify locking states; example, "state [001]," where value WP#, Block Lock Status Register, Block Lock Status Register. Figure "Block Locking State Diagram" page displays possible locking states.
Figure
Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
Notes:
[a,b,c] represents [WP#, D0]. Don't Care. indicates block Lock-down status. `0', Lock-down been issued this block. `1', Lock-down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
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11.1.1
Locking Operation
locking status each block Locked, Unlocked, Lock-Down, each which will described following sections. Figure "Block Locking State Diagram" page Figure "Locking Operations Flowchart" page following paragraph concisely summarizes locking functionality.
11.1.1.1
Locked State
default state blocks upon power-up reset locked (states [001] [101]). Locked blocks fully protected from alteration. Program Erase operations attempted locked block will return error SR[1]. state locked block changed Unlocked Lock Down using appropriate software commands. Unlocked block locked writing Lock command sequence, 0x60 followed 0x01.
11.1.1.2
Unlocked State
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return Locked state when device reset powered down. status unlocked block changed Locked Locked Down using appropriate software commands. Locked block unlocked writing Unlock command sequence, 0x60 followed 0xD0.
11.1.1.3
Lock-Down State
Blocks that Locked-Down (state [011]) protected from Program Erase operations (just like Locked blocks), their protection status cannot changed using software commands alone. Locked Unlocked block Locked Down writing Lock-Down command sequence, 0x60 followed 0x2F. Locked-Down blocks revert Locked state when device reset powered down. Lock-Down function depends input pin. When blocks Lock Down [011] protected from program, erase, lock status changes. When Lock-Down function disabled ([111]), Locked-Down blocks individually unlocked software command [110] state, where they erased programmed. These blocks then relocked [111] unlocked [110] required while remains high. When goes low, blocks that were previously Locked Down return Lock-Down state [011], regardless changes made while high. Device reset power-down resets blocks, including those Lock-Down, Locked state.
11.2
Reading Block-Lock Status
Lock status each block read read-identifier mode device issuing readidentifier command (0x90). Subsequent reads Block Address 0x00002 will output Lock status that block. Lock status represented DQ1:
indicates Block Lock/Unlock status Lock command cleared
Unlock command. also automatically when entering Lock Down.
indicates Lock-Down status Lock-Down command. cannot cleared
software-only device reset power-down. Table "Device Identification Codes" page block-status information.
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11.3
Locking Operations during Erase Suspend
Changes block-lock status performed during erase-suspend using standard locking command sequences Unlock, Lock, Lock Down block. This operation useful case when another block needs updated while Erase operation progress. change block locking during Erase operation, first issue Erase Suspend command (0xB0), then check Status Register until indicates that Erase operation been suspended. Next, write preferred Lock command sequence block Lock status will changed. After completing preferred Lock, Read, Program operations, resume Erase operation with Erase Resume command (0xD0). block Locked Locked Down during Suspended Erase same block, locking status bits will changed immediately. when Erase resumed, Erase operation will complete. Locking operations cannot performed during Program Suspend. Refer Appendix "Write State Machine States" page detailed information which commands valid during Erase Suspend.
11.4
Status Register Error Checking
Using nested-locking program-command sequences during Erase Suspend introduce ambiguity into Status Register results. Since locking changes performed using two-cycle command sequence, example, 0x60 followed 0x01 lock block. Following Block Lock, Block Unlock, Block Lock-Down Setup command (0x60) with invalid command will produce Lock-Command error (SR[4] SR[5] will Status Register. Lock-Command error occurs during Erase Suspend, SR[4] SR[5] will will remain after Erase resumed. When Erase complete, possible error during Erase cannot detected Status Register because previous Lock-Command error. similar situation happens error occurs during Program-Operation error nested within Erase Suspend.
11.5
128-Bit Protection Register
device architecture includes 128-bit protection register than used increase security system design. example, number contained protection register used "match" flash component with other system components, such ASIC, preventing device substitution. Application note, AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture, contains additional application information. bits protection register divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unchangeable. other segment left blank customer designs program, preferred. Once customer segment programmed, locked prevent further programming.
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11.5.1
Reading Protection Register
protection register read Read-Identifier mode. device switched this mode issuing Read Identifier command (0x90). Once this mode, read cycles from addresses shown Figure "Protection Register Mapping" retrieve specified information. return ReadArray mode, issue Read Array command (0xFF).
11.5.2
Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time. First, issue Protection Program Setup command, 0xC0. next write device will latch address data program specified location. allowable addresses listed Table "Device Identification Codes" page Figure "Protection Register Programming Flowchart" page Attempting program previously locked protection register segment will result Status Register error (Program Error SR[4] Lock Error SR[1] will
Note:
attempt address Protection Program commands outside defined protection register address space; status register indeterminate.
11.5.3
Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location Figure "Protection Register Mapping" page this location programmed Intel factory protect unique device number. This using Protection Program command program 0xFFFD PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result Status Register error (Program Error SR[4] Lock Error SR[1] will Protection register lockout state reversible.
Figure
Protection Register Mapping
0x88
64-bit Segment (User-Programmable)
0x85 0x84
128-Bit Protection Register
64-bit Segment (Intel Factory-Programmed)
0x81 Lock Register 0x80
11.6
Program Erase Voltages
device provides in-system programming erase 1.65 V-3.6 range. fast production programming, programming used. Figure "Example Power Supply Configurations" page
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11.6.1
Program Protection
addition flexible block locking, programming voltage held absolute hardware write protection blocks flash device. When below equal VPPLK, Program Erase operation will result error, prompting corresponding Status Register (SR[3]) set.
Figure
Example Power Supply Configurations
System Supply Supply Fast Programming Absolute Write Protection With System Supply
(Note
System Supply
Prot# (Logic Signal)
Low-Voltage Programming VPPLK Absolute Write Protection Logic Signal System Supply
Low-Voltage Programming
0645_06
Supply Voltage Fast Programming
Note: resistor used supply sink adequate current based resistor value. AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture details.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix Write State Machine States
Table Table show Write State Machine command state transitions based incoming commands.
Table Write State Machine States
Command Input (and Next State) Data When Read Array Status Config Status Status Status Status Status Status Status Status Status Array Config Status Status Status Status Status Array Config Status Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Read Array Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Read Array Program (Not Done) Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prog. Setup Ers. Setup Erase (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Read Array Prog. Setup Read Array (FFH) Read Array Read Array Read Array Read Array Program Setup (10/ 40H) Prog. Setup Prog. Setup Prog. Setup Prog. Setup Erase Setup (20H) Ers. Setup Ers. Setup Ers. Setup Ers. Setup Lock (Done) Ers. Setup Ers. Setup Erase Confirm (D0H) Prog/Ers Suspend (B0H) Read Array Read Array Read Array Read Array Lock Cmd. Error Read Array Read Array Protection Register Program Protection Register Program (Not Done) Ers. Setup Read Array Program Prog. Sus. Status Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Erase Cmd. Error Read Array Erase Sus. Status Erase Erase Erase Erase Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array Erase Erase Erase Erase Erase (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Read Status Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Read Sts. Read Array Lock (Done) Prog/Ers Resume (D0) Read Status (70H) Read Sts. Read Sts. Read Sts. Read Sts. Clear Status (50H) Read Array Read Array Read Array Read Array
Current State Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config Prog. Susp. Read Query Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Ers. Susp. Status Erase Susp. Array Ers. Susp. Read Config Ers. Susp. Read Query Erase (Done)
SR.7
Lock Command Error Read Array Read Array Prog. Setup Prog. Setup
Lock Cmd. Error Read Sts. Read Sts. Read Array Read Array
Erase Command Error Read Array Prog. Setup Ers. Setup
Erase Command Error Read Status Erase (Not Done) Erase Sus. Status Erase Sus. Status Erase Sus. Status Erase Sus. Status Read Sts. Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array Read Array
Erase (Not Done) Prog. Setup Prog. Setup Prog. Setup Prog. Setup Prog. Setup Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Setup
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Table
Write State Machine States, Continued
Command Input (and Next State) Read Config (90H) Read Config. Read Config. Read Config. Read Config. Read Query (98H) Read Query Read Query Read Query Read Query Lock Setup (60H) Prot. Prog. Setup (C0H) Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Lock Confirm (01H) Lock Down Confirm (2FH) Read Array Read Array Read Array Read Array Lock Operation (Done) Prot. Prog. Setup Prot. Prog. Setup Protection Register Program Protection Register Program (Not Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Program Program (Not Done) Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Read Config. Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Read Query Lock Setup Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prot. Prog. Setup Read Array Erase (Not Done) Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Read Array Read Array Read Array Unlock Confirm (D0H)
Current State
Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query. Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Erase Susp. Status Erase Suspend Array Eras Sus. Read Config Eras Sus. Read Query Ers.(Done)
Lock Setup Lock Setup Lock Setup Lock Setup
Locking Command Error Read Config. Read Config. Read Query Read Query Lock Setup Lock Setup
Erase Command Error Read Config. Read Query Lock Setup Prot. Prog. Setup Erase (Not Done) Ers. Susp. Read Config. Ers. Susp. Read Config. Erase Suspend Read Config. Erase Suspend Read Config. Read Config. Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Read Query Lock Setup Lock Setup Lock Setup Lock Setup Lock Setup Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Prot. Prog. Setup Read Array
Erase (Not Done) Erase (Not Done) Erase (Not Done) Erase (Not Done)
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Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix Flow Charts
Figure Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Operation Command Write
(Setup)
Comments
Write 0x40, Word Address Write Data, Word Address Read Status Register
Program Data 0x40 Setup Addr Location program Data Data Data program Addr Location program Status register data: Toggle update Status Register Check SR[7] Ready Busy
Write
(Confirm)
Read Program Suspend Loop
None
Idle
None
SR[7]
Suspend?
Repeat subsequent Word Program operations. Full Status Register check done after each program, after sequence program operations. Write 0xFF after last operation Read Array state.
Full Status Check desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Command Operation Idle SR[3]
Comments Check SR[3]: Error Check SR[4]: Data Program Error Check SR[1]: Block locked; operation aborted
None
Range Error Idle Program Error None
SR[4]
Idle
None
SR[1]
Device Protect Error
SR[3] MUST cleared before Write State Machine will allow further program attempts. error detected, clear Status Register before continuing operations only Clear Staus Register command clears Status Register error bits.
Program Successful
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Figure
Program Suspend Resume Flowchart
PROGRAM SUSPEND RESUME PROCEDURE
Start Operation Command Write
(Program Suspend)
Comments Data 0x70 Addr address
Write 0xB0 Address Write 0x70 Address Read Status Register
Read Status
Write
(Read Status)
Program Data 0xB0 Suspend Addr address Status register data Toggle update Status register Addr address Check SR[7]: ready busy Check SR[2]: Program suspended Program completed Data 0xFF Addr address Read array data from block other than being programmed
Read
None
SR[7]
Idle
None
SR[2]
Program Completed
Idle
None
Write
(Read Array)
Read Array None
Write 0xFF
Read Read Array Data Write 0xFF
(Read Array)
Write
Program Data 0xD0 Resume Addr address
Done Reading
Read Array Data
Write 0xD0 Address Program Resumed
(Program Resume)
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Figure
Erase Suspend Resume Flowchart
ERASE SUSPEND RESUME PROCEDURE
Start Operation Command Write
(Erase Suspend)
Comments Data 0x70 Addr address Data 0xB0 Addr address Status Register data. Toggle update Status register; Addr Address Check SR[7]: ready busy Check SR[6]: Erase suspended Erase completed
Write 0xB0, Address Write 0x70, Address Read Status Register
Read Status Erase Suspend
Write
(Read Status)
Read
None
Idle SR[7]
None
Idle Erase Completed Write Read Write Write
None
SR[6]
Read Array Data 0xFF 0x40 Program Addr address None Read array program data from/to block other than being erased
Write 0xFF
(Read Array)
Read Array Data
Program Data 0xD0 Resume Addr address
Done Reading
(Erase Resume)
Write 0xD0, Address Erase Resumed
Write 0xFF
(Read Array)
Read Array Data
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Figure
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Command Comments Operation Block Data 0x20 Erase Write Addr Block erased (BA) Setup Write Write 0xD0, (Erase Confirm) Block Address Read Read Status Register
Write 0x20, Block Address
(Block Erase)
Erase Confirm None
Data 0xD0 Addr Block erased (BA) Status Register data. Toggle update Status register data Check SR[7]: ready busy
Suspend Erase Loop Suspend Erase
Idle
None
SR[7]
Repeat subsequent block erasures. Full Status register check done after each block erase after sequence block erasures. Write 0xFF after last operation enter read array mode.
Full Erase Status Check desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register
Command Operation Idle None None None Range Error Command Sequence Error Block Erase Error Block Locked Error
Comments Check SR[3]: Range Error Check SR[4,5]: Both Command Sequence Error Check SR[5]: Block Erase Error
SR[3]
Idle Idle
SR[4,5]
SR[5]
SR[1]
Check SR[1]: Attempted erase locked block; erase aborted. SR[1,3] must cleared before Write State Machine will allow further erase attempts. Idle None Only Clear Status Register command clears SR[1, error detected, clear Status register before attempting erase retry other error recovery.
Block Erase Successful
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Figure
Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Operation Command
(Lock Setup)
Comments Data 0x60 Addr Address 0x01 (Block Lock) 0xD0 (Block Unlock) 0x2F (Lock-Down Block) Block lock/unlock/lock-down
Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address
Write
Lock Setup
(Lock Confirm)
Write
Lock, Data Unlock, Lock-Down Confirm Addr
Write 0x90
(Read Device
Write Read Data 0x90 (Optional) Device Addr Address Read Block Lock Block Lock status data (Optional) Status Addr Block address offset Idle (Optional)
ptional
Read Block Lock Status
Locking Change?
None
Confirm locking change D[1,0]
Write
(Read Array)
Read Array
Data 0xFF Addr address
Write 0xFF Address Lock Change Complete
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Figure
Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start Command Operation Write
(Program Setup)
Comments
Write 0xC0, Address
Program Data 0xC0 Setup Addr First Location Program Protection Data Data Program Program Addr Location Program None Status Register Data. Toggle Update Status Register Data Check SR[7]: Ready Busy
Write Write Address Data
(Confirm Data)
Read
Read Status Register
Idle
None
SR[7]
Program Protection Register operation addresses must within Protection Register address space. Addresses outside this space will return error. Repeat subsequent programming operations.
Full Status Check desired) Program Complete
Full Status Register check done after each program, after sequence program operations. Write 0xFF after last operation Read Array state.
FULL STATUS CHECK PROCEDURE
Read Status Register Data Command Operation Idle SR[3], SR[4]
Comments Check SR[1], SR[3], SR[4]: 0,1,1 Range Error Check SR[1], SR[3], SR[4]: 0,0,1 Programming Error Check SR[1], SR[3], SR[4]: 1,0,1 Block locked; operation aborted
None
Range Error Idle None
Idle SR[3], SR[4]
None
Program Error SR[3] must cleared before Write State Machine will allow further program attempts. Only Clear Staus Register command clears SR[1,
SR[3], SR[4]
Register Locked; Program Aborted
error detected, clear Status register before attempting program retry other error recovery.
Program Successful
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Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix Common Flash Interface
This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software detects which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query database allows system software obtain information controlling flash device. This section describes device's CFI-compliant interface that allows access Query data. Query data presented lowest-order data outputs (DQ0-DQ7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 0x10, which word address devices. word-wide (x16) device, first Query-structure bytes, ASCII "R," appear byte word addresses 0x10 0x11. This CFI-compliant device outputs 0x00 data upper bytes. device outputs ASCII byte (DQ0-DQ7) 0x00 high byte (DQ8-DQ15). Query addresses containing more bytes information, least-significant data byte presented lower address, most-significant data byte presented higher address. tables this appendix, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "0x00," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have 0x00 upper byte this mode.
Table
Summary Query Structure Output Function Device Mode
Device Offset
00010: Device Addresses 00011: 00012:
Code
ASCII Value
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Table
Example Query Structure Output Devices
Word Addressing: Offset A[X-0]
0x00010 0x00011 0x00012 0x00013 0x00014 0x00015 0x00016 0x00017 0x00018 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI
Code DQ[16:0]
Value
PrVendor PrVendor TblAdr AltVendor
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." Table summarizes structure sub-sections address locations.
Table
Query Structure
Offset
0x00000 0x00001 0x(BA+2)
Sub-Section Name
Manufacturer Code Device Code Block Status register Reserved query identification string System interface information Device geometry definition Primary Intel-specific Extended Query Table
Description1
Block-specific information Reserved vendor-specific information Command vendor data offset Device timing voltage information Flash device layout Vendor-defined additional information specific Primary Vendor Algorithm
0x00004-0xF 0x00010 0x0001B 0x00027
Notes: Refer Query Structure Output section offset 0x28 detailed definition offset address function device width mode. Block Address beginning location (i.e., 0x08000 block beginning location when block size 32K-word). Offset defines which points Primary Intel-specific Extended Query Table.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Block Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations. Table Block Erase Status (BSR[1]) allows system software determine success last block erase operation. BSR[1] used just after power-up verify that supply accidentally removed during erase operation.
Table
Block Status Register
Offset Length Description
Block Lock Status Register BSR[0] Block lock status Unlocked Locked BSR[1] Block lock-down status locked down Locked down BSR[7:2]: Reserved future
Add.
BA+2 BA+2
Value
(bit
0x(BA+2)1
BA+2 BA+2
(bit (bit 2-7):
Notes: Block Address beginning location (i.e., 0x08000 block beginning location when block size 32K-word).
2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s). Table
Table
Offset
0x10
Identification
Length
Description
Query-unique ASCII string "QRY" Primary vendor command control interface code 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code 0x0000 means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address 0x0000 means none exists
Add.
Code
Value
0x13 0x15 0x17 0x19
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Offset
0x1B
System Interface Information
Length
Description
logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
Add.
Code
Value
0x1C
0x1D
11.4
0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26
12.6 512µs
Table
Offset
Device Geometry Definition
Device Geometry Definition
Length Description
such that device size number bytes async 28:00,29:00 async 28:01,29:00 x8/x16 async 28:02,29:00
Add.
Code
Value
0x27
Table "Device Geometry Details" page
0x28 0x2A
Flash device interface:
such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks. Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes
0x2C
0x2D
Table "Device Geometry Details" page
0x2D
Table "Device Geometry Details" page
2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Device Geometry Details
Mbit Address
0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34
Mbit
Mbit
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel-Specific Extended Query Table
Certain flash features commands optional shown Table "Primary-Vendor Specific Extended Query" page Intel-specific Extended Query table specifies these features well other similar types information.
Table
Offset1 0x15
0x(P+0) 0x(P+1) 0x(P+2) 0x(P+3) 0x(P+4)
Primary-Vendor Specific Extended Query
Length Description (Optional Flash Features Commands)
Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field.
Address
Code
Value
0x(P+5) 0x(P+6) 0x(P+7) 0x(P+8)
Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant individual block locking supported Protection bits supported Page mode read supported Synchronous read supported Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block Status Register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status Register active Block Lock-Down Status active logic supply highest performance program/ erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts
0x(P+9)
0x(P+A) 0x(P+B)
0x(P+C)
0x(P+D)
12.0
Notes: variable pointer which defined offset 0x15.
2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Offset1 0x35
0x(P+E) 0x(P+F) 0x(P+10) (0xP+11)
Protection Register Information
Length
Description (Optional Flash Features Commands)
Number Protection register fields JEDEC space. "00h," indicates that protection bytes available
Address
Code
Value
byte
0x(P+12)
Protection Field Protection Description This field describes user-available Time Programmable (OTP) Protection register bytes. Some pre-programmed with deviceunique serial numbers. Others user programmable. Bits 0-15 point Protection register Lock byte, section's first byte. following bytes factory pre-programmed userprogrammable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC -plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user programmable bytes Reserved future
byte
0x(P+13)
Notes: variable pointer which defined offset 0x15.
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix Additional Information
Order Number
297938 292216 292215 Contact your Intel Representative 297874
Document/Tool
Volt Advanced+ Boot Block Flash Memory Specification Update AP-658 Designing Upgrade Advanced+ Boot Block Flash Memory AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture Intel® Flash Data Integrator (Intel® FDI) Software Developer's IFDI Interactive: Play with Intel® Flash Data Integrator Your
Notes: 1.Call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. 2.See Intel page technical documentation tools.
2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix Ordering Information
Figure Component Ordering Information
Package Lead TSOP Ball µBGA Easy Free Easy Free VFBGA Free TSOP Product line designator Intel Flash products Device Density Mbit) Mbit) Mbit) Mbit) Access Speed (ns) (70, Lithography 0.25 0.18 0.13 Blocking Bottom Blocking Product Family Volt Advanced+ Boot Block V-3.6 V-12
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
2005
Intel® Advanced+ Boot Block Flash Memory (C3)
Table
Product Information Ordering Matrix
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP
Extended Mbit TE28F320C3TD70 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 JS28F320C3BD70 JS28F320C3TD70 JS28F320C3BD90 JS28F320C3TD90 TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC70 TE28F160C3BC70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TC90 TE28F160C3BC90 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 JS28F160C3BD70 JS28F160C3TD70 TE28F800C3TD70 TE28F800C3BD70 TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 JS28F800C3BD70 JS28F800C3TD70
48-Ball µBGA*
48-Ball
Easy
Extended Mbit
GT28F320C3TA100 GT28F320C3BA100 GT28F320C3TA110 GT28F320C3BA110
GE28F320C3TD70 GE28F320C3BD70 GE28F320C3TC70 GE28F320C3BC70 GE28F320C3TC90 GE28F320C3BC90 PH28F320C3BD70 PH28F320C3TD70 PH28F320C3BD90 PH28F320C3TD90
RC28F320C3TD70 RC28F320C3BD70 RC28F320C3TD90 RC28F320C3BD90 RC28F320C3TC90 RC28F320C3BC90 RC28F320C3TA100 RC28F320C3BA100 RC28F320C3TA110 RC28F320C3BA110 PC28F320C3BD70 PC28F320C3TD70 PC28F320C3BD90 PC28F320C3TD90 RC28F160C3TD70 RC28F160C3BD70 RC28F160C3TC70 RC28F160C3BC70 RC28F160C3TC80 RC28F160C3BC80 RC28F160C3TC90 RC28F160C3BC90 RC28F160C3TA90 RC28F160C3BA90 RC28F160C3TA110 RC28F160C3BA110 PC28F160C3BD70 PC28F160C3TD70 RC28F800C3TD70 RC28F800C3BD70 RC28F800C3TA90 RC28F800C3BA90 RC28F800C3TA110 RC28F800C3BA110 PC28F800C3BD70 PC28F800C3TD70
Extended Mbit
GT28F160C3TA90 GT28F160C3BA90 GT28F160C3TA110 GT28F160C3BA110
GE28F160C3TD70 GE28F160C3BD70 GE28F160C3TC70 GE28F160C3BC70 GE28F160C3TC80 GE28F160C3BC80 GE28F160C3TC90 GE28F160C3BC90 PH28F160C3BD70 PH28F160C3TD70
Extended Mbit
Note:
second line 48-ball µBGA package side mark specifies assembly codes. samples only, first character signifies either engineering samples silicon daisy chain samples. other assembly codes without first character production units.
2005
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision:
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