Diagrams PDIP, SOIC RA4/T0CKI MCLR RB0/INT 18-pin Enhan
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PIC16F84A
Diagrams
PDIP, SOIC
RA4/T0CKI MCLR RB0/INT
18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
Devices Included this Data Sheet:
PIC16F84A Extended voltage range device available (PIC16LF84A)
OSC1/CLKIN OSC2/CLKOUT
High Performance RISC Features:
Only single word instructions learn instructions single cycle except program branches which two-cycle Operating speed: clock input instruction cycle 1024 words program memory bytes data bytes data EEPROM 14-bit wide instruction words 8-bit wide data bytes special function hardware registers Eight-level deep hardware stack Direct, indirect relative addressing modes Four interrupt sources: External RB0/INT TMR0 timer overflow PORTB<7:4> interrupt change Data EEPROM write complete
SSOP
RA4/T0CKI MCLR RB0/INT
PIC16F84A PIC16F84A
OSC1/CLKIN OSC2/CLKOUT
Peripheral Features:
pins with individual direction control High current sink/source direct drive sink max. source max. TMR0: 8-bit timer/counter with 8-bit programmable prescaler
CMOS Enhanced Flash/EERPOM Technology:
Low-power, high-speed technology Fully static design Wide operating voltage range: Commercial: 2.0V 5.5V Industrial: 2.0V 5.5V power consumption: typical typical typical standby current
Special Microcontroller Features:
1000 erase/write cycles Enhanced Flash program memory 1,000,000 typical erase/write cycles EEPROM data memory EEPROM Data Retention years In-Circuit Serial Programming (ICSPTM) pins Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with on-chip oscillator reliable operation Code-protection Power saving SLEEP mode Selectable oscillator options
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PIC16F84A
Table Contents
Device Overview Memory Organization. Ports. Timer0 Module Data EEPROM Memory. Special Features Instruction Summary. Development Support Electrical Characteristics PIC16F84A. 10.0 Characteristics Graphs/Tables 11.0 Packaging Information Appendix Revision History Appendix Conversion Considerations. Appendix Migration from Baseline Midrange Devices Index On-Line Support. Reader Response PIC16F84A Product Identification System
Valued Customers
Most Current Data Sheet
obtain most up-to-date version this data sheet, please check Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number. e.g., DS30000A version document DS30000.
Errata
errata sheet exist current devices, describing minor operational differences (from data sheet) recommended workarounds. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting sales office literature center, please specify which device, revision silicon data sheet (include literature number) using.
Corrections this Data Sheet
constantly strive improve quality products documentation. have spent great deal time ensure that this document correct. However, realize that have missed things. find information that missing appears error, please: Fill mail reader response form back this data sheet. E-mail webmaster@microchip.com. appreciate your assistance making this better document.
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PIC16F84A
DEVICE OVERVIEW
This document contains device-specific information operation PIC16F84A device. Additional information found PICmicroMid-Range Reference Manual, (DS33023), which downloaded from Microchip website. Reference Manual should considered complementary document this data sheet, highly recommended reading better understanding device architecture operation peripheral modules. PIC16F84A belongs mid-range family PICmicromicrocontroller devices. block diagram device shown Figure 1-1. program memory contains words, which translates 1024 instructions, since each 14-bit program memory word same width each device instruction. data memory (RAM) contains bytes. Data EEPROM bytes. There also pins that user-configured pin-to-pin basis. Some pins multiplexed with other device functions. These functions include: External interrupt Change PORTB interrupt Timer0 clock input Table details pinout device with descriptions details each pin.
FIGURE 1-1:
PIC16F84A BLOCK DIAGRA13 Data Program Counter EEPROM Data Memory
Flash Program Memory PIC16F84A Program Level Stack (13-bit) File Registers PIC16F84A Addr
EEDATA
EEPROM Data Memory
EEADR
Instruction Direct Addr
Addr Indirect Addr TMR0
RA4/T0CKI STATUS
Power-up Timer Instruction Decode Control Oscillator Start-up Timer Power-on Reset Watchdog Timer
Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD,
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PIC16F84A
TABLE
Name OSC1/CLKIN OSC2/CLKOUT
PIC16F84A PINOUT DESCRIPTION
SOIC SSOP I/O/P Type Buffer Type Description
ST/CMOS Oscillator crystal input/external clock source input. Oscillator crystal output. Connects crystal resonator crystal oscillator mode. mode, OSC2 outputs CLKOUT which frequency OSC1, denotes instruction cycle rate. Master clear (reset) input/programming voltage input. This active reset device. PORTA bi-directional port.
MCLR
RA4/T0CKI
also selected clock input TMR0 timer/counter. Output open drain type. PORTB bi-directional port. PORTB software programmed internal weak pull-up inputs.
RB0/INT Legend: input
15,16
TTL/ST TTL/ST
RB0/INT also selected external interrupt pin.
Interrupt change pin. Interrupt change pin. Interrupt change pin. Serial programming clock. Interrupt change pin. Serial programming data. Ground reference logic pins. Positive supply logic pins.
TTL/ST
output Input/Output power used input Schmitt Trigger input Note This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used serial programming mode. This buffer Schmitt Trigger input when configured oscillator mode CMOS input otherwise.
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PIC16F84A
MEMORY ORGANIZATION
FIGURE 2-1:
There memory blocks PIC16F84A. These program memory data memory. Each block bus, that access each block occur during same oscillator cycle. data memory further broken down into general purpose Special Function Registers (SFRs). operation SFRs that control "core" described here. SFRs used control peripheral modules described section discussing each individual peripheral module. data memory area also contains data EEPROM memory. This memory directly mapped into data memory, indirectly mapped. That indirect address pointer specifies address data EEPROM memory read/write. bytes data EEPROM memory have address range 0h-3Fh. More details EEPROM memory found Section 5.0. Additional information device memory found PICmicroMid-Range Reference Manual, (DS33023).
PROGRAM MEMORY STACK PIC16F84A
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level
Stack Level Reset Vector Peripheral Interrupt Vector
0000h 0004h
User Memory Space
Program Memory Organization
3FFh
PIC16FXX 13-bit program counter capable addressing program memory space. PIC16F84A, first (0000h-03FFh) physically implemented (Figure 2-1). Accessing location above physically implemented address will cause wraparound. example, locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, 1C20h will same instruction. reset vector 0000h interrupt vector 0004h.
1FFFh
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PIC16F84A
Data Memory Organization
2.2.1 GENERAL PURPOSE REGISTER FILE data memory partitioned into areas. first Special Function Registers (SFR) area, while second General Purpose Registers (GPR) area. SFRs control operation device. Portions data memory banked. This both area area. area banked allow greater than bytes general purpose RAM. banked areas registers that control peripheral functions. Banking requires control bits bank selection. These control bits located STATUS Register. Figure shows data memory organization. Instructions MOVWF MOVF move values from register location register file ("F"), vice-versa. entire data memory accessed either directly using absolute address each register file indirectly through File Select Register (FSR) (Section 2.4). Indirect addressing uses present value access into banked areas data memory. Data memory partitioned into banks which contain general purpose registers special function registers. Bank selected clearing (STATUS<5>). Setting selects Bank Each Bank extends (128 bytes). first twelve locations each Bank reserved Special Function Registers. remainder General Purpose Registers implemented static RAM. Each General Purpose Register (GPR) bits wide accessed either directly indirectly through (Section 2.4). addresses bank mapped addresses bank example, addressing location will access same GPR.
FIGURE 2-1:
File Address
REGISTER FILE PIC16F84A
File Address Indirect addr.(1) OPTION_REG STATUS TRISA TRISB EECON1 EECON2(1) PCLATH INTCON EEDATA EEADR PCLATH INTCON
Indirect addr.(1) TMR0 STATUS PORTA PORTB
General Purpose Registers (SRAM)
Mapped (accesses) Bank
Bank Bank
Unimplemented data memory location; read '0'. Note physical register.
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PIC16F84A
2.2.2 SPECIAL FUNCTION REGISTERS Special Function Registers (Figure Table 2-1) used Peripheral functions control device operation. These registers static RAM. special function registers classified into sets, core peripheral. Those associated with core functions described this section. Those related operation peripheral features described section that specific feature.
TABLE
REGISTER FILE SUMMARY
Value Power-on Reset Value other resets (Note3)
Addr
Name
Bank Bank EECON1 EECON2 PCLATH INTCON INDF OPTION_REG STATUS TRISA TRISB Uses contents address data memory (not physical register) RBPU INTEDG T0CS T0SE -1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 -EEIF WRERR WREN x000 0000 INTF RBIF 0000 000x -1111 1111 0000 0000 000q quuu uuuu uuuu 1111 1111 1111 q000 0000 0000 000u EEDATA EEADR PCLATH INTCON INDF TMR0 STATUS PORTA PORTB
Uses contents address data memory (not physical register) 8-bit real-time clock/counter order bits Program Counter (PC)
-xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
-uuuu uuuu 0000 0000 000q quuu uuuu uuuu uuuu uuuu uuuu -uuuu uuuu uuuu uuuu 0000 0000 000u
Indirect data memory address pointer RA4/T0CKI RB0/INT
xxxx xxxx xxxx -xxxx xxxx xxxx xxxx
Unimplemented location, read EEPROM data register EEPROM address register EEIE T0IE Write buffer upper bits INTE RBIE T0IF INTF RBIF
0000 0000 000x
order bits Program Counter (PC)
Indirect data memory address pointer PORTA data direction register
PORTB data direction register Unimplemented location, read
EEPROM control register (not physical register) EEIE T0IE Write buffer upper bits INTE RBIE T0IF
Legend: unknown, unchanged. unimplemented read '0', value depends condition. Note upper byte program counter directly accessible. PCLATH slave register PC<12:8>. contents PCLATH transferred upper byte program counter, contents PC<12:8> never transferred PCLATH. status bits STATUS register affected MCLR reset. Other (non power-up) resets include: external reset through MCLR Watchdog Timer Reset. device reset, these pins configured inputs. This value that will port output latch.
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PIC16F84A
2.2.2.1 STATUS REGISTER STATUS register contains arithmetic status ALU, RESET status bank select data memory. with register, STATUS register destination instruction. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS will clear upper-three bits bit. This leaves STATUS register 000u u1uu (where unchanged). Only BCF, BSF, SWAPF MOVWF instructions should used alter STATUS register (Table 7-2) because these instructions affect status bit. Note bits (STATUS<7:6>) used PIC16F84A should programmed cleared. these bits general purpose bits recommended, since this affect upward compatibility with future products. Note bits operate borrow digit borrow bit, respectively, subtraction. SUBLW SUBWF instructions examples. Note When STATUS register destination instruction that affects bits, then write these three bits disabled. specified bit(s) will updated according device logic
FIGURE 2-1:
R/W-0 bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-x R/W-x R/W-x bit0
R/W-0
Readable Writable Unimplemented bit, read Value reset
IRP: Register Bank Select (used indirect addressing) used PIC16F84A. should maintained clear.
6-5: RP1:RP0: Register Bank Select bits (used direct addressing) Bank (00h 7Fh) Bank (80h FFh) Each bank bytes. Only used PIC16F84A. should maintained clear. Time-out After power-up, CLRWDT instruction, SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit carry/borrow (for ADDWF ADDLW instructions) (For borrow polarity reversed) carry-out from order result occurred carry-out from order result Carry/borrow (for ADDWF ADDLW instructions) carry-out from most significant result occurred carry-out from most significant result occurred Note:For borrow polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high order source register.
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PIC16F84A
2.2.2.2 OPTION_REG REGISTER Note: When prescaler assigned (PSA '1'), TMR0 prescaler assignment. OPTION_REG register readable writable register which contains various control bits configure TMR0/WDT prescaler, external interrupt, TMR0, weak pull-ups PORTB.
FIGURE 2-1:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1 bit0
R/W-1 INTEDG
Readable Writable Unimplemented bit, read Value reset
RBPU: PORTB Pull-up Enable PORTB pull-ups disabled PORTB pull-ups enabled individual port latch values) INTEDG: Interrupt Edge Select Interrupt rising edge RB0/INT Interrupt falling edge RB0/INT T0CS: TMR0 Clock Source Select Transition RA4/T0CKI Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select Increment high-to-low transition RA4/T0CKI Increment low-to-high transition RA4/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned TMR0
2-0: PS2:PS0: Prescaler Rate Select bits
Value TMR0 Rate Rate
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2.2.2.3 INTCON REGISTER Note: Interrupt flag bits when interrupt condition occurs regardless state corresponding enable global enable bit, (INTCON<7>). INTCON register readable writable register which contains various enable bits interrupt sources.
FIGURE 2-1:
R/W-0 bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 EEIE
Readable Writable Unimplemented bit, read Value reset
GIE: Global Interrupt Enable Enables un-masked interrupts Disables interrupts Note: operation interrupt structure, please refer Section EEIE: Write Complete Interrupt Enable Enables write complete interrupt Disables write complete interrupt T0IE: TMR0 Overflow Interrupt Enable Enables TMR0 interrupt Disables TMR0 interrupt INTE: RB0/INT Interrupt Enable Enables RB0/INT interrupt Disables RB0/INT interrupt RBIE: Port Change Interrupt Enable Enables port change interrupt Disables port change interrupt T0IF: TMR0 Overflow Interrupt Flag TMR0 overflowed (must cleared software) TMR0 overflow INTF: RB0/INT Interrupt Flag RB0/INT interrupt occurred RB0/INT interrupt occur RBIF: Port Change Interrupt Flag When least RB7:RB4 pins changed state (must cleared software) None RB7:RB4 pins have changed state
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PIC16F84A
PCLATH
program counter (PC) specifies address instruction fetch execution. bits wide. byte called register. This register readable writable. high byte called register. This register contains PC<12:8> bits directly readable writable. updates register through PCLATH register. 2.3.1 STACK
Indirect Addressing; INDF Registers
INDF register physical register. Addressing INDF actually addresses register whose address contained register (FSR pointer). This indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
stack allows combination program calls interrupts occur. stack contains return address from this branch program execution. Midrange devices have level deep 13-bit wide hardware stack. stack space part either program data space stack pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH modified when stack PUSHed POPed. After stack been PUSHed eight times, ninth push overwrites value that stored from first push. tenth push overwrites second push (and on).
Register file contains value Register file contains value Load value into register read INDF register will return value Increment value register (FSR read INDF register will return value 0Ah. Reading INDF itself indirectly (FSR will produce 00h. Writing INDF register indirectly results no-operation (although STATUS bits affected). simple program clear locations 20h-2Fh using indirect addressing shown Example 2-2.
EXAMPLE 2-2:
CLEAR USING INDIRECT ADDRESSING
0x20 INDF FSR,4 NEXT ;initialize pointer ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
NEXT
movlw movwf clrf incf btfss goto
CONTINUE
effective 9-bit address obtained concatenating 8-bit register (STATUS<7>), shown Figure 2-1. However, used PIC16F84A.
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FIGURE 2-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing from opcode Indirect Addressing (FSR)
bank select
location select
bank select
location select
Data Memory Bank Bank Addresses back Bank
Note memory detail Figure 2-1. Maintain clear upward compatiblity with future products. implemented.
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PIC16F84A
PORTS
FIGURE 3-1:
Data Port
Some pins these ports multiplexed with alternate function peripheral features device. general, when peripheral enabled, that used general purpose pin. Additional information ports found PICmicroMid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM PINS RA3:RA0
Data Latch
PORTA TRISA Registers
TRIS
PORTA 5-bit wide bi-directional port. corresponding data direction register TRISA. Setting TRISA (=1) will make corresponding PORTA input, i.e., corresponding output driver hi-impedance mode. Clearing TRISA (=0) will make corresponding PORTA output, i.e., contents output latch selected pin. Note: Power-on Reset, these pins configured inputs read '0'.
input buffer
TRIS Latch
TRIS
Reading PORTA register reads status pins whereas writing will write port latch. write operations read-modify-write operations. Therefore write port implies that port pins read, this value modified, then written port data latch. multiplexed with Timer0 module clock input become RA4/T0CKI pin. RA4/T0CKI Schmitt Trigger input open drain output. other port pins have input levels full CMOS output drivers.
PORT
Note: pins have protection diodes VSS.
EXAMPLE 3-1:
CLRF
INITIALIZING PORTA
Initialize PORTA clearing output data latches Select Bank Value used initialize data direction RA<3:0> inputs output TRISA<7:5> always read '0'.
STATUS, PORTA
MOVLW
STATUS, 0x0F
MOVWF
TRISA
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FIGURE 3-2:
Data PORT
BLOCK DIAGRAM
Data Latch
TRIS
TRIS Latch
Schmitt Trigger input buffer
TRIS
PORT TMR0 clock input Note: protection diodes only.
TABLE
Name RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type Function
Input/output Input/output Input/output Input/output Input/output external clock input TMR0. Output open drain type. Legend: input, Schmitt Trigger input
TABLE
Address Name PORTA TRISA
SUMMARY REGISTERS ASSOCIATED WITH PORTA
RA4/T0CKI TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 Value Power-on Reset xxxx 1111 Value other resets uuuu 1111
Legend: unknown, unchanged, unimplemented read '0'. Shaded cells unimplemented, read
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PORTB TRISB Registers
PORTB 8-bit wide bi-directional port. corresponding data direction register TRISB. Setting TRISB (=1) will make corresponding PORTB input, i.e., corresponding output driver hi-impedance mode. Clearing TRISB (=0) will make corresponding PORTB output, i.e., contents output latch selected pin. Four PORTB's pins, RB7:RB4, have interrupt change feature. Only pins configured inputs cause this interrupt occur (i.e. RB7:RB4 configured output excluded from interrupt change comparison). input pins RB7:RB4) compared with value latched last read PORTB. "mismatch" outputs RB7:RB4 OR'ed together generate Port Change Interrupt with flag RBIF (INTCON<0>). This interrupt wake device from SLEEP. user, interrupt service routine, clear interrupt following manner: read write PORTB. This will mismatch condition. Clear flag RBIF.
EXAMPLE 3-1:
CLRF
INITIALIZING PORTB
Initialize PORTB clearing output data latches Select Bank Value used initialize data direction RB<3:0> inputs RB<5:4> outputs RB<7:6> inputs
STATUS, PORTB
MOVLW
STATUS, 0xCF
MOVWF
TRISB
mismatch condition will continue flag RBIF. Reading PORTB will mismatch condition, allow flag RBIF cleared. interrupt change feature recommended wake-up depression operation operations where PORTB only used interrupt change feature. Polling PORTB recommended while using interrupt change feature.
Each PORTB pins weak internal pull-up. single control turn pull-ups. This performed clearing RBPU (OPTION<7>). weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset.
FIGURE 3-4:
RBPU(1)
BLOCK DIAGRAM PINS RB3:RB0
weak pull-up Data Latch TRIS Latch pin(2)
FIGURE 3-3:
BLOCK DIAGRAM PINS RB7:RB4
Data RBPU(1) Data Latch TRIS Latch TRIS Input Buffer pin(2) TRIS Port
weak pull-up
Data Port
Input Buffer
TRIS Port
TRIS
Latch
RB0/INT Schmitt Trigger Buffer Note TRISB enables weak pull-up RBPU OPTION_REG register). pins have diode protection VSS. Port
Port RBIF From other RB7:RB4 pins
Port
Note TRISB enables weak pull-up RBPU OPTION_REG register). pins have diode protection VSS.
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TABLE
Name RB0/INT
PORTB FUNCTIONS
bit0 Buffer Type TTL/ST(1) Consistency Function
Input/output external interrupt input. Internal software programmable weak pull-up. bit1 Input/output pin. Internal software programmable weak pull-up. bit2 Input/output pin. Internal software programmable weak pull-up. bit3 Input/output pin. Internal software programmable weak pull-up. bit4 Input/output (with interrupt change). Internal software programmable weak pull-up. bit5 Input/output (with interrupt change). Internal software programmable weak pull-up. bit6 TTL/ST(2) Input/output (with interrupt change). Internal software programmable weak pull-up. Serial programming clock. bit7 TTL/ST(2) Input/output (with interrupt change). Internal software programmable weak pull-up. Serial programming data. Legend: input, Schmitt Trigger. Note This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used serial programming mode.
TABLE
Addr Name PORTB TRISB
SUMMARY REGISTERS ASSOCIATED WITH PORTB
TRISB7 RBPU TRISB6 INTEDG TRISB5 T0CS TRISB4 T0SE TRISB3 TRISB2 TRISB1 RB0/INT TRISB0 Value Power-on Reset xxxx xxxx 1111 1111 1111 1111 Value other resets uuuu uuuu 1111 1111 1111 1111
OPTION_REG
Legend: unknown, unchanged. Shaded cells used PORTB.
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PIC16F84A
TIMER0 MODULE
Timer0 module timer/counter following features: 8-bit timer/counter Readable writable Internal external clock select Edge select external clock 8-bit software programmable prescaler Interrupt overflow from Additional information external clock requirements available PICmicroMid-Range Reference Manual, (DS33023).
Prescaler
Figure simplified block diagram Timer0 module. Additional information timer modules available PICmicroMid-Range Reference Manual, (DS33023).
8-bit counter available prescaler Timer0 module, postscaler Watchdog Timer, respectively (Figure 4-2). simplicity, this counter being referred "prescaler" throughout this data sheet. Note that there only prescaler available which mutually exclusively shared between Timer0 module Watchdog Timer. Thus, prescaler assignment Timer0 module means that there prescaler Watchdog Timer, vice-versa. prescaler readable writable. PS2:PS0 bits (OPTION_REG<3:0>) determine prescaler assignment prescale ratio. Clearing will assign prescaler Timer0 module. When prescaler assigned Timer0 module, prescale values 1:2, 1:4, 1:256 selectable. Setting will assign prescaler Watchdog Timer (WDT). When prescaler assigned WDT, prescale values 1:1, 1:2, 1:128 selectable. When assigned Timer0 module, instructions writing TMR0 register (e.g. CLRF MOVWF 1,x.etc.) will clear prescaler. When assigned WDT, CLRWDT instruction will clear prescaler along with WDT. Note: Writing TMR0 when prescaler assigned Timer0 will clear prescaler count, will change prescaler assignment.
Timer0 Operation
Timer0 operate timer counter. Timer mode selected clearing T0CS (OPTION_REG<5>). timer mode, Timer0 module will increment every instruction cycle (without prescaler). TMR0 register written, increment inhibited following instruction cycles. user work around this writing adjusted value TMR0 register. Counter mode selected setting T0CS (OPTION_REG<5>). counter mode, Timer0 will increment either every rising falling edge RA4/T0CKI. incrementing edge determined Timer0 Source Edge Select T0SE (OPTION_REG<4>). Clearing T0SE selects rising edge. Restrictions external clock input discussed below. When external clock input used Timer0, must meet certain requirements. requirements ensure external clock synchronized with internal phase clock (TOSC). Also, there delay actual incrementing Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAData FOSC/4 Programmable Prescaler T0SE PS2, PS1, T0CS interrupt flag T0IF overflow PSout Sync with Internal clocks cycle delay) TMR0 PSout
RA4/T0CKI
Note T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). prescaler shared with Watchdog Timer (refer Figure detailed block diagram).
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PIC16F84A
4.2.1 SWITCHING PRESCALER ASSIGNMENT
Timer0 Interrupt
prescaler assignment fully under software control, i.e., changed fly" during program execution. Note: avoid unintended device RESET, specific instruction sequence (shown PICmicroMid-Range Reference Manual, DS3023) must executed when changing prescaler assignment from Timer0 WDT. This sequence must followed even disabled.
TMR0 interrupt generated when TMR0 register overflows from 00h. This overflow sets T0IF (INTCON<2>). interrupt masked clearing T0IE (INTCON<5>). T0IF must cleared software Timer0 module interrupt service routine before re-enabling this interrupt. TMR0 interrupt cannot awaken processor from SLEEP since timer shut during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM TIMER0/WDT PRESCALER
Data SYNC Cycles TMR0
CLKOUT (=Fosc/4)
RA4/T0CKI T0SE
T0CS
flag T0IF Overflow
8-bit Prescaler 1MUX PS2:PS0
Watchdog Timer
Enable
Time-out Note: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
TABLE
Address 0Bh,8Bh
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 INTCON OPTION_REG TRISA Value POR, xxxx xxxx INTE T0SE RBIE T0IF INTF RBIF 0000 000x 1111 1111 1111 Value other resets uuuu uuuu 0000 000u 1111 1111 1111
Timer0 module's register PEIE T0IE T0CS
RBPU INTEDG
PORTA Data Direction Register
Legend: unknown, unchanged, unimplemented locations read '0'. Shaded cells used Timer0.
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PIC16F84A
DATA EEPROM MEMORY
EEPROM data memory readable writable during normal operation (full range). This memory directly mapped register file space. Instead indirectly addressed through Special Function Registers. There four SFRs used read write this memory. These registers are: EECON1 EECON2 (Not physically implemented register) EEDATA EEADR EEPROM data memory allows byte read write. byte write automatically erases location writes data (erase before write). EEPROM data memory rated high erase/write cycles. write time controlled on-chip timer. writetime will vary with voltage temperature well from chip chip. Please refer specifications exact limits. When device code protected, continue read write data EEPROM memory. device programmer longer access this memory. Additional information Data EEPROM available PICmicroMid-Range Reference Manual, (DS33023).
EEDATA holds 8-bit data read/write, EEADR holds address EEPROM location being accessed. PIC16F84A devices have bytes data EEPROM with address range from 3Fh.
FIGURE 5-1:
bit7
EECON1 REGISTER (ADDRESS 88h)
R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 R/S-x bit0 Readable Writable Settable Unimplemented bit, read Value reset
Unimplemented: Read EEIF: EEPROM Write Operation Interrupt Flag write operation completed (must cleared software) write operation complete been started WRERR: EEPROM Error Flag write operation prematurely terminated (any MCLR reset reset during normal operation) write operation completed WREN: EEPROM Write Enable Allows write cycles Inhibits write data EEPROM Write Control initiates write cycle. (The cleared hardware once write complete. only (not cleared) software. Write cycle data EEPROM complete Read Control Initiates EEPROM read (read takes cycle. cleared hardware. only (not cleared) software). Does initiate EEPROM read
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PIC16F84A
Reading EEPROM Data Memory
read data memory location, user must write address EEADR register then control (EECON1<0>). data available, very next cycle, EEDATA register; therefore read next instruction. EEDATA will hold this value until another read until written user (during write operation). code execution (i.e., lost programs). user should keep WREN clear times, except when updating EEPROM. WREN cleared hardware After write sequence been initiated, clearing WREN will affect this write cycle. will inhibited from being unless WREN set. completion write cycle, cleared hardware Write Complete Interrupt Flag (EEIF) set. user either enable this interrupt poll this bit. EEIF must cleared software.
EXAMPLE 5-1:
MOVLW MOVWF MOVF
DATA EEPROM READ
Bank Address read Bank Read Bank EEDATA
STATUS, CONFIG_ADDR EEADR STATUS, EECON1, STATUS, EEDATA,
Write Verify
Writing EEPROM Data Memory
write EEPROM data location, user must first write address EEADR register data EEDATA register. Then user must follow specific sequence initiate write each byte.
Depending application, good programming practice dictate that value written Data EEPROM should verified (Example 5-1) desired value written. This should used applications where EEPROM will stressed near specification limit. Total Endurance disk will help determine your comfort level. Generally EEPROM write failure will which written '0', reads back (due leakage bit).
EXAMPLE 5-1:
MOVLW MOVWF MOVLW MOVWF
DATA EEPROM WRITE
Bank Disable INTs. Enable Write Write Write begin write Enable INTs. READ EECON1, YES, Read value written STATUS, Bank
Required Sequence
STATUS, INTCON, EECON1, WREN EECON2 EECON2 EECON1,WR INTCON,
EXAMPLE 5-1:
MOVF
WRITE VERIFY
Bank code here Must Bank Bank
STATUS, EEDATA, STATUS,
write will initiate above sequence exactly followed (write EECON2, write EECON2, then bit) each byte. strongly recommend that interrupts disabled during this code segment. Additionally, WREN EECON1 must enable write. This mechanism prevents accidental writes data EEPROM errant (unexpected)
value written reg) read EEDATA) same? SUBWF EEDATA, BTFSS STATUS, difference GOTO WRITE_ERR Write error YES, Good write Continue program
TABLE
Address Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROBit Value Power-on Reset xxxx xxxx xxxx xxxx EEIF WRERR WREN x000 -Value other resets uuuu uuuu uuuu uuuu q000
EEDATA EEADR EECON1 EECON2
EEPROM data register EEPROM address register
EEPROM control register
Legend: unknown, unchanged, unimplemented read '0', value depends upon condition. Shaded cells used data EEPROM.
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PIC16F84A
SPECIAL FEATURES
chip reset until crystal oscillator stable. other Power-up Timer (PWRT), which provides fixed delay (nominal) power-up only. This design keeps device reset while power supply stabilizes. With these timers on-chip, most applications need external reset circuitry. SLEEP mode offers very current power-down mode. user wake-up from SLEEP through external reset, Watchdog Timer time-out through interrupt. Several oscillator options provided allow part application. oscillator option saves system cost while crystal option saves power. configuration bits used select various options. Additional information special features available PICmicroMid-Range Reference Manual, (DS33023).
What sets microcontroller apart from other processors special circuits deal with needs real time applications. PIC16F84A host such features intended maximize system reliability, minimize cost through elimination external components, provide power saving operating modes offer code protection. These features are: Selection Reset Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Interrupts Watchdog Timer (WDT) SLEEP Code protection locations In-circuit serial programming PIC16F84A Watchdog Timer which shut only through configuration bits. runs oscillator added reliability. There timers that offer necessary delays power-up. Oscillator Start-up Timer (OST), intended keep
Configuration Bits
configuration bits programmed (read '0') left unprogrammed (read '1') select various device configurations. These bits mapped program memory location 2007h. Address 2007h beyond user program memory space belongs special test/configuration memory space (2000h 3FFFh). This space only accessed during programming.
FIGURE 6-1:
CONFIGURATION WORD PIC16F84A
R/P-u R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit0 Readable Programmable Value reset unchanged
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u bit13
13:4 Code Protection Code protection memory code protected PWRTE: Power-up Timer Enable Power-up timer disabled Power-up timer enabled WDTE: Watchdog Timer Enable enabled disabled FOSC1:FOSC0: Oscillator Selection bits oscillator oscillator oscillator oscillator
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PIC16F84A
6.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE
Ranges Tested: Mode
CAPACITOR SELECTION CERAMIC RESONATORS
PIC16F84A operated four different oscillator modes. user program configuration bits (FOSC1 FOSC0) select these four modes: Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR CERAMIC RESONATORS
Freq 10.0
OSC1/C1
OSC2/C2
Note
6.2.2
modes crystal ceramic resonator connected OSC1/CLKIN OSC2/CLKOUT pins establish oscillation (Figure 6-2).
Recommended values identical ranges tested table. Higher capacitance increases stability oscillator also increases start-up time. These values design guidance only. Since each resonator characteristics, user should consult resonator manufacturer appropriate values external components.
Resonators Tested:
FIGURE 6-2:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, CONFIGURATION)
OSC1 internal logic SLEEP PIC16FXX
C1(1)
10.0
Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA10.00MTZ
0.3% 0.5% 0.5% 0.5% 0.5%
None resonators built-in capacitors.
XTAL OSC2 C2(1) Note1: RS(2)
RF(3)
TABLE
Mode
CAPACITOR SELECTION CRYSTAL OSCILLATOR
Freq OSC1/C1 OSC2/C2
Table recommended values series resistor (RS) required strip crystals. varies with crystal chosen.
Note
PIC16F84A oscillator design requires parallel crystal. series crystal give frequency crystal manufacturers specifications. When modes, device have external clock source drive OSC1/CLKIN (Figure 6-3).
FIGURE 6-3:
EXTERNAL CLOCK INPUT OPERATION (HS, CONFIGURATION)
OSC1 PIC16FXX Open OSC2
Higher capacitance increases stability oscillator also increases start-up time. These values design guidance only. required mode well mode avoid overdriving crystals with drive level specification. Since each crystal characteristics, user should consult crystal manufacturer appropriate values external components. 4.5V, recommended.
Crystals Tested: 32.768 10.0 Epson C-001R32.768K-A Epson 100.00 KC-P 200.000 ECS-10-13-2 ECS-20-S-2 ECS-40-S-4 ECS-100-S-4
Clock from ext. system
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PIC16F84A
6.2.3 OSCILLATOR
Reset
timing insensitive applications device option offers additional cost savings. oscillator frequency function supply voltage, resistor (Rext) values, capacitor (Cext) values, operating temperature. addition this, oscillator frequency will vary from unit unit normal process parameter variation. Furthermore, difference lead frame capacitance between package types also affects oscillation frequency, especially Cext values. user needs take into account variation tolerance external components. Figure shows combination connected PIC16F84A.
PIC16F84A differentiates between various kinds reset: Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP Reset (during normal operation) Wake-up (during SLEEP)
Figure shows simplified block diagram on-chip reset circuit. MCLR reset path noise filter ignore small pulses. electrical specifications state pulse width requirements MCLR pin. Some registers affected reset condition; their status unknown reset unchanged other reset. Most other registers reset "reset state" POR, MCLR reset during normal operation MCLR reset during SLEEP. They affected reset during SLEEP, since this reset viewed resumption normal operation. Table gives description reset conditions program counter (PC) STATUS register. Table gives full description reset states registers. bits cleared differently different reset situations (Section 6.7). These bits used software determine nature reset.
FIGURE 6-4:
Rext
OSCILLATOR MODE
OSC1 Cext Fosc/4 Recommended values: OSC2/CLKOUT
Internal clock PIC16FXX
Rext Cext 20pF
FIGURE 6-5:
SIMPLIFIED BLOCK DIAGRAM ON-CHIP RESET CIRCUIT
External Reset
MCLR Module rise detect OST/PWRT 10-bit Ripple counter OSC1/ CLKIN PWRT On-chip OSC(1) 10-bit Ripple counter Chip_Reset SLEEP Time_Out Reset Power_on_Reset
Enable PWRT
Note This separate oscillator from oscillator CLKIN pin.
Table
Enable
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TABLE RESET CONDITION PROGRAM COUNTER STATUS REGISTER
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP Reset (during normal operation) Wake-up Interrupt wake-up from SLEEP Program Counter 000h 000h 000h 000h
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
Legend: unchanged, unknown. Note When wake-up interrupt set, loaded with interrupt vector (0004h).
TABLE
RESET CONDITIONS REGISTERS
MCLR Reset during: normal operation SLEEP Reset during normal operation uuuu uuuu -uuuu uuuu 0000h 000q quuu(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 000u -1111 1111 0000h 000q quuu
Register
Address
Power-on Reset
Wake-up from SLEEP: through interrupt through Time-out
INDF TMR0 STATUS PORTA
xxxx xxxx -xxxx xxxx 0000h 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 000x -1111 1111 0000h 0001 1xxx xxxx xxxx 1111 1111 1111 x000 0000 0000 000x
uuuu uuuu -uuuu uuuu 1(2) uuuq quuu(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) -uuuu uuuu uuuq quuu(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1)
PORTB
EEDATA EEADR PCLATH INTCON INDF OPTION_REG STATUS TRISA TRISB EECON1 EECON2 PCLATH INTCON
Legend: Note
uuuu uuuu 1111 1111 1111 q000 0000 0000 000u
unchanged, unknown, unimplemented read '0', value depends condition. more bits INTCON will affected cause wake-up). When wake-up interrupt set, loaded with interrupt vector (0004h). Table lists reset value each specific condition. device reset, these pins configured inputs. This value that will port output latch.
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PIC16F84A
Power-on Reset (POR) FIGURE 6-6:
Power-on Reset pulse generated on-chip when rise detected range 1.2V 1.7V). take advantage POR, just MCLR directly through resistor) VDD. This will eliminate external components usually needed create Power-on Reset. minimum rise time must this operate properly. Electrical Specifications details. When device starts normal operation (exits reset condition), device operating parameters (voltage, frequency, temperature, must meet ensure operation. these conditions met, device must held reset until operating conditions met. additional information, refer Application Note AN607, "Power-up Trouble Shooting." circuit does produce internal reset when declines.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW POWER-UP)
MCLR PIC16FXX
Power-up Timer (PWRT)
Power-up Timer (PWRT) provides fixed nominal time-out (TPWRT) from (Figure 6-7, Figure 6-8, Figure Figure 6-10). Power-up Timer operates internal oscillator. chip kept reset long PWRT active. PWRT delay allows rise acceptable level (Possible exception shown Figure 6-10). configuration bit, PWRTE, enable/disable PWRT. Figure operation PWRTE particular device. power-up time delay TPWRT will vary from chip chip VDD, temperature, process variation. parameters details.
Note External Power-on Reset circuit required only power-up rate slow. diode helps discharge capacitor quickly when powers down. recommended make sure that voltage drop across does exceed 0.2V (max leakage current spec MCLR µA). larger voltage drop will degrade level MCLR pin. will limit current flowing into MCLR from external capacitor event MCLR breakdown EOS.
Oscillator Start-up Timer (OST)
Oscillator Start-up Timer (OST) provides 1024 oscillator cycle delay (from OSC1 input) after PWRT delay ends (Figure 6-7, Figure 6-8, Figure Figure 6-10). This ensures crystal oscillator resonator started stabilized. time-out (TOST) invoked only modes only Power-on Reset wake-up from SLEEP. When rises very slowly, possible that TPWRT time-out TOST time-out will expire before reached final value. this case (Figure 6-10), external power-on reset circuit necessary (Figure 6-6).
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FIGURE 6-7: TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
FIGURE 6-8:
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR
INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
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FIGURE 6-9: TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): FAST RISE TIME
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
FIGURE 6-10: TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): SLOW RISE TIME
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET When rises very slowly, possible that TPWRT time-out TOST time-out will expire before reached final value. this example, chip will reset properly only min.
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PIC16F84A
Time-out Sequence Power-down Status Bits (TO/PD) Interrupts
PIC16F84A sources interrupt: External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt
power-up (Figure 6-7, Figure 6-8, Figure Figure 6-10) time-out sequence follows: First PWRT time-out invoked after expired. Then activated. total time-out will vary based oscillator configuration PWRTE configuration status. example, mode with PWRT disabled, there will time-out all.
TABLE
Oscillator Configuration
TIME-OUT VARIOUS SITUATIONS
Power-up PWRT PWRT Enabled Disabled 1024TOSC 1024TOSC Wake-up from SLEEP 1024TOSC
interrupt control register (INTCON) records individual interrupt requests flag bits. also contains individual global interrupt enable bits. global interrupt enable bit, (INTCON<7>) enables set) un-masked interrupts disables cleared) interrupts. Individual interrupts disabled through their corresponding enable bits INTCON register. cleared reset. "return from interrupt" instruction, RETFIE, exits interrupt routine well sets bit, which re-enable interrupts. RB0/INT interrupt, port change interrupt TMR0 overflow interrupt flags contained INTCON register. When interrupt responded cleared disable further interrupt, return address pushed onto stack loaded with 0004h. external interrupt events, such RB0/INT PORTB change interrupt, interrupt latency will three four instruction cycles. exact latency depends when interrupt event occurs. latency same both cycle instructions. Once interrupt service routine source(s) interrupt determined polling interrupt flag bits. interrupt flag bit(s) must cleared software before re-enabling interrupts avoid infinite interrupt requests. Note Individual interrupt flag bits regardless status their corresponding mask bit.
Since time-outs occur from reset pulse, MCLR kept long enough, time-outs will expire. Then bringing MCLR high, execution will begin immediately (Figure 6-7). This useful testing purposes synchronize more than PIC16F84A device when operating parallel. Table shows significance bits. Table lists reset conditions some special registers, while Table lists reset conditions registers.
TABLE
STATUS BITS THEIR SIGNIFICANCE
Condition Power-on Reset Illegal, Illegal, Reset (during normal operation) Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP interrupt wake-up from SLEEP
FIGURE 6-11: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE EEIF EEIE
Wake-up SLEEP mode)
Interrupt
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6.8.1 INTERRUPT 6.8.4 DATA EEPROM INTERRUPT External interrupt RB0/INT edge triggered: either rising INTEDG (OPTION_REG<6>) set, falling, INTEDG clear. When valid edge appears RB0/INT pin, INTF (INTCON<1>) set. This interrupt disabled clearing control INTE (INTCON<4>). Flag INTF must cleared software interrupt service routine before re-enabling this interrupt. interrupt wake processor from SLEEP (Section 6.11) only INTE prior going into SLEEP. status decides whether processor branches interrupt vector following wake-up. 6.8.2 TMR0 INTERRUPT completion data EEPROM write cycle, flag EEIF (EECON1<4>) will set. interrupt enabled/disabled setting/clearing enable EEIE (INTCON<6>) (Section 5.0).
Context Saving During Interrupts
During interrupt, only return value saved stack. Typically, users wish save register values during interrupt (e.g., register STATUS register). This implemented software. Example stores restores STATUS register's values. User defined registers, W_TEMP STATUS_TEMP temporary storage locations STATUS registers values. Example does following: Stores register. Stores STATUS register STATUS_TEMP. Executes Interrupt Service Routine code. Restores STATUS (and bank select bit) register. Restores register.
overflow (FFh 00h) TMR0 will flag T0IF (INTCON<2>). interrupt enabled/disabled setting/clearing enable T0IE (INTCON<5>) (Section 4.0). 6.8.3 PORB INTERRUPT
input change PORTB<7:4> sets flag RBIF (INTCON<0>). interrupt enabled/disabled setting/clearing enable RBIE (INTCON<3>) (Section 3.2). Note change recognized, pulse width must least wide.
EXAMPLE 6-1:
PUSH MOVWF SWAPF MOVWF SWAPF MOVWF SWAPF SWAPF
SAVING STATUS REGISTERS RAW_TEMP STATUS, STATUS_TEMP Copy TEMP register, Swap status saved into Save status STATUS_TEMP register Interrupt Service Routine should configure Bank required Swap nibbles STATUS_TEMP register place result into Move into STATUS register (sets bank original state) Swap nibbles W_TEMP place result W_TEMP Swap nibbles W_TEMP place result into
STATUS_TEMP, STATUS W_TEMP, W_TEMP,
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6.10 Watchdog Timer (WDT)
Watchdog Timer free running on-chip oscillator which does require external components. This oscillator separate from oscillator OSC1/CLKIN pin. That means that will even clock OSC1/CLKIN OSC2/CLKOUT pins device been stopped, example, execution SLEEP instruction. During normal operation time-out generates device RESET. device SLEEP mode, Wake-up causes device wake-up continue with normal operation. permanently disabled programming configuration WDTE (Section 6.1). 6.10.1 PERIOD part (see specs). longer time-out periods desired, prescaler with division ratio 1:128 assigned under software control writing OPTION_REG register. Thus, time-out periods seconds realized. CLRWDT SLEEP instructions clear postscaler assigned WDT) prevent from timing generating device RESET condition. STATUS register will cleared upon time-out. 6.10.2 PROGRAMMING CONSIDERATIONS
nominal time-out period (with prescaler). time-out periods vary with temperature, process variations from part
should also taken into account that under worst case conditions (VDD Min., Temperature Max., max. prescaler) take several seconds before time-out occurs.
FIGURE 6-12: WATCHDOG TIMER BLOCK DIAGRAFrom TMR0 Clock Source (Figure 4-2)
Timer
Postscaler PS2:PS0
Enable
TMR0 (Figure 4-2)
Time-out
Note: PS2:PS0 bits OPTION_REG register.
TABLE
Addr Name
SUMMARY REGISTERS ASSOCIATED WITH WATCHDOG TIMER
PWRTE(1) Value Power-on Reset 1111 1111 1111 1111 Value other resets
2007h
Config. bits OPTION_REG
RBPU
INTEDG
T0CS
T0SE
WDTE
FOSC1
FOSC0
Legend: unknown. Shaded cells used WDT. Note Figure operation PWRTE bit. Figure Section 6.12 operation Code Data protection bits.
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PIC16F84A
6.11 Power-down Mode (SLEEP)
6.11.2 WAKE-UP FROM SLEEP device powered down (SLEEP) later powered (Wake-up from SLEEP). 6.11.1 SLEEP device wake-up from SLEEP through following events: External reset input MCLR pin. Wake-up enabled). Interrupt from RB0/INT pin, port change, data EEPROM write complete.
Power-down mode entered executing SLEEP instruction. enabled, Watchdog Timer cleared (but keeps running), (STATUS<3>) cleared, (STATUS<4>) set, oscillator driver turned off. ports maintain status they before SLEEP instruction executed (driving high, low, hi-impedance). lowest current consumption SLEEP mode, place pins either VSS, with external circuitry drawing current from pins, disable external clocks. pins that hi-impedance inputs should pulled high externally avoid switching currents caused floating inputs. T0CKI input should also VSS. contribution from on-chip pull-ups PORTB should considered. MCLR must logic high level (VIHMC). should noted that RESET generated time-out does drive MCLR low.
Peripherals cannot generate interrupts during SLEEP, since on-chip clocks present. first event (MCLR reset) will cause device reset. latter events considered continuation program execution. bits used determine cause device reset. bit, which power-up, cleared when SLEEP invoked. cleared time-out occurred (and caused wake-up). While SLEEP instruction being executed, next instruction pre-fetched. device wake-up through interrupt event, corresponding interrupt enable must (enabled). Wake-up occurs regardless state bit. clear (disabled), device continues execution instruction after SLEEP instruction. (enabled), device executes instruction after SLEEP instruction then branches interrupt address (0004h). cases where execution instruction following SLEEP desirable, user should have after SLEEP instruction.
FIGURE 6-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC1 CLKOUT(4) INTF flag (INTCON<1>) (INTCON<7>) INSTRUCTION FLOW Instruction fetched Instruction executed Inst(PC) SLEEP Inst(PC PC+1 Inst(PC SLEEP PC+2 PC+2 Inst(PC Inst(PC Dummy cycle 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor SLEEP Interrupt Latency (Note TOST(2)
Note
oscillator mode assumed. TOST 1024TOSC (drawing scale) This delay will there mode. assumed. this case after wake- processor jumps interrupt routine. '0', execution will continue in-line. CLKOUT available these modes, shown here timing reference.
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6.11.3 WAKE-UP USING INTERRUPTS
6.14
In-Circuit Serial Programming
When global interrupts disabled (GIE cleared) interrupt source both interrupt enable interrupt flag set, following will occur: interrupt occurs before execution SLEEP instruction, SLEEP instruction will complete NOP. Therefore, postscaler will cleared, will bits will cleared. interrupt occurs during after execution SLEEP instruction, device will immediately wake from sleep. SLEEP instruction will completely executed before wake-up. Therefore, postscaler will cleared, will will cleared. Even flag bits were checked before executing SLEEP instruction, possible flag bits become before SLEEP instruction completes. determine whether SLEEP instruction executed, test bit. set, SLEEP instruction executed NOP. ensure that cleared, CLRWDT instruction should executed before SLEEP instruction.
PIC16F84A microcontrollers serially programmed while application circuit. This simply done with lines clock data, three other lines power, ground, programming voltage. Customers manufacture boards with unprogrammed devices, then program microcontroller just before shipping product, allowing most recent firmware custom firmware programmed. complete details serial programming, please refer In-Circuit Serial Programming (ICSPTM) Guide, (DS30277).
6.12
Program Verification/Code Protection
code protection bit(s) have been programmed, on-chip program memory read verification purposes. Note: Microchip does recommend code protecting windowed devices.
6.13
Locations
Four memory locations (2000h 2004h) designated locations store checksum other code identification numbers. These locations accessible during normal execution readable writable only during program/verify. Only four least significant bits location usable.
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PIC16F84A
INSTRUCTION SUMMARY
Each PIC16CXXX instruction 14-bit word divided into OPCODE which specifies instruction type more operands which further specify operation instruction. PIC16CXX instruction summary Table lists byte-oriented, bit-oriented, literal control operations. Table shows opcode field descriptions. byte-oriented instructions, represents file register designator represents destination designator. file register designator specifies which file register used instruction. destination designator specifies where result operation placed. zero, result placed register. one, result placed file register specified instruction. bit-oriented instructions, represents field designator which selects number affected operation, while represents number file which located. literal control operations, represents eight eleven constant literal value. Table lists instructions recognized MPASM assembler. Figure shows general formats that instructions have. Note: maintain upward compatibility with future PIC16CXXX products, OPTION TRIS instructions.
examples following format represent hexadecimal number: 0xhh where signifies hexadecimal digit.
FIGURE 7-1:
GENERAL FORMAT INSTRUCTIONS
Byte-oriented file register operations OPCODE (FILE destination destination 7-bit file register address Bit-oriented file register operations OPCODE (BIT (FILE 3-bit address 7-bit file register address Literal control operations General OPCODE 8-bit immediate value CALL GOTO instructions only OPCODE (literal) (literal)
TABLE
Field
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 0x7F) Working register (accumulator) address within 8-bit file register Literal field, constant data label Don't care location assembler will generate code with recommended form compatibility with Microchip software tools. Destination select; store result store result file register Default Program Counter Time-out Power-down
11-bit immediate value
instruction highly orthogonal grouped into three basic categories: Byte-oriented operations Bit-oriented operations Literal control operations instructions executed within single instruction cycle, unless conditional test true program counter changed result instruction. this case, execution takes instruction cycles with second cycle executed NOP. instruction cycle consists four oscillator periods. Thus, oscillator frequency MHz, normal instruction execution time conditional test true program counter changed result instruction, instruction execution time
description each instruction available PICmicroMid-Range Reference Manual, (DS33023).
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TABLE
Mnemonic, Operands
PIC16CXXX INSTRUCTION
Description Cycles BYTE-ORIENTED FILE REGISTER OPERATIONS 14-Bit Opcode Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF SUBWF SWAPF XORWF
with Clear Clear Complement Decrement Decrement Skip Increment Increment Skip Inclusive with Move Move Operation Rotate Left through Carry Rotate Right through Carry Subtract from Swap nibbles Exclusive with
1(2) 1(2)
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z
1,2,3 1,2,3
C,DC,Z
BIT-ORIENTED FILE REGISTER OPERATIONS BTFSC BTFSS Clear Test Skip Clear Test Skip 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff
LITERAL CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note literal literal with Call subroutine Clear Watchdog Timer address Inclusive literal with Move literal Return from interrupt Return with literal Return from Subroutine into standby mode Subtract from literal Exclusive literal with 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z TO,PD
TO,PD C,DC,Z
When register modified function itself e.g., MOVF PORTB, value used will that value present pins themselves. example, data latch configured input driven external device, data will written back with '0'. this instruction executed TMR0 register (and, where applicable, prescaler will cleared assigned Timer0 Module. Program Counter (PC) modified conditional test true, instruction requires cycles. second cycle executed NOP.
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PIC16F84A
DEVELOPMENT SUPPORT
Development Tools
ICEPIC: Low-Cost PICmicroIn-Circuit Emulator
PICmicrmicrocontrollers supported with full range hardware software development tools: MPLABTM-ICE Real-Time In-Circuit Emulator ICEPICLow-Cost PIC16C5X PIC16CXXX In-Circuit Emulator MATE® Universal Programmer PICSTART® Plus Entry-Level Prototype Programmer SIMICE PICDEM-1 Low-Cost Demonstration Board PICDEM-2 Low-Cost Demonstration Board PICDEM-3 Low-Cost Demonstration Board MPASM Assembler MPLABSIM Software Simulator MPLAB-C17 Compiler) Fuzzy Logic Development System (fuzzyTECH®-MP) KEELOQ® Evaluation Kits Programmer
ICEPIC low-cost in-circuit emulator solution Microchip PIC12CXXX, PIC16C5X PIC16CXXX families 8-bit microcontrollers. ICEPIC designed operate PC-compatible machines ranging from through Pentiumbased machines under Windows 3.x, Windows Windows environment. ICEPIC features real time, nonintrusive emulation.
MATE Universal Programmer
MATE Universal Programmer full-featured programmer capable operating stand-alone mode well PC-hosted mode. MATE compliant. MATE programmable supplies which allows verify programmed memory maximum reliability. display displaying error messages, keys enter commands modular detachable socket assembly support various package types. standalone mode MATE read, verify program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX PIC17CXX devices. also configuration code-protect bits this mode.
MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB
MPLAB-ICE Universal In-Circuit Emulator intended provide product development engineer with complete microcontroller design tool PICmicro microcontrollers (MCUs). MPLAB-ICE supplied with MPLAB Integrated Development Environment (IDE), which allows editing, "make" download, source debugging from single environment. Interchangeable processor modules allow system easily reconfigured emulation different processors. universal architecture MPLAB-ICE allows expansion support Microchip microcontrollers. MPLAB-ICE Emulator System been designed real-time emulation system with advanced features that generally found more expensive development tools. compatible (and higher) machine platform Microsoft Windows® Windows environment were chosen best make these features available you, user. MPLAB-ICE available versions. MPLAB-ICE 1000 basic, low-cost emulator system with simple trace capabilities. shares processor modules with MPLAB-ICE 2000. This full-featured emulator system with enhanced trace, trigger, data monitoring features. Both systems will operate across entire operating speed reange PICmicro MCU.
PICSTART Plus Entry Level Development System
PICSTART programmer easy-to-use, lowcost prototype programmer. connects (RS-232) ports. MPLAB Integrated Development Environment software makes using programmer simple efficient. PICSTART Plus recommended production programming. PICSTART Plus supports PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX PIC17CXX devices with pins. Larger count devices such PIC16C923, PIC16C924 PIC17C756 supported with adapter socket. PICSTART Plus compliant.
1998 Microchip Technology Inc.
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DS35007A-page
PIC16F84A
SIMICE Entry-Level Hardware Simulator PICDEM-2 Low-Cost PIC16CXX Demonstration Board
SIMICE entry-level hardware development system designed operate PC-based environment with Microchip's simulator MPLABTM-SIM. Both SIMICE MPLAB-SIM under Microchip Technology's MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation Microchip's PIC12C5XX, PIC12CE5XX, PIC16C5X families PICmicro8-bit microcontrollers. SIMICE works conjunction with MPLAB-SIM provide non-real-time port emulation. SIMICE enables developer simulator code driving target system. addition, target system provide input simulator code. This capability allows simple interactive debugging without having manually generate MPLAB-SIM stimulus files. SIMICE valuable debugging tool entrylevel system development.
PICDEM-2 simple demonstration board that supports PIC16C62, PIC16C64, PIC16C65, PIC16C73 PIC16C74 microcontrollers. necessary hardware software included basic demonstration programs. user program sample microcontrollers provided with PICDEM-2 board, MATE programmer PICSTART-Plus, easily test firmware. MPLAB-ICE emulator also used with PICDEM-2 board test firmware. Additional prototype area been provided user adding additional hardware connecting microcontroller socket(s). Some features include RS-232 interface, push-button switches, potentiometer simulated analog input, Serial EEPROM demonstrate usage separate headers connection module keypad.
PICDEM-1 Low-Cost PICmicro Demonstration Board
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
PICDEM-1 simple board which demonstrates capabilities several Microchip's microcontrollers. microcontrollers supported are: PIC16C5X (PIC16C54 PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 PIC17C44. necessary hardware software included basic demo programs. users program sample microcontrollers provided with PICDEM-1 board, MATE PICSTART-Plus programmer, easily test firmware. user also connect PICDEM-1 board MPLAB-ICE emulator download firmware emulator testing. Additional prototype area available user build some additional hardware connect microcontroller socket(s). Some features include RS-232 interface, potentiometer simulated analog input, push-button switches eight LEDs connected PORTB.
PICDEM-3 simple demonstration board that supports PIC16C923 PIC16C924 PLCC package. will also support future 44-pin PLCC microcontrollers with Module. necessary hardware software included basic demonstration programs. user program sample microcontrollers provided with PICDEM-3 board, MATE programmer PICSTART Plus with adapter socket, easily test firmware. MPLAB-ICE emulator also used with PICDEM-3 board test firmware. Additional prototype area been provided user adding hardware connecting microcontroller socket(s). Some features include RS-232 interface, push-button switches, potentiometer simulated analog input, thermistor separate headers connection external module keypad. Also provided PICDEM-3 board panel, with commons segments, that capable displaying time, temperature week. PICDEM-3 provides additional RS-232 interface Windows software showing demultiplexed signals simple serial interface allows user construct hardware demultiplexer signals.
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1998 Microchip Technology Inc.
PIC16F84A
8.10 MPLAB Integrated Development Environment Software 8.12 Software Simulator (MPLAB-SIM)
MPLAB-SIM Software Simulator allows code development host environment. allows user simulate PICmicro series microcontrollers instruction level. given instruction, user examine modify data areas provide external stimulus pins. input/ output radix user execution performed single step, execute until break, trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 MPASM. Software Simulator offers cost flexibility develop debug code outside laboratory environment making excellent multi-project software development tool.
MPLAB Software brings ease software development previously unseen 8-bit microcontroller market. MPLAB windows based application which contains: full featured editor Three operating modes editor emulator simulator project manager Customizable tool mapping status with project information Extensive on-line help MPLAB allows Edit your source files (either assembly `C') touch assemble compile) download PICmicro tools (automatically updates project information) Debug using: source files absolute listing file ability MPLAB with Microchip's simulator allows consistent platform ability easily switch from cost simulator full featured emulator with minimal retraining development tools.
8.13
MPLAB-C17 Compiler
MPLAB-C17 Code Development System complete ANSI compiler integrated development environment Microchip's PIC17CXXX family microcontrollers. compiler provides powerful integration capabilities ease found with other compilers. easier source level debugging, compiler provides symbol information that compatible with MPLAB memory display.
8.14
Fuzzy Logic Development System (fuzzyTECH-MP)
8.11
Assembler (MPASM)
MPASM Universal Macro Assembler PChosted symbolic assembler. supports microcontroller series including PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, several source listing formats. generates various object code formats support Microchip's development tools well third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip's Universal Emulator System. MPASM following features assist developing software specific applications. Provides translation Assembler source code object code Microchip microcontrollers. Macro assembly capability. Produces files (Object, Listing, Symbol, special) required symbolic debug with Microchip's emulator systems. Supports (default), Decimal Octal source listing formats. MPASM provides rich directive language support programming PICmicro. Directives helpful making development your assemble source code shorter more maintainable.
fuzzyTECH-MP fuzzy logic development tool available versions cost introductory version, Explorer, designers gain comprehensive working knowledge fuzzy logic system design; full-featured version, fuzzyTECH-MP, Edition implementing more complex systems.
Both versions include Microchip's fuzzyLABdemonstration board hands-on experience with fuzzy logic systems implementation.
8.15
SEEVAL® Evaluation Programming System
SEEVAL SEEPROM Designer's supports Microchip 2-wire 3-wire Serial EEPROMs. includes everything necessary read, write, erase program special features Microchip SEEPROM product including Smart Serialsand secure serials. Total EnduranceDisk included tradeoff analysis reliability calculations. total significantly reduce time-to-market result optimized system.
1998 Microchip Technology Inc.
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Preliminary
DS35007A-page
PIC16F84A
8.16 KEELOQ® Evaluation Programming Tools
KEELOQ evaluation programming tools support Microchips Secure Data Products. evaluation includes display show changing codes, decoder decode transmissions, programming interface program test transmitters.
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1998 Microchip Technology Inc.
Software Tools
Programmers
Demo Boards
1998 Microchip Technology Inc.
TABLE 8-1:
PIC12C5XX Emulator Products
PIC14000
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
MPLABTM-ICE
DEVELOPMENT TOOLS FROM MICROCHIP
ICEPICLow-Cost In-Circuit Emulator MPLABIntegrated Development Environment MPLABC17* Compiler
fuzzyTECH®-MP
Explorer/Edition Fuzzy Logic Dev. Tool Total EnduranceSoftware Model PICSTART®Plus Low-Cost Universal Dev. MATE® Universal Programmer KEELOQ® Programmer SEEVAL® Designers SIMICE PICDEM-14A PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ® Evaluation KEELOQ Transponder
Preliminary
DS35007A-page
PIC16F84A
PIC16F84A
NOTES:
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PIC16F84A
ELECTRICAL CHARACTERISTICS PIC16F84A
Absolute Maximum Ratings Ambient temperature under bias.-55°C +125°C Storage temperature -65°C +150°C Voltage with respect (except VDD, MCLR, RA4). -0.3V (VDD 0.3V) Voltage with respect -0.3 +7.5V Voltage MCLR with respect VSS(1) -0.3 +14V Voltage with respect -0.3 +8.5V Total power dissipation(2) .800 Maximum current .150 Maximum current into .100 Input clamp current, VDD).± Output clamp current, VDD) Maximum output current sunk pin.25 Maximum output current sourced Maximum current sunk PORTA Maximum current sourced PORTA Maximum current sunk PORTB.150 Maximum current sourced PORTB.100 Note Voltage spikes below MCLR pin, inducing currents greater than cause latch-up. Thus, series resistor 50-100 should used when applying "low" level MCLR rather than pulling this directly VSS. Note Power dissipation calculated follows: Pdis {IDD IOH} {(VDD-VOH) IOH} (VOl IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operation listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
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DS35007A-page
PIC16F84A
TABLE CROSS REFERENCE DEVICE SPECS OSCILLATOR CONFIGURATIONS FREQUENCIES OPERATION (COMMERCIAL DEVICES)
PIC16F84A-04
VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V 5.5V max. 5.5V max. max. 4.0V 5.5V max. 5.5V max. max. 4.5V 5.5V typ. 5.5V typ. 4.5V, max. 4.5V 4.0V 5.5V typ. kHz, 2.0V typ. 3.0V, max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
PIC16F84A-20
4.5V 5.5V typ. 5.5V typ. 5.5V, max. 4.5V 5.5V typ. 5.5V typ. 5.5V, max. 4.5V 4.5V 5.5V max. 5.5V typ. typ. 4.5V, max. 4.5V VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
PIC16LF84A-04
2.0V 5.5V max. 5.5V max. max. 2.0V 5.5V max. 5.5V max. max.
mode
mode
VDD: IDD: IPD: Freq:
2.0V 5.5V max. kHz, 2.0V max. 2.0V max.
shaded sections indicate oscillator selections which tested functionality, MIN/MAX specifications. recommended that user select device type that ensures specifications required.
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1998 Microchip Technology Inc.
PIC16F84A
CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature +70°C (commercial) -40°C +85°C (industrial) Units Conditions 1.5* configuration configuration Device SLEEP mode section Power-on Reset details
Characteristics Power Supply Pins
Parameter
VPOR
Characteristic Supply Voltage Data Retention Voltage (Note Start Voltage ensure internal Power-on Reset signal Rise Rate ensure internal Power-on Reset signal Supply Current (Note
D001 D001A D002* D003
D004* D004A*
SVDD
0.05*
D010 D010A
D013 D020 D021 D021A
Power-down Current (Note
V/ms PWRT enabled (PWRTE clear) PWRT disabled (PWRTE set) section Power-on Reset details configuration (Note FOSC MHz, 5.5V FOSC MHz, 5.5V (During Flash programming) configuration (PIC16F84A-20) FOSC MHz, 5.5V 4.0V, enabled, industrial 4.0V, disabled, commercial 4.0V, disabled, industrial
D022*
WDTE set, 4.0V, commercial WDTE set, 4.0V, extended These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. Note This limit which lowered without losing data. supply current mainly function operating voltage frequency. Other factors such loading switching rate, oscillator type, internal code execution pattern, temperature also have impact current consumption. test conditions measurements active operation mode are: OSC1=external square wave, from rail rail; pins tristated, pulled VDD, T0CKI VDD, MCLR VDD; enabled/disabled specified. power down current SLEEP mode does depend oscillator type. Power-down current measured with part SLEEP mode, with pins hi-impedance state tied VSS. configuration, current through Rext included. current through resistor estimated formula VDD/2Rext (mA) with Rext kOhm. current additional current consumed when this peripheral enabled. This current should added base measurement.
Module Differential Current (Note IWDT Watchdog Timer
1998 Microchip Technology Inc.
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Preliminary
DS35007A-page
PIC16F84A
CHARACTERISTICS: PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature +70°C (commercial) -40°C +85°C (industrial) Units Conditions 1.5* configuration Device SLEEP mode section Power-on Reset details Characteristics Power Supply Pins
Parameter
VPOR
Characteristic Supply Voltage Data Retention Voltage (Note Start Voltage ensure internal Power-on Reset signal Rise Rate ensure internal Power-on Reset signal Supply Current (Note
D001 D002* D003
D004* D004A*
SVDD
0.05*
D010 D010A
D014 D020 D021 D021A Power-down Current (Note
V/ms PWRT enabled (PWRTE clear) PWRT disabled (PWRTE set) section Power-on Reset details configuration (Note FOSC MHz, 5.5V FOSC MHz, 5.5V (During Flash programming) configuration FOSC kHz, 2.0V, disabled 2.0V, enabled, industrial 2.0V, disabled, commercial 2.0V, disabled, industrial
D022*
WDTE set, 4.0V, commercial WDTE set, 4.0V, industrial These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. Note This limit which lowered SLEEP mode without losing data. supply current mainly function operating voltage frequency. Other factors such loading switching rate, oscillator type, internal code execution pattern, temperature also have impact current consumption. test conditions measurements active operation mode are: OSC1=external square wave, from rail rail; pins tristated, pulled VDD, T0CKI VDD, MCLR VDD; enabled/disabled specified. power down current SLEEP mode does depend oscillator type. Power-down current measured with part SLEEP mode, with pins hi-impedance state tied VSS. configuration, current through Rext included. current through resistor estimated formula VDD/2Rext (mA) with Rext kOhm. current additional current consumed when this peripheral enabled. This current should added base measurement.
Module Differential Current (Note IWDT Watchdog Timer
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Preliminary
1998 Microchip Technology Inc.
PIC16F84A
CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature +70°C (commercial) -40°C +85°C (industrial) Operating voltage range described spec Section Section 9.2.
Characteristics Pins Except Power Supply Pins
Parameter
Characteristic Input Voltage ports with buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, modes) OSC1 mode) Input High Voltage ports with buffer
Units
Conditions
D030 D030A D031 D032 D033 D034 D040 D040A D041 D042 D043 D043A D050 D070
0.16VDD 0.2VDD 0.2VDD 0.3VDD 0.1VDD
4.5V 5.5V (Note entire range (Note entire range (Note
VHYS IPURB
D060 D061 D063
with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, modes) OSC1 mode) Hysteresis Schmitt Trigger inputs PORTB weak pull-up current Input Leakage Current (Note 2,3) ports MCLR, RA4/T0CKI OSC1
0.25VDD +0.8
4.5V 5.5V (Note entire range (Note entire range
250*
(Note
400*
5.0V, VPIN
VPIN VDD, hi-impedance VPIN VPIN VDD, configuration
These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. Note oscillator configuration, OSC1 Schmitt Trigger input. drive PIC16F84A with external clock while device mode, chip damage result. leakage current MCLR strongly dependent applied voltage level. specified levels represent normal operating conditions. Higher leakage current measured different input voltages. Negative current defined coming pin. user choose better specs.
1998 Microchip Technology Inc.
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DS35007A-page
PIC16F84A
CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature +70°C (commercial) -40°C +85°C (industrial) Operating voltage range described spec Section Section 9.2. Units Conditions
Characteristics Pins Except Power Supply Pins
Parameter
Characteristic Output Voltage ports OSC2/CLKOUT Output High Voltage ports (Note OSC2/CLKOUT (Note Open Drain High Voltage Capacitive Loading Specs Output Pins OSC2
D080 D083
4.5V 4.5V, Mode Only) -3.0 4.5V -1.3 4.5V Mode Only)
D090 D092
VDD-0.7 VDD-0.7
D150
D100
COSC2
modes when external clock used drive OSC1.
D101
pins OSC2 mode) Data EEPROM Memory Endurance read/write Erase/Write cycle time Program Flash Memory Endurance read
D120 D121 D122 D130 D131
VDRW TDEW
VMIN 100* VMIN
1000
25°C VMIN Minimum operating voltage VMIN Minimum operating voltage
D132 VPEW erase/write D133 TPEW Erase/Write cycle time These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. Note oscillator configuration, OSC1 Schmitt Trigger input. drive PIC16F84A with external clock while device mode, chip damage result. leakage current MCLR strongly dependent applied voltage level. specified levels represent normal operating conditions. Higher leakage current measured different input voltages. Negative current defined coming pin. user choose better specs.
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1998 Microchip Technology Inc.
PIC16F84A
9.5.1
(Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
timing parameter symbols have been created following following formats: TppS2ppS TppS Frequency Lowercase symbols (pp) their meanings: CLKOUT cycle time port MCLR Uppercase symbols their meanings: Fall High Invalid (Hi-impedance)
Time
os,osc pwrt
OSC1 oscillator start-up timer power-up timer pins T0CKI watchdog timer
Period Rise Valid High Impedance
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DS35007A-page
PIC16F84A
9.5.2 TIMING CONDITIONS temperature voltages specified Table apply timing specifications unless otherwise noted. timings measure between high measurement points indicated Figure 9-1. Figure specifies load conditions timing specifications.
TABLE
TEMPERATURE VOLTAGE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature +70°C commercial -40°C +85°C industrial Operating voltage range described spec Section Section
CHARACTERISTICS
FIGURE 9-1:
PARAMETER MEASUREMENT INFORMATION
XTAL (High) XTAL 0.15 (Low) (High) (Low) Port Measurement Points
OSC1 Measurement Points
FIGURE 9-2:
LOAD CONDITIONS
Load Condition VDD/2 Load Condition
pins except OSC2. OSC2 output.
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1998 Microchip Technology Inc.
PIC16F84A
9.5.3 TIMING DIAGRAMS SPECIFICATIONS
FIGURE 9-3:
EXTERNAL CLOCK TIMING
OSC1 CLKOUT
TABLE
Parameter
EXTERNAL CLOCK TIMING REQUIREMENTS
FOSC Characteristic External CLKIN Frequency(1) 4/Fosc 10,000 10,000 1,000 Units Conditions (-04, (-04) (-20) (-04, (-04, (-04) (-04, (-04) (-20) (-04, (-04, (-04) (-20) (-04, (-04, (-04) (-04, (-04) (-20) (-04, (-04, (-04) (-04, (-20) (-04) (-04, (-20)
Oscillator Frequency(1)
Tosc
External CLKIN Period(1)
Oscillator Period(1)
TosL, TosH
Instruction Cycle Time(1) Clock (OSC1) High Time
TosR, TosF
Clock (OSC1) Rise Fall Time
These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. Note Instruction cycle period (TCY) equals four times input oscillator time-base period. specified values based characterization data that particular oscillator type under standard operating conditions with device executing code. Exceeding these specified limits result unstable oscillator operation and/or higher than expected current consumption. devices tested operate "min." values with external clock applied OSC1 pin. When external clock input used, "Max." cycle time limit "DC" clock) devices.
1998 Microchip Technology Inc.
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PIC16F84A
FIGURE 9-4: CLKOUT TIMING
OSC1 CLKOUT (input) (output) value value
Note: tests must done with specified capacitive loads (Figure 9-2) pins CLKOUT.
TABLE
Parameter TckF TckR
CLKOUT TIMING REQUIREMENTS
TosH2ckL Characteristic OSC1 CLKOUT Standard Extended (LF) TosH2ckH OSC1 CLKOUT CLKOUT rise time CLKOUT fall time Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI CLKOUT Port valid Port valid before CLKOUT OSC1 cycle) Port valid OSC1 cycle) Port input invalid (I/O hold time) Port input valid OSC1 (I/O setup time) Port output rise time Port output fall time high time Trbp RB7:RB4 change high time Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) TioF Tinp Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) 0.30TCY 0.30TCY -175 TOSC TOSC 0.5TCY Units Conditions Note Note Note Note Note Note Note Note Note Note Note Note
Port hold after CLKOUT
TioV2osH
TioR
These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested. design Note Measurements taken Mode where CLKOUT output TOSC.
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PIC16F84A
FIGURE 9-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER POWER-UP TIMER TIMING
MCLR Internal PWRT Time-out Time-out Internal RESET Watchdog Timer RESET Pins
TABLE
Parameter
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER POWER-UP TIMER REQUIREMENTS
TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period Prescaler) Oscillation Start-up Timer Period Power-up Timer Period Hi-impedance from MCLR reset 1024TOSC Units Conditions
5.0V, extended 5.0V, extended
TOSC OSC1 period
5.0V, extended
These parameters characterized tested. Data "Typ" column 25°C unless otherwise stated. These parameters design guidance only tested.
1998 Microchip Technology Inc.
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DS35007A-page
PIC16F84A
FIGURE 9-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
TABLE
Parameter
TIMER0 CLOCK REQUIREMENTS
Characteristic 0.5TCY 0.5TCY Units 2.0V 3.0V 3.0V 6.0V prescale value 256) 2.0V 3.0V 3.0V 6.0V Conditions
Tt0H T0CKI High Pulse Width Prescaler With Prescaler
Tt0L T0CKI Pulse Width Prescaler With Prescaler
Tt0P T0CKI Period
These parameters characterized tested. Data "Typ" column 5.0V, 25°C unless otherwise stated. These parameters design guidance only tested.
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Preliminary
1998 Microchip Technology Inc.
PIC16F84A
10.0 CHARACTERISTICS GRAPHS/TABLES
data available this time.
1998 Microchip Technology Inc.
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Preliminary
DS35007A-page
PIC16F84A
NOTES:
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1998 Microchip Technology Inc.
PIC16F84A
11.0
11.1
PACKAGING INFORMATION
Package Marking Information
PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE
Example
PIC16F84A-04I/P 9832SAW
SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX
Example
PIC16F84A-04
AABBCDE
9848SAN
SSOP
XXXXXXXXXX XXXXXXXXXX
Example
PIC16F84A20/SS
AABBCDE
9822CAN
Legend: MM.M XX.X
Note:
Microchip part number information Customer specific information* Year code (last digits calendar year) Week code (week January week `01') Facility code plant which wafer manufactured Outside Vendor Line Line Line Mask revision number Assembly code plant country origin which part assembled
event full Microchip part number cannot marked line, will carried over next line thus limiting number available characters customer specific information.
Standard marking consists Microchip part number, year code, week code, facility code, mask rev#, assembly code. marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. devices, special marking adders included price.
1998 Microchip Technology Inc.
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Preliminary
DS35007A-page
PIC16F84A
11.2 K04-007 18-Lead Plastic Dual In-line
Units Dimension Limits Spacing Number Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Seating Plane Lead Seating Plane Base Seating Plane Seating Plane Package Length Molded Package Width Radius Radius Width Overall Spacing Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter.
INCHES* 0.300 0.100 0.013 0.018 0.055 0.060 0.000 0.005 0.005 0.010 0.110 0.155 0.075 0.095 0.000 0.020 0.125 0.130 0.890 0.895 0.245 0.255 0.230 0.250 0.310 0.349
0.023 0.065 0.010 0.015 0.155 0.115 0.020 0.135 0.900 0.265 0.270 0.387
MILLIMETERS 7.62 2.54 0.33 0.46 0.58 1.40 1.52 1.65 0.00 0.13 0.25 0.13 0.25 0.38 2.79 3.94 3.94 1.91 2.41 2.92 0.00 0.51 0.51 3.18 3.30 3.43 22.61 22.73 22.86 6.22 6.48 6.73 5.84 6.35 6.86 7.87 8.85 9.83
Dimension "B1" does include dam-bar protrusions. Dam-bar protrusions shall exceed 0.003" (0.076 side 0.006" (0.152 more than dimension "B1." Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010" (0.254 side 0.020" (0.508 more than dimensions "E."
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Preliminary
1998 Microchip Technology Inc.
PIC16F84A
11.3 K04-051 18-Lead Plastic Small Outline (SO) Wide,
Units Dimension Limits Pitch Number Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Mold Draft Angle Bottom
MILLIMETERS 1.27 2.64 2.36 2.50 1.73 1.22 1.47 0.28 0.10 0.19 11.73 11.43 11.58 7.59 7.42 7.51 10.64 10.01 10.33 0.74 0.25 0.50 0.25 0.13 0.13 0.25 0.13 0.13 0.53 0.28 0.41 0.51 0.25 0.38 0.30 0.23 0.27 0.48 0.36 0.42
INCHES* 0.050 0.093 0.099 0.048 0.058 0.004 0.008 0.450 0.456 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.016 0.011 0.015 0.010 0.011 0.009 0.017 0.014
0.104 0.068 0.011 0.462 0.299 0.419 0.029 0.010 0.010 0.021 0.020 0.012 0.019
Controlling Parameter. Dimension does include dam-bar protrusions. Dam-bar protrusions shall exceed 0.003" (0.076 side 0.006" (0.152 more than dimension "B." Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010" (0.254 side 0.020" (0.508 more than dimensions "E."
1998 Microchip Technology Inc.
This Material Copyrighted Respective Manufacturer
Preliminary
DS35007A-page
PIC16F84A
11.4 K04-072 20-Lead Plastic Shrink Small Outine (SS) 5.30
Units Dimension Limits Pitch Number Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Mold Draft Angle Bottom
INCHES 0.026 0.073 0.068 0.026 0.036 0.002 0.005 0.278 0.283 0.205 0.208 0.301 0.306 0.005 0.005 0.005 0.005 0.015 0.020 0.000 0.005 0.005 0.007 0.010 0.012
0.078 0.046 0.008 0.289 0.212 0.311 0.010 0.010 0.025 0.010 0.009 0.015
MILLIMETERS* 0.65 1.73 1.86 1.99 0.66 0.91 1.17 0.05 0.13 0.21 7.07 7.20 7.33 5.20 5.29 5.38 7.65 7.78 7.90 0.13 0.13 0.25 0.13 0.13 0.25 0.38 0.51 0.64 0.00 0.13 0.25 0.13 0.18 0.22 0.25 0.32 0.38
Controlling Parameter. Dimension does include dam-bar protrusions. Dam-bar protrusions shall exceed 0.003" (0.076 side 0.006" (0.152 more than dimension "B." Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010" (0.254 side 0.020" (0.508 more than dimensions "E."
DS35007A-page
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Preliminary
1998 Microchip Technology Inc.
PIC16F84A
APPENDIX REVISION HISTORY
Version Date 9/14/98 Revision Description This data sheet. However, devices described this data sheet upgrades devices found PIC16F8X Data Sheet, DS30430C.
APPENDIX CONVERSION CONSIDERATIONS
Considerations converting from PIC16X8X device another listed Table B-1.
TABLE B-1:
CONVERSION CONSIDERATIONS PIC16C84, PIC16F83/F84, PIC16CR83/CR84, PIC16F84A PIC16C84
2.0V 6.0V (-40°C +85°C) 10MHz (typ) 60µA (max) 400µA osc, FOSC 32kHz, 2.0V, disabled) (typ) 26µA (max) 100µA (VDD 2.0V, disabled, industrial)
Difference
Program Memory size Data Memory size Voltage Range Maximum Operating Frequency Supply Current (IDD). parameter D014 electrical spec's more detail. Power-down Current (IPD). parameters D020, D021, D021A electrical spec's more detail. Input Voltage (VIL). parameters D032 D034 electrical spec's more detail. Input High Voltage (VIH). parameter D040 electrical spec's more detail. Data EEPROM Memory Erase/Write cycle time (TDEW). parameter D122 electrical spec's more detail.
PIC16F83/F84
2.0V 6.0V (-40°C +85°C) 10MHz (typ) 15µA (max) 45µA osc, FOSC 32kHz, 2.0V, disabled) (typ) 0.4µA (max) (VDD 2.0V, disabled, industrial)
PIC16CR83/ CR84
2.0V 6.0V (-40°C +85°C) 10MHz (typ) 15µA (max) 45µA osc, FOSC 32kHz, 2.0V, disabled) (typ) 0.4µA (max) (VDD 2.0V, disabled, industrial)
PIC16F84A
2.0V 5.5V (-40°C +125°C) 20MHz (typ) 15µA (max) 45µA osc, FOSC 32kHz, 2.0V, disabled) (typ) 0.4µA (max) (VDD 2.0V, disabled, industrial)
(max) 0.2VDD (Osc1, mode)
(max) 0.1VDD (Osc1, mode)
(max) 0.1VDD (Osc1, mode)
(max) 0.1VDD (Osc1, mode)
(min) 0.36VDD (I/O Ports with TTL, 4.5V 5.5V)
(min) 2.4V (I/O Ports with TTL, 4.5V 5.5V)
(min) 2.4V (I/O Ports with TTL, 4.5V 5.5V)
(min) 2.4V (I/O Ports with TTL, 4.5V 5.5V)
TDEW (typ) 10ms TDEW (max) 20ms
TDEW (typ) 10ms TDEW (max) 20ms
TDEW (typ) 10ms TDEW (max) 20ms
TDEW (typ) TDEW (max) 10ms
1998 Microchip Technology Inc.
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Preliminary
DS35007A-page
PIC16F84A
TABLE B-1: CONVERSION CONSIDERATIONS PIC16C84, PIC16F83/F84, PIC16CR83/CR84, PIC16F84A PIC16C84
TioR, TioF (max) 25ns (C84) TioR, TioF (max) 60ns (LC84)
Difference
Port Output Rise/Fall time (TioR, TioF). parameters #20, 20A, electrical spec's more detail. MCLR on-chip filter. parameter electrical spec's more detail. PORTA crystal oscillator values less than 500kHz
PIC16F83/F84
TioR, TioF (max) 35ns (C84) TioR, TioF (max) 70ns (LC84)
PIC16CR83/ CR84
TioR, TioF (max) 35ns (C84) TioR, TioF (max) 70ns (LC84)
PIC16F84A
TioR, TioF (max) 35ns (C84) TioR, TioF (max) 70ns (LC84)
crystal oscillator configurations operating below 500kHz, device generate spurious internal Q-clock when PORTA<0> switches state. recommended that EEADR<7:6> bits cleared. When either these bits set, maximum device higher than when both cleared. PWRTE REXT 100k
RB0/INT EEADR<7:6>
TTL/ST* Schmitt Trigger)
TTL/ST* Schmitt Trigger)
TTL/ST* Schmitt Trigger)
polarity PWRTE Recommended value REXT oscillator circuits unintentional enable
PWRTE REXT 100k
PWRTE REXT 100k
PWRTE REXT 100k
interrupt occurs while Global Interrupt Enable (GIE) being cleared, unintentionally re-enabled user's Interrupt Service Routine (the RETFIE instruction). PDIP, SOIC
Packages
PDIP, SOIC
PDIP, SOIC
PDIP, SOIC, SSOP
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Preliminary
1998 Microchip Technology Inc.
PIC16F84A
NOTES:
1998 Microchip Technology Inc.
This Material Copyrighted Respective Manufacturer
Preliminary
DS35007A-page
PIC16F84A
APPENDIX MIGRATION FROM BASELINE MIDRANGE DEVICES
This section discusses migrate from baseline device (i.e., PIC16C5X) midrange device (i.e., PIC16CXXX). following list feature improvements over PIC16C5X microcontroller family: Instruction word length increased bits. This allows larger page sizes both program memory opposed before) register file (128 bytes versus bytes before). latch register (PCLATH) added handle program memory paging. PA2, bits removed from status register placed option register. Data memory paging redefined slightly. STATUS register modified. Four instructions have been added: RETURN, RETFIE, ADDLW, SUBLW. instructions, TRIS OPTION, being phased although they kept compatibility with PIC16C5X. OPTION TRIS registers made addressable. Interrupt capability added. Interrupt vector 0004h. Stack size increased deep. Reset vector changed 0000h. Reset registers revisited. Five different reset (and wake-up) types recognized. Registers reset differently. Wake from SLEEP through interrupt added. separate timers, Oscillator Start-up Timer (OST) Power-up Timer (PWRT), included more reliable power-up. These timers invoked selectively avoid unnecessary delays power-up wake-up. PORTB weak pull-ups interrupt change features. T0CKI also port (RA4/T0CKI). full 8-bit register. system programming" made possible. user program PIC16CXX devices using only five pins: VDD, VSS, VPP, (clock) (data in/out). convert code written PIC16C5X PIC16F84A, user should take following steps: Remove program memory page select operations (PA2, PA1, bits) CALL, GOTO. Revisit computed jump operations (write etc.) make sure page bits properly under scheme. Eliminate data memory page switching. Redefine data variables reallocation. Verify writes STATUS, OPTION, registers since these have changed. Change reset vector 0000h.
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1998 Microchip Technology Inc.
PIC16F84A
INDEX
Absolute Maximum Ratings (Timing) Characteristics Architecture, Block Diagram Assembler MPASM Assembler INTCON Register EEIE INTE INTF RBIE RBIF T0IE T0IF Interrupt Sources Block Diagram Data EEPROM Write Complete Interrupt Change (RB7:RB4) RB0/INT Pin, External TMR0 Overflow Interrupts, Context Saving During Interrupts, Enable Bits Data EEPROM Write Complete Enable (EEIE Bit) Global Interrupt Enable (GIE Bit) Interrupt Change (RB7:RB4) Enable (RBIE Bit) RB0/INT Enable (INTE Bit) TMR0 Overflow Enable (T0IE Bit) Interrupts, Flag Bits Data EEPROM Write Complete Flag (EEIF Bit) Interrupt Change (RB7:RB4) Flag (RBIF Bit) RB0/INT Flag (INTF Bit) TMR0 Overflow Flag (T0IF Bit)
Banking, Data Memory
CLKIN CLKOUT Code Protection Configuration Bits Conversion Considerations
Data EEPROM Memory EEADR Register EECON1 Register EECON2 Register EEDATA Register Write Complete Enable (EEIE Bit) Write Complete Flag (EEIF Bit) Data EEPROM Write Complete Data Memory Bank Select (RP0 Bit) Banking Characteristics Graphs/Tables Characteristics Development Support Development Tools
KeeLoq® Evaluation Programming Tools
Master Clear (MCLR) MCLR MCLR Reset, Normal Operation MCLR Reset, SLEEP Memory Organization Data EEPROM Memory Data Memory Program Memory Migration from Baseline Midrange Devices MPLAB Integrated Development Environment Software
EECON1 Register EEIF WREN WRERR Electrical Characteristics Endurance Errata External Power-on Reset Circuit
Firmware Instructions site Fuzzy Logic Dev. System (fuzzyTECH®-MP)
On-Line Support OPCODE Field Descriptions OPTION_REG Register INTEDG PS2:PS0 Bits RBPU T0CS T0SE OSC1 OSC2 Oscillator Configuration Selection (FOSC1:FOSC0 Bits)
Ports ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator Locations In-Circuit Serial Programming (ICSP) Indirect Addressing Register INDF Register Instruction Format Instruction Summary Table Interrupt (RB0/INT)
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PIC16F84A
Packaging PICDEM-1 Low-Cost PICmicro Demo Board PICDEM-2 Low-Cost PIC16CXX Demo Board PICDEM-3 Low-Cost PIC16CXXX Demo Board PICSTART® Plus Entry Level Development System Pinout Descriptions Pointer, PORTA Initializing PORTA Register RA3:RA0 Block Diagram Block Diagram RA4/T0CKI TRISA Register PORTB Initializing PORTB Register Pull-up Enable (RBPU Bit) RB0/INT Edge Select (INTEDG Bit) RB0/INT Pin, External RB3:RB0 Block Diagram RB7:RB4 Block Diagram RB7:RB4 Interrupt Change RB7:RB4 Interrupt Change Enable (RBIE Bit) RB7:RB4 Interrupt Change Flag (RBIF Bit) TRISB Register Power-on Reset (POR) Oscillator Start-up Timer (OST) Power-up Timer (PWRT) PWRT Enable (PWRTE Bit) Time-out Sequence Time-out Sequence Power-up Prescaler Assignment (PSA Bit) Block Diagram Rate Select (PS2:PS0 Bits) Switching Prescaler Assignment MATE® Universal Programmer Product Identification System Program Counter Register PCLATH Register Reset Conditions Program Memory General Purpose Registers Interrupt Vector Reset Vector Special Function Registers Programming, Device Instructions
Saving Register STATUS SEEVAL® Evaluation Programming System SLEEP Software Simulator (MPLAB-SIM) Special Features Special Function Registers Speed, Operating Stack STATUS Register Reset Conditions
Time-out (TO) Bit. Power-on Reset (POR) Timer0 Block Diagram Clock Source Edge Select (T0SE Bit) Clock Source Select (T0CS Bit) Overflow Enable (T0IE Bit) Overflow Flag (T0IF Bit) Overflow Interrupt RA4/T0CKI Pin, External Clock TMR0 Register Timing Diagrams Diagrams Specifications Time-out Sequence Power-up
Register Wake-up from SLEEP Interrupts MCLR Reset Reset Watchdog Timer (WDT) Block Diagram Enable (WDTE Bit) Programming Considerations Oscillator Time-out Period Reset, Normal Operation Reset, SLEEP WWW, On-Line Support
RAM. Data Memory Reader Response Register File Reset Block Diagram Reset Conditions Registers Reset Conditions Program Counter Reset Conditions STATUS Register Reset. Watchdog Timer (WDT) Revision History
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