128M-BIT MASK WITH PAGE MODE organization (byte mode) (double wor

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128M-BIT MASK WITH PAGE MODE organization (byte mode) (double wor

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MX23L12822
128M-BIT MASK WITH PAGE MODE
organization (byte mode) (double word mode) Fast access time Random access: 120ns (max.) Page access: 30ns (max.) Page Size double words page Current Operating: 75mA (max.) Standby: 15uA (max.) Supply voltage 3.3V±10% Package SSOP (500 mil) TSOP(2)
CONFIGURATION
SSOP
WORD D31/A-1
TSOP
WORD D31/A-1
MX23L12822
P/N:PM0561
MX23L12822
REV. 1.5, DEC. 2000
MX23L12822
ORDER INFORMATION
Part MX23L12822MC-12 MX23L12822YC-12 Access Time 120ns 120ns Page Access Time 30ns 30ns Package SSOP TSOP
DESCRIPTION
Symbol A0~A21 D0~D30 D31/A-1 Word Function Address Inputs Data Outputs (Double Word Mode)/ Address (Word Mode) Chip Enable Input Output Enable Input Double Word/ Word Mode Selection Power Supply Ground Connection
MODE SELECTION Word D31/A-1 Output Input D0~D15 High High D0~D15 D0~D15 D16~D31 High High D16~D31 High Mode Double Word Word Power Stand-by Active Active Active
P/N:PM0561
REV. 1.5, DEC. 2000
MX23L12822
BLOCK DIAGRAM
A0/(A-1) WORD Address Buffer Memory Array Page Buffer Page Decoder Double Word/ Word Output Buffer D31/(D15)
ABSOLUTE MAXIMUM RATINGS
Item Voltage Relative Ambient Operating Temperature Storage Temperature Symbol Topr Tstg Ratings -1.3V 2.0V -65° 125°
Note: Minimum voltage input pins -0.5V. During voltage transitions, inputs undershoot -1.3V periods 20ns. Maximum voltage input pins VCC+0.5V. During voltage transitions, input overshoot VCC+2.0V periods 20ns.
CHARACTERISTICS 70°C, 3.3V±10%)
Item Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Operating Current Symbol ICC1 MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 75mA Conditions -0.4mA 1.6mA
Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance
P/N:PM0561
ISTB1 ISTB2 COUT
15uA 10pF 10pF
120ns, output open, with normal sequential access testing pattern CE>VCC-0.2V 1MHZ 1MHZ
REV. 1.5, DEC. 2000
MX23L12822
CHARACTERISTICS 70°C, 3.3V±10%)
Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Delay Symbol tACE 23L12822-12 MIN. 120ns MAX. 120ns 120ns 30ns 30ns 20ns
Note:Output high-impedance delay (tHZ) measured from going high, this parameter guaranteed design over full voltage temperature operating range tested.
Test Conditions
Input Pulse Levels Input Rise Fall Times Input Timing Level Output Timing Level Output Load 0.4V~ 2.4V 10ns 1.4V 1.4V Figure
(load)=-0.4mA DOUT (load)=1.6mA
C<100pF
Note:No output loading present tester load board. Active loading used under software programming control. Output loading capacitance includes load board's stray capacitance.
P/N:PM0561
REV. 1.5, DEC. 2000
MX23L12822
TIMING DIAGRAM
RANDOM READ
tACE
VALID VALID
DATA VALID
PAGE READ
A3-A21
VALID
(A-1),A0,A1,A2
1'st
2'nd VALID VALID
3'rd
DATA
VALID
Note: enable. Page size double words 32-bit mode, words 16-bit mode.
P/N:PM0561
REV. 1.5, DEC. 2000
MX23L12822
Revision History
Revision Description Characteristics ISTB2(CMOS Standby Current) 5uA->15uA Operating Current (ICC1) 60mA->75mA Modify Configuration-86 TSOP D31->D31/A-1 Page P1,3 Date DEC/15/1999 JAN/14/2000 DEC/26/2000
P/N:PM0561
REV. 1.5, DEC. 2000
MX23L12822
MACRONIX INTERNATIONAL CO., LTD.
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MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.

128M-BIT MASK WITH PAGE MODE organization (byte mode) (double wor

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