1M-BIT [128K 8/64K CMOS EPROM organization(MX27C1024, JEDEC

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1M-BIT [128K 8/64K CMOS EPROM organization(MX27C1024, JEDEC

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MX27C1100/27C1024
1M-BIT [128K 8/64K CMOS EPROM
organization(MX27C1024, JEDEC
out) 128K organization(MX27C1100, compatible) +12.5V programming voltage Fast access time: 55/70/85/100/120/150 Totally static operation Completely compatible
Operating current: 40mA Standby current: 100uA Package type:
plastic plastic PLCC 40pin 14mm TSOP(I)
GENERAL DESCRIPTION
MX27C1024 only, 1M-bit, Time Programmable Read Only Memory. organized words bits word(MX27C1024), 128K 16(MX27C1100), operates from single volt supply, static standby mode, features fast single address location programming. programming signals levels, requiring single pulse. programming outside from system, existing EPROM programmers used. MX27C1100/ 1024 supports intelligent fast programming algorithm which result programming time less than thirty seconds. This EPROM packaged industry standard dual-in-line packages, lead SOP, lead PLCC, lead TSOP(I) packages.
CONFIGURATIONS
PDIP/SOP(MX27C1100)
BYTE/VPP Q15/A-1
BLOCK DIAGRAM (MX27C1100)
BYTE/VPP
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q14 Q15/A-1
A0~A15 ADDRESS INPUTS
Y-DECODER
X-DECODER
Y-SELECT
MX27C1100
CELL MAXTRIX
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
CONFIGURATIONS
PDIP/SOP(MX27C1024)
PLCC(MX27C1024)
MX27C1024
MX27C1024
BLOCK DIAGRAM (MX27C1024)
TSOP(I)
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q15
A0~A15 ADDRESS INPUTS
Y-DECODER
Y-DECODER
MX27C1024
X-DECODER
CELL MAXTRIX
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
DESCRIPTION(MX27C1100)
SYMBOL A0~A15 Q0~Q14 BYTE/VPP NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Selection /Program Supply Voltage Q15/A-1 Q15(Word mode)/LSB addr. (Byte mode) Power Supply (+5V) Ground
DESCRIPTION(MX27C1024)
SYMBOL A0~A15 Q0~Q15 NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Enable Input Program Supply Voltage Power Supply (+5V) Ground
TRUTH TABLE BYTE FUNCTION(MX27C1100)
BYTE MODE(BYTE GND)
Q15/A-1 input MODE selected selected Selected Q0-Q7 High High DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
WORD MODE(BYTE VCC)
NOTE Q15/A-1 High High DOUT MODE selected selected Selected Q0-Q14 High High DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
FUNCTIONAL DESCRIPTION
PROGRAMMING MX27C1100/1024 When MX27C1100/1024 delivered, erased, chip bits "ONE" HIGH state. "ZEROs" loaded into MX27C1100/1024 through procedure programming. programming, data programmed applied with bits parallel data pins. must applied simultaneously before VPP, removed simultaneously after VPP. When programming MXIC EPROM, 0.1uF capacitor required across ground suppress spurious voltage transients which damage device. AUTO IDENTIFY MODE auto identify mode allows reading binary code from EPROM that will identify manufacturer device type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional 25°C ambient temperature range that required when programming MX27C1100/1024. activate this mode, programming equipment must force 12.0 address line device. identifier bytes then sequenced from device outputs toggling address line from VIH. other address lines must held during auto identify mode. Byte VIL) represents manufacturer code, byte VIH), device identifier code. MX27C1100/1024, these identifier bytes given Mode Select Table. identifiers manufacturer device codes will possess parity, with (Q15) defined parity bit. VIL(for MX27C1024), VIL, VIH(for MX27C1100)and programming voltage.
FAST PROGRAMMING device fast programming mode when programming voltage 12.75V applied, with 6.25 VIL(or VIH) (Algorithm shown Figure programming achieved applying single level 100us pulse input after addresses data line stable. data verified, additional pulse applied maximum pulses. This process repeated while sequencing through each address device. When programming mode completed, data address verified 10%.
READ MODE MX27C1100/1024 control functions, both which must logically satisfied order obtain data outputs. Chip Enable (CE) power control should used device selection. Output Enable (OE) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge OE's, assuming that been addresses have been stable least tACC
PROGRAM INHIBIT MODE Programming multiple MX27C1100/1024's parallel with different data also easily accomplished using Program Inhibit Mode. Except like inputs parallel MX27C1100/1024 common. low-level program pulse applied MX27C1100/1024 input with 12.5 will program MX27C1100/1024. high-level input inhibits other MX27C1100/1024s from being programmed.
WORD-WIDE MODE PROGRAM VERIFY MODE Verification should performed programmed bits determine that they were correctly programmed. verification should performed with With BYTE/VPP 0.2V outputs Q0-7 present data Q0-7 outputs Q8-15 present data Q8-15, after appropriately enabled.
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
BYTE-WIDE MODE With BYTE/VPP 0.2V, outputs Q8-15 tristated. Q15/A-1 VIH, outputs Q0-7 present data bits Q8-15. Q15/A-1 VIL, outputs Q0-7 present data bits Q0-7. arrays, bulk electrolytic capacitor should used between each eight devices. location capacitor should close where power supply connected array.
STANDBY MODE MX27C1100/1024 CMOS standby mode which reduces maximum current placed CMOS standby when MX27C1100/1024 also TTL-standby mode which reduces maximum current placed TTL-standby when VIH. When standby mode, outputs high-impedance state, independent input.
TWO-LINE OUTPUT CONTROL FUNCTION accommodate multiple memory connections, twoline control function provided allow for: memory power dissipation, Assurance that output contention will occur. recommended that decoded used primary device-selecting function, while made common connection devices array connected READ line from system control bus. This assures that deselected memory devices their low-power standby mode that output pins only active when data desired from particular memory device.
SYSTEM CONSIDERATIONS During switch between active standby conditions, transient current peaks produced rising falling edges Chip Enable. magnitude these transient current peaks dependent output capacitance loading device. minimum, ceramic capacitor (high frequency, inherent inductance) should used each device between minimize transient effects. addition, overcome voltage drop caused inductive effects printed circuit board traces EPROM
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
MODE SELECT TABLE (MX27C1024)
PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) VCC±0.3V OUTPUTS DOUT High High High DOUT High 00C2H 0115H
NOTES:1. 12.0 Either
VIL(For auto select) Programming Characteristics voltage during programming.
MODE SELECT TABLE (MX27C1100)
BYTE/ MODE Read (Word) Read (Upper Byte) Read (Lower Byte) Output Disable Standby Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) Q15/A-1 High High High VPP(5) Q8-14 Q8-14 High High High High Q8-14 Q8-14 High Q0-7 Q0-7 Q8-15 Q0-7 High High Q0-7 Q0-7 High
NOTES: 12.0V 0.5V Either VIL(For auto select)
Programming Characteristics voltages. BYTE/VPP intended operation under Voltage conditions only.
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
FIGURE FAST PROGRAMMING FLOW CHART
START
ADDRESS FIRST LOCATION
6.25V 12.75V
PROGRAM 50us PULSE
INTERACTIVE SECTION
INCREMENT
FAIL
VERIFY WORD
PASS INCREMENT ADDRESS LAST ADDRESS FAIL
5.25V
VERIFY SECTION
VERIFY WORDS
FAIL
DEVICE FAILED
PASS DEVICE PASSED
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K
6.2K
DIODES IN3064 EQUIVALENT
including capacitance (30pF 55/70ns parts)
SWITCHING TEST WAVEFORMS
2.0V
driving levels
2.0V TEST POINTS 0.8V OUTPUT
0.8V INPUT
TESTING: driving levels 2.4V/0.4V Input pulse rise fall times <20ns.
driving levels
1.5V
TEST POINTS OUTPUT
1.5V
INPUT
TESTING: driving levels 3.0V/0V. Input pulse rise fall times 10ns. MX27C1100/1024-55/70
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage Ground Potential VALUE -40oC 85oC -65oC 125oC -0.5V 7.0V -0.5V 0.5V -0.5V 7.0V -0.5V 13.5V
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended period affect reliability. NOTICE: Specifications contained within following tables subject change.
DC/AC Operating Conditions Read Operation
MX27C1100/1024 -55* Operating Temperature Commercial Industrial Power Supply 55°C 70°C 70°C 70°C 70°C 70°C
-40° 85°C -40°C 85°C -40° 85°C -40° -40°C 85°C
55ns MX27C1024 only **:Industrial grade MX27C1024 only
CHARACTERISTICS
SYMBOL ICC3 ICC2 ICC1 PARAMETER Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Power-Down Current Standby Current Active Current Supply Current Read -0.3 MIN. MAX. UNIT 5.5V VOUT 5.5V 0.3V VIL, f=5MHz, Iout VIL, 5.5V CONDITIONS -0.4mA 2.1mA
CAPACITANCE 25oC, (Sampled only)
SYMBOL COUT CVPP PARAMETER Input Capacitance Output Capacitance Capacitance TYP. MAX. UNIT CONDITIONS VOUT
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
CHARACTERISTICS
27C1024-55 SYMBOL tACC PARAMETER Address Output Delay Chip Enable Output Delay Output Enable Output Delay High Output Float, High Output Float Output Hold from Address, which ever occurred first *tBHA *tOHB *tBHZ *tBLZ BYTE Access Time BYTE Output Hold Time BYTE Output Delay Time BYTE Output Time MIN. MAX. 27C1100/1024-70 MIN. MAX. 27C1100/1024-85 MIN. MAX. UNIT CONDITIONS
MX27C1100 only
CHARACTERISTICS
27C1100/1024-10 SYMBOL tACC PARAMETER Address Output Delay Chip Enable Output Delay Output Enable Output Delay High Output Float, High Output Float Output Hold from Address, which ever occurred first *tBHA *tOHB *tBHZ *tBLZ BYTE Access Time BYTE Output Hold Time BYTE Output Delay Time BYTE Output Time MIN. MAX. 27C1100/1024-12 MIN. MAX. 27C1100/1024-15 MIN. MAX. UNIT CONDITIONS
MX27C1100 only
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
PROGRAMMING CHARACTERISTICS 25oC
SYMBOL ICC3 IPP2 VCC1 VPP1 PARAMETER Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Auto Select Voltage Supply Current (Program Verify) Supply Current(Program) Fast Programming Supply Voltage Fast Programming Voltage 6.00 12.5 -0.3 11.5 MIN. 12.5 6.50 13.0 MAX. UNIT VIL, 5.5V CONDITIONS -0.40mA 2.1mA
PROGRAMMING CHARACTERISTICS 25oC
SYMBOL tOES tDFP tVPS tVCS tCES PARAMETER Address Setup Time Setup Time Data Setup Time Address Hold Time Data Hold Time Output Enable Output Float Delay Setup Time Program Pulse Width Setup Time Setup Time Data valid from MIN. MAX. UNIT CONDITIONS
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
WAVEFORMS(MX27C1024)
READ CYCLE(WORD MODE)
ADDRESS INPUTS
tACC
DATA ADDRESS
DATA
VALID DATA
FAST PROGRAMMING ALGORITHM WAVEFORMS
PROGRAM
PROGRAM VERIFY
Addresses
Hi-z DATA STABLE DATA VALID
DATA
VPP1
tDFP
tVPS VCC1
tVCS
tCES
tOES
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
WAVEFORMS(MX27C1100)
READ CYCLE(BYTE MODE)
HIGH-Z
HIGH-Z
tACC
BYTE/VPP
Q0-Q7
VALID DATA
tBHA tOHB
VALID DATA
Q15-Q8
tBHZ tBLZ
VALID DATA
FAST PROGRAMMING ALGORITHM WAVEFORM
PROGRAM VERIFY
Addresses
VALID ADDRESS
DATA
VPP1
DATA
DATA VALID
tDFP
BYTE/VPP
tVPS VCC1
tVCS
tOES
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
ORDER INFORMATION
PLASTIC PACKAGE
PART ACCESS TIME (ns) MX27C1100PC-70 MX27C1100PC-85 MX27C1100PC-10 MX27C1100PC-12 MX27C1100PC-15 MX27C1100MC-70 MX27C1100MC-85 MX27C1100MC-10 MX27C1100MC-12 MX27C1100MC-15 MX27C1024PC-55 MX27C1024PC-70 MX27C1024PC-85 MX27C1024PC-10 MX27C1024PC-12 MX27C1024PC-15 MX27C1024QC-55 MX27C1024QC-70 MX27C1024QC-85 MX27C1024QC-10 MX27C1024QC-12 MX27C1024QC-15 MX27C1024MC-55 MX27C1024MC-70 MX27C1024MC-85 MX27C1024MC-10 MX27C1024MC-12 MX27C1024MC-15 MX27C1024TC-55 MX27C1024TC-70 MX27C1024TC-85 MX27C1024TC-10 MX27C1024TC-12 MX27C1024TC-15 MX27C1024TI-70 MX27C1024TI-85 MX27C1024TI-10 MX27C1024TI-12 MX27C1024TI-15 OPERATING CURRENT MAX.(mA) STANDBY CURRENT MAX.(uA) DIP(ROM out) DIP(ROM out) DIP(ROM out) DIP(ROM out) DIP(ROM out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) PLCC PLCC PLCC PLCC PLCC PLCC TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I) PACKAGE
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
PACKAGE INFORMATION
40-PIN PLASTIC DIP(600 mil)
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
44-PIN PLASTIC LEADED CHIP CARRIER(PLCC)
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
40-PIN PLASTIC SOP(450 mil)
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
40-PIN PLASTIC TSOP
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
REVISION HISTORY
Revision Description Revise speed grade from 70/90/120/150ns 55/70/85/100/ 120/150ns. package type. Eliminate Interactive Programming Mode. 40-CDIP package quartz lens, change square shape. 100uA 10uA industrial grade 70/85/100/120/150ns 40-TSOP(I) Cancel ceramic package type Cancel "Ultraviolet Erasable" wording General Description modify Package Information Page Date 10/15/1996
06/14/1997 08/08/1997 11/19/1998 FEB/25/2000 AUG/20/2001
P1,2,4,15,16 P15~18
P/N: PM0156
REV. AUG. 2001
MX27C1100/27C1024
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.

1M-BIT [128K 8/64K CMOS EPROM organization(MX27C1024, JEDEC

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