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PAGE MODE FLASH MEMORY 8/1M FEATURES Single read, progr


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DS05-20872-1E
PAGE MODE FLASH MEMORY
8/1M
FEATURES
Single read, program erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands E2PROMs Compatible with MASK pinouts 48-pin TSOP (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin (Package suffix: Minimum 100,000 program/erase cycles High performance maximum page access time (75ns maximum random access time) words page read mode function Sector erase architecture word, words, 112K word, seven 128K words sectors word mode byte, bytes, 224K byte, seven 256K bytes sectors byte mode combination sectors concurrently erased. Also supports full chip erase Boot Code Sector Architecture sector Bottom sector Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded programAlgorithms Automatically programs verifies data specified address Data Polling Toggle feature detection program erase cycle completion Ready/Busy output (RY/BY) Hardware method detection program erase cycle completion Automatic sleep mode When addresses remain stable, automatically switches themselves power mode write inhibit
(Continued)
Embedded Eraseand Embedded Programare trademarks Advanced Micro Devices, Inc.
(Continued) Erase Suspend/Resume Suspends erase operation allow read data and/or program another sector within same device Sector protection Hardware method disables combination sectors from program erase operations Temporary sector unprotection Temporary sector unprotection with software command tolerant (Data, Address, Control Signals) accordance with (Common Flash Memory Interface)
PACKAGE
48-pin plastic TSOP
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
44-pin plastic
(FPT-44P-M16)
GENERAL DESCRIPTION
MBM29PL160TD/BD 16M-bit, V-only Flash memory organized bytes bits each words bits each. MBM29PL160TD/BD offered 48-pin TSOP (I), 44-pin packages. device designed programmed in-system with standard system supply. 12.0 required write erase operations. device also reprogrammed standard EPROM programmers. standard MBM29PL160TD/BD offers access times allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. MBM29PL160TD/BD command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Flash EPROM devices. MBM29PL160TD/BD programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margins. Typically, each sector programmed verified about seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margins. individual sector typically erased verified second. already preprogrammed.) device also features sector erase architecture. sector mode allows each sector erased reprogrammed without affecting other sectors. MBM29PL160TD/BD erased when shipped from factory. device features single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling Toggle feature output pin. Once program erase cycle been comleted, device internally resets read mode. Fujitsu's Flash technology combines years Flash memory manufacturing experience produce highest levels quality, reliability, cost effectiveness. MBM29PL160TD/BD memory electrically erases bits within sector simultaneously Fowler-Nordhiem tunneling. bytes/words programmed byte/word time using EPROM programming mechanism electron injection.
FLEXIBLE SECTOR-ERASE ARCHITECTURE
word, words, 112K word, seven 128K words sectors word mode. byte, bytes, 224K byte, seven 256K bytes sectors byte mode. Individual-sector, multiple-sector, bulk-erase capability. Individual multiple-sector protection user definable.
Sector SA10
Sector Size Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords
Address Range 000000H 03FFFFH 040000H 07FFFFH 080000H 0BFFFFH 0C0000H 0FFFFFH 100000H 13FFFFH 140000H 16FFFFH 180000H 1BFFFFH 1C0000H 1F7FFFH 1F8000H 1F9FFFH 1FA000H 1FBFFFH 1FC000H 1FFFFFH
Address Range 00000H 1FFFFH 20000H 3FFFFH 40000H 5FFFFH 60000H 7FFFFH 80000H 9FFFFH A0000H BFFFFH C0000H DFFFFH E0000H FBFFFH FC000H FCFFFH FD000H FDFFFH FE000H FFFFFH
MBM29PL160TD Boot Sector Architecture
Sector SA10
Sector Size Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords Kbytes Kwords
Address Range 000000H 003FFFH 004000H 005FFFH 006000H 007FFFH 008000H 03FFFFH 040000H 07FFFFH 080000H 0BFFFFH 0C0000H 0FFFFFH 100000H 13FFFFH 140000H 17FFFFH 180000H 1BFFFFH 1C0000H 1FFFFFH
Address Range 00000H 01FFFH 02000H 02FFFH 03000H 03FFFH 04000H 1FFFFH 20000H 3FFFFH 40000H 5FFFFH 60000H 7FFFFH 80000H 9FFFFH A0000H BFFFFH C0000H DFFFFH E0000H FFFFFH
MBM29PL160BD Bottom Boot Sector Architecture
PRODUCT LINE
Part Ordering Part
+0.6 -0.3
MBM29PL160TD/160BD
Max. Address Access Time (ns) Max. Page Address Access Time (ns) Max. Access Time (ns) Max. Access Time (ns)
BLOCK DIAGRAM
DQ15
Erase Voltage Generator
Input/Output Buffers
State Control
BYTE
Command Register Program Voltage Generator
Chip Enable Output Enable Logic
Data Latch
Y-Decoder
Y-Gating
Detector
Timer Program/Erase
Address Latch
X-Decoder
Cell Matrix
CONNECTION DIAGRAMS
(Marking Side) DQ10 DQ11 N.C. BYTE DQ15/A-1 DQ14 DQ13 DQ12 N.C. BYTE N.C. DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 N.C. BYTE N.C. TSOP(I) (Marking Side) N.C. DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 N.C.
Standard Pinout
FPT-48P-M19
(Marking Side)
Reverse Pinout
FPT-44P-M16
FPT-48P-M20
LOGIC SYMBOL
Table MBM29PL160TD/BD Configuration
DQ15 BYTE
Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Selects 8-bit 16-bit mode Connected Internally Device Ground Device Power Supply
A-1, DQ15 BYTE N.C.
DEVICE OPERATIONS
Table Operation Auto-Select Manufacture Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Protection (2), Verify Sector Protection (2), MBM29PL160TD/BD User Operation (BYTE VIH)
DQ15
Code Code DOUT HIGH-Z HIGH-Z Code
Table Operation
MBM29PL160TD/BD User Operation (BYTE VIL) DQ15/ Code Code DOUT HIGH-Z HIGH-Z Code
Auto-Select Manufacture Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Protection (2), Verify Sector Protection (2), Legend: VIL, VIH, VIH.
pulse input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Table Refer section Sector Protection. VIL, initiates write operations. ±10%
FUNCTIONAL DESCRIPTION
Random Read Mode
MBM29PL160TD/BD control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins. (Assuming addresses have been stable least tACC time.) Figure timing specifications. When reading data without changing addresses after powe-up, necessary input hardware reset change from "L".
Page Read Mode
MBM29PL160TD/BD capable fast Page read mode compatible with Page mode MASK read operation. This mode provides faster read access speed random locations within page. Page size MBM29PL160TD/BD device words, bytes, within appropriate Page being selected higheraddress bits word mode) byte mode) determining specific word/ bytewithin that page. This asynchronous operation with microprocessor supplying specific word byte location. rondom initial page access equal tACC subsequent Page read access long locations specified microprocessor fall within that Page) equivalent tPACC. Here again, selects device output control should used gate data output pins device selected. Fast Page mode accesses obtained keeping constant changing select specific word, changing select specific byte, within that page. Figure timing specifications.
Standby Mode
MBM29PL160TD/BD standby mode, CMOS standby mode input ±0.3 V.), when current consumed less than During Embedded Algorithm operation, Active current (ICC2) required even "H". device read with standard access time (tCE) from standby modes. standby mode, outputs high-impedance state, independent input. device deselected during erasure programming, device will draw active current until operation completed.
Automatic Sleep Mode
There function called automatic sleep mode restrain power consumption during read-out MBM29PL160TD/BD data. This mode used effectively with application requesting power consumption such handy terminals. activate this mode, MBM29PL160TD/BD automatically switches itself power mode when addresses remain stable necessary control this mode. During such mode, current consumed typically (CMOS Level). Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system.
Output Disable
input logic high level (VIH), output from device disabled. This will cause output pins high-impedance state.
Autoselect
Autoselect mode allows reading binary code from device will identify manufacturer type. intent allow programming equipment automatically match device programmed with corresponding programming algorithm. Autoselect command also used check status write-protected sectors. (See Tables 4.2.) This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from devices outputs toggling address from VIH. addresses DON'T CARES except (A-1). (See Table Table (Recomend other addresses pins.) manufacturer device codes also read command register, instances when MBM29PL160TD/BD erased programmed system without access high voltage pin. command sequence illustrated Table Command Definitions. Word VIL) represents manufacture's code word VIH) represents device identifier code. MBM29PL160TD/BD these bytes given Table 4.2. identifiers manufactures device will exhibit parity with defined parity bit. order read proper device codes when executing Autoselect, must VIL. (See Tables BYTE (for byte mode), device code (for boot block) (for bottom boot block). BYTE (for word mode), device code 2227H (for boot block) 2245H (for bottom boot block). order determine which sectors write protected, must while running through sector addresses; selected sector protected, logical will output (DQ0 =1).
Table MBM29PL160TD/BD Sector Protection Verify Autoselect Code Type Manufacture's Code Byte MBM29PL160TD Word Device Code Byte MBM29PL160BD Word Sector Protection Temporary Sector Unprotection Byte mode. Outputs protected sector addresses outputs unprotected sector addresses. Outputs Temporary Sector Unprotect outputs Temporary Sector Unprotect. Table Expanded Autoselect Code Table Type Manufacture's Code
MBM29PL160TD
A-1*1
Code (HEX) 2227H 2245H 01H*2 01H*3
Sector Addresses
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
A-1/0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
Device Code
MBM29PL160BD
2227H
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
2245H
Sector Protection Temporary Sector Unprotection (B): Byte mode (W): Word mode
A-1/0 A-1/0
Table Sector Address SA10 Sector Address Tables (MBM29PL160TD) Address Range 000000H 03FFFFH 040000H 07FFFFH 080000H 0BFFFFH 0C0000H 0FFFFFH 100000H 13FFFFH 140000H 17FFFFH 180000H 1BFFFFH 1C0000H 1F7FFFH 1F8000H 1F9FFFH 1FA000H 1FBFFFH 1FC000H 1FFFFFH Address Range 00000H 1FFFFH 20000H 3FFFFH 40000H 5FFFFH 60000H 7FFFFH 80000H 9FFFFH A0000H BFFFFH C0000H DFFFFH E0000H FBFFFH FC000H FCFFFH FD000H FDFFFH FE000H FFFFFH
00000 11011
Table Sector Address SA10
Sector Address Tables (MBM29PL160BD) Address Range 000000H 003FFFH 004000H 005FFFH 006000H 007FFFH 008000H 03FFFFH 040000H 07FFFFH 080000H 0BFFFFH 0C0000H 0FFFFFH 100000H 13FFFFH 140000H 17FFFFH 180000H 1BFFFFH 1C0000H 1FFFFFH Address Range 00000H 01FFFH 02000H 02FFFH 03000H 03FFFH 04000H 1FFFFH 20000H 3FFFFH 40000H 5FFFFH 60000H 7FFFFH 80000H 9FFFFH A0000H BFFFFH C0000H DFFFFH E0000H FFFFFH
00100 11111
Write
Device erasure programming accomplished command register. command register written bringing VIL, while VIH. Addresses latched falling edge whichever occurs later, while data latched rising edge pulse, whichever occurs first. Standard microprocessor write timings used. Figures Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Protection
MBM29PL160TD/BD features hardware sector protection. This feature will disable both program erase operations number sectors through 10). sector protection feature enabled using programming equipment user's site. device shipped with sectors unprotected. activate this mode, programming equipment must force address control VIL, VIL, VIH. sector addresses pins (A19, A18, A17, A16, A15, A14, A13, A12) should sector protected. Tables define sector address each eleven (11) individual sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector addresses must held constant during pulse. figures sector protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector addresses (A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical device output protected sector. Otherwise device will read unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. requires byte mode. also possible determine sector protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses pins (A19, A18, A17, A16, A15, A14, A13, A12) represents sector address will produce logical protected sector. Tables Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection previously protected sectors MBM29PL160TD/BD devices order change data. Temporary Sector Unprotection mode activated command register. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once mode taken away using command register, previously protected sectors will protected again. (See Figures 20.)
Table Command Sequence (Notes
Read/Reset (Note Read/Reset (Note Write Cycles Req'd
MBM29PL160TD/BD Standard Command Definitions
Second First Third Fourth Fifth Sixth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data XXXH 555H AAAH 555H AAAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH XXXH XXXH 555H AAAH 555H AAAH 2AAH 555H 2AAH 555H 555H AAAH
Word /Byte Word Byte Word Byte
Autoselect Byte/Word Program (Notes Chip Erase
Word Byte Word Byte Word Byte Word /Byte Word /Byte Word Byte Word Byte
AAAH 555H AAAH 555H AAAH
Sector Erase (Note Sector Erase Suspend Sector Erase Resume Temporary Unprotect Enable Temporary Unprotect Disable
XXXH XXXH 555H AAAH 555H AAAH
Notes: Address bits address commands except Program Address (PA) Sector Address (SA). operations defined Tables =Address memory location read. =Address memory location programmed. Addresses latched falling edge pulse. =Address sector erased. combination A19, A18, A17, A16, A15, A14, A13, will uniquely select sector. =Data read from location during read operation. =Data programmed location Data latched rising edge system should generate following address patterns: Word Mode: 555H 2AAH addresses Byte Mode: AAAH 555H addresses Both Read/Reset commands functionally equivalent, resetting device read mode.
Table Command Sequence Fast Mode Fast Program Reset from Fast Mode Query Command Word Byte Word Byte Word Byte Word Byte MBM29PL160TD/BD Extended Command Definitions First Write Cycle Addr 555H AAAH XXXH XXXH XXXH XXXH Data Second Write Cycle Addr 2AAH 555H XXXH XXXH Data Third Write Cycle Addr 555H AAAH Data Fourth Read Cycle Addr Data
Write Cycles Req'd
Sector Address protected. sector address (SA) (A6, Sector protection verify data. Output protected sector addresses output unprotected sector addresses. This command valid while fast mode. Addresses from system other addresses "Don't care". data" 00H" also acceptable.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0H) Erase Resume (30H) commands valid only while Sector Erase operation progress. Moreover both Read/Reset commands functionally equivalent, resetting device read mode. Please note that commands always written DQ15 bits ignored.
Read/Reset Command
order return from Autoselect mode Exceeded Timing Limits (DQ5 read mode, read/reset operation initiated writing Read/Reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up Read/Reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory contents occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters. (See Figure 5.2.)
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufactures device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice. device contains Autoselect command operation supplement traditional PROM programming methodology. operation initiated writing Autoselect command sequence into command register. Following last command write, read cycle from address XX00H retrieves manufacture code 04H. read cycle from address XX01H (XX02H retrieves device code (MBM29PL160TD
MBM29PL160BD mode; MBM29PL160TD 2227H MBM29PL160BD 2245H mode). (See Tables 4.2.) manufactures device codes will exhibit parity with defined parity bit. sector state (protection unprotection) will indicated address XX02H (XX04H Scanning sector addresses (A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical device output protected sector. programming verification should perform margin mode verification protected sector. (See Tables terminate operation, necessary write Read/Reset command sequence into register and, also write Autoselect command during operation, executing after writing Read/Reset command sequence.
Word/Byte Programming
device programmed byte-by-byte word-by-word) basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge last (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. (See Figures automatic programming operation completed when data equivalent data written this which time device return read mode addresses longer latched. (See Table Hardware Sequence Flags.) Therefore, device requires that valid address supplied system this time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. hardware reset occures during programming operation, impossible guarantee whether data being written correct not. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device result apparent success according data polling algorithm read from read/reset mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded ProgramAlgorithm using typical command strings operations.
Chip Erase
Chip erase six-bus cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device will automatically program verify entire memory zero data pattern prior electrical erase. (Preprogram Function.) system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (See Write Operation Status section.) which time device returns read mode. (See Figure Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Sector Erase
Sector erase six-bus cycle operation. There "unlock" write cycles, followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (any address location within desired sector) latched falling edge while command (Data 30H) latched rising edge After time-out from rising edge last sector erase command, sector erase operation will begin.
Multiple sectors erased concurrently writing six-bus cycle operations Table This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. Monitor determine sector erase timer window still open. (See section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset device read mode, ignoring previous command string. Resetting device once excution begun will corrupt data sector. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors 10). Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase (Preprogram Function). When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. (See Figure automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data (See Write Operation Status section) which time device returns read mode. Data polling must performed address within sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) Sector Erase Time] Number Sector Erase. Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Erase Suspend/Resume
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from program sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writting Erase Suspend command during Sector Erase time-out results immediate termination time-out period suspension erase operation. Writing Erase Resume command resumes erase operation. addresses "DON'T CARES" when writing Erase Suspend Erase Resume commands. When Erase Suspend command written during Sector Erase operation, device will take maximum suspend erase operation. When devices have entered erase-suspended mode, output will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, device defaults erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Program. This Program mode known erase-suspend-program mode. Again, programming this mode same programming regular Program mode except that data must programmed sectors that erase-suspended. Successively reading from erase-suspended sector while devices erase-suspend-program mode will cause toggle. erasesuspended Program operation detected Data polling Toggle (DQ6) which same regular Program operation. Note that must read from Program address while read from address.
resume operation Sector Erase, Resume command (30H) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
Extended Command
Fast Mode MBM29PL160TD/BD Fast Mode function. This mode dispenses with initial unlock cycles required standard program command sequence writing Fast Mode command into command register. this mode, required cycle programming cycles instead four cycles standard program command. write erase command this mode.) read operation also executed after exiting this mode. exit this mode, necessary write Fast Mode Reset command into command register. (Refer Figure Extended algorithm.) active current required even during Fast Mode. Fast Programming During Fast Mode, programming executed with cycles operation. Embedded Program Algorithm executed writing program set-up command (A0H) data write cycles (PA/PD). (Refer Figure Extended algorithm.) (Common Flash Memory Interface) (Common Flash Memory Interface) specification outlines device host system software interrogation handshake which allows specific vendor-specified software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward-and backwardcompatible software support specified flash device families. Refer specification detail. operation initiated writing query command (98H) into command register. Following command write, read cycle from specific address retrives device information. Please note that output data upper byte (DQ8 DQ15) word mode bit) read. Refer code table. terminate operation, necessary write read/reset command sequence into register.
Write Operation Status
Table Status Embedded Program Algorithm Embedded/Erase Algorithm Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspend (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Time Limits Embedded/Erase Algorithm Erase Suspend Program (Non-Erase Suspended Sector) Hardware Sequence Flags Data Toggle Toggle Data Toggle (Note Toggle Toggle Toggle Data Data Toggle Toggle Data (Note
Notes: Performing successive read operations from address will cause toggle. Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspended sector will cause toggle. reserve pins future use. Fujitsu internal only. Data Polling MBM29PL160TD/BD device features Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm, attempt read devices will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure chip erase sector erase, Data Polling valid after rising edge sixth pulse six-write pulse sequence. Data Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. Once Embedded Algorithm operation close being completed, MBM29PL160TD/BD data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Program Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm sector erase time-out. Figure Data Polling timing specifications diagrams.
Toggle MBM29PL160TD/BD also feature "Toggle method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data read next successive attempts. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth pulse sixwrite pulse sequence. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle Toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. Figure Figure Toggle timing specifications diagrams. Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function device under this condition. circuit will partially power down device under these conditions. pins will control output disable functions described Tables failure condition also appear user tries program blank location without erasing. this case device locks never completes Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate "1." Please note that this device failure condition since device incorrectly used. this occurs, reset device with command sequence. Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, command have been accepted. Table Hardware Sequence Flags.
Toggle This Toggle along with DQ6, used determine whether device Embedded Erase Algorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded Erase Algorithm. device erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When device erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic DQ2. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. example, used together determine erase-suspend-read mode progress. (DQ2 toggles while does not.) also Table Figure Furthermore, also used determine which sector being erased. When device erase mode, toggles this read from erasing sector. Table Mode Program Erase Erase Suspend Read (Erase Suspended Sector) (Note Erase-Suspend Program Toggle Status Toggle Toggle Toggle (Note Toggle Toggle (Note
Notes: Performing successive read operations from address will cause toggle. Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspended sector will cause toggle.
Word/Byte Configuration
BYTE selects byte (8-bit) mode word (16-bit) mode MBM29PL160TD/BD device. When this driven high, device operates word (16-bit) mode. data read programmed DQ15. When this driven low, device operates byte (8-bit) mode. Under this mode, DQ15/A-1 becomes lowest address DQ14 bits tri-stated. However, command cycle always 8-bit operation hence commands written DQ15 bits ignored. Refer Figures timing diagrams.
Data Protection
MBM29PL160TD/BD designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequence. device also incorporates several features prevent inadvertent write cycles resulting form power-up power-down transitions system noise.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than (typically VLKO, command register disabled internal program/erase circuits disabled. Under this condition, device will reset read mode. Subsequent writes will ignored until level greater than VLKO. users responsibility ensure that control pins logically correct prevent unintentional writes when above Embedded Erase Algorithm interrupted, there possibility that erasing sector(s) will need erased again prior programming.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will change command registers.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write, must logical zero while logical one.
Power-up Write Inhibit
Power-up devices with will accept commands rising edge internal state machine automatically reset read mode power-up.
Table Common Flash Memory Interface Code Description Query-unique ASCII string "QRY" Primary Command AMD/FJ standard type Address Primary Extended Table Alternate Command (00h applicable) Address Alternate Extended Table Min. (write/erase) D7-4: volt, D3-0: mvolt Max. (write/erase) D7-4: volt, D3-0: mvolt Min. voltage Max. voltage Typical timeout single byte/word write Typical timeout Min. size buffer write Typical timeout individual block erase Typical timeout full chip erase Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical Device Size byte Flash Device Interface description Max. number byte multi-byte write Number Erase Block Regions within device Erase Block Region Information
DQ15
Description Erase Block Region Information
DQ15
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h
0001h 0000h 0020h 0000h 0000h 0000h 0080h 0003h 0006h 0000h 0000h 0004h 0050h 0052h 0049h 0031h 0030h 0000h
Erase Block Region Information
Erase Block Region Information
Query-unique ASCII string "PRI" Major version number, ASCII
0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h
Minor version number, ASCII Address Sensitive Unlock Required Required Erase Suspend Supported Read Only Read Write Sector Protect Supported Number sectors group Sector Temporary Unprotect Supported Supported Sector Protection Algorithm Number Sector Bank2 Burst Mode Type supported Page Mode Type supported word Page word Page
0002h
0001h
0001h
0004h
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -55°C +125°C Ambient Temperature with Power Applied -40°C +85°C Voltage with respect Ground pins except RESET (Note -0.5 +5.5 (Note -0.5 +4.0 RESET (Note -0.5 +13.0 Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins 6.0V. During voltage transitions,outputs positive overshoot +2.0 periods Minimum input voltage RESET pins -0.5 During voltage transitions, RESET pins negative overshoot -2.0 periods Maximum input voltage RESET pins +13.0 which positive overshoot 13.5 periods Voltage difference between input voltage supply voltage (VIN VCC) exceed WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING RANGES
Ambient Temperature (TA) MBM29PL160TD/BD-75 .-20°C +70°C MBM29PL160TD/BD-90 .-40°C +85°C Supply Voltages MBM29PL160TD/BD-75/90 .+2.7 +3.6 Operating ranges define those limits between which functionality device quaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MAXIMUM OVERSHOOT
+0.6 -0.5 -2.0
Figure
Maximum Negative Overshoot Waveform
+0.5 +2.0
Figure
Maximum Positive Overshoot Waveform
+13.5 +13.0 +0.5
Note This waveform applied RESET.
Figure
Maximum Positive Overshoot Waveform
CHARACTERISTICS
Parameter Symbol ILIT Parameter Description Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Test Conditions VCC, Max. VOUT VCC, Max. Max., 12.5 VIL, ICC1 Active Current (Note VIL, ICC2 ICC3 ICC4 ICC5 VOH1 Output High Voltage Level VOH2 VLKO Notes: Lock-Out Voltage -100 Active Current (Note Current (Standby) VIL, Max., ±0.3 -0.5 11.5 12.5 0.45 Min. -1.0 -1.0 Max. +1.0 +1.0 Unit
Current Max., ±0.3 (Automatic Sleep Mode) (Note ±0.3 ±0.3 Active Current (Page Read Mode) Input Level Input High Level (Note Voltage Autoselect,Sector Protection (A9, (Note Output Voltage Level 30MHz VIL, 40MHz Min. -2.0 Min.
current listed includes both operating current frequency dependent component. active while Embedded Erase Embedded Program progress. Automatic sleep mode enables power mode when address remain stable Applicable only sector protection. input voltage must input after valid.
CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tACC tPRC tPACC tELFL tELFH Read Cycle Time Address Output Delay Page Read Cycle Time Page Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output HIGH-Z Output Enable Output HIGH-Z Output Hold Time From Address, Whichever Occurs First BYTE Switching High Min. Max. Min. Max. Max. Max. Max. Max. Min. Max. (Note) (Note)
Description
Test Setup
Unit
Note: Test Conditions: Output Load:
gate (MBM29PL160TD/BD-75) gate (MBM29PL160TD/BD-90) Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Notes: including capacitance (MBM29PL160TD/BD-75) including capacitance (MBM29PL160TD/BD-90)
Figure
Test Conditions
Write (Erase/Program) Operations Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tOES tOEH tGHWL tGHEL tWPH tCPH tWHWH1 tWHWH2 tEOE tVCS tVLHT tWPP tOESP tCSP tFLQZ tFHQV Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle Data Polling
MBM29PL160TD/BD
Description Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Byte Word Typ. Typ. Max. Min. Min. Min. Min. Min. Min. Max. Min.
12.6
12.6
Unit
Read Recover Time Before Write Read Recover Time Before Write High Low) Setup Time Setup Time Hold Time Hold Time Write Pulse Width Pulse Width Write Pulse Width High Pulse Width High Programming Operation Sector Erase Operation (Note Delay Time from Embedded Output Enable Setup Time Voltage Transition Time (Note Write Pulse Width (Note Setup Time Active (Note Setup Time Active (Note Recover Time From RY/BY BYTE Switching Output HIGH-Z BYTE Switching High Output Active
Notes: This does include preprogramming time. This timing Sector Protection operation.
SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM
INPUTS Must Steady Change from Change from "L": Change Permitted Does Apply
OUTPUTS Will Steady Will Change from Will Change from Changing, State Unknown Center Line HighImpedance "Off" State
Addresses
Addresses Stable
tACC
tOEH
Outputs
HIGH-Z
Output Valid
HIGH-Z
Figure
Waveforms Read Operations
Addresses Valid
(A-1)
tACC
tPRC
tOEH
tPACC
tPACC
Outputs
HIGH-Z
Figure
Waveforms Page Read Mode Operations
Cycle Addresses
555H
Data Polling
tGHWL tWPH tWHWH1
Data
DOUT
DOUT
Notes:
address memory location programmed. data programmed word address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Alternate Controlled Program Operations
Cycle
Data Polling
Addresses
555H
tGHEL tCPH tWHWH1
DOUT
Data
Notes:
address memory location programmed. data programmed word address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Alternate Controlled Program Operations
Addresses
555H
2AAH
555H
555H
2AAH
tGHWL tWPH
Sector Erase
Data
tVCS
sector address Sector Erase. Addresses 555H (Word), AAAAH (Byte) Chip Erase. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Chip/Sector Erase Operations
tOEH
Data Valid Data
High-Z
tWHWH1
High-Z
Data
Output Flag
Valid Data
(tEOE)
Valid Data (The device completed Embedded operation.) Figure Waveforms Data Polling during Embedded Algorithm Operations
tOEH
tOEH
tOES
Toggle Stop Toggling Data Valid
Data
Toggle
Stops toggling. (The device completed Embedded operation.) Figure Waveforms Taggle during Embedded Algorithm Operations
BYTE
DQ14
tELFH
tFHQV
DQ14
DQ15/A-1
DQ15
Figure
Timing Diagram Word Mode Configuration
BYTE
tELFL
DQ14
DQ14
DQ15/A-1
DQ15 tFLQZ
Figure
Timing Diagram Byte Mode Configuration
falling edge last signal
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
Figure
BYTE Timing Diagram Write Operations
A19, A18, A16, A15, A13,
tVLHT tWPP tVLHT tVLHT
tOESP tCSP tVLHT
Data
tVCS
Sector Address initial sector Sector Address next sector Note: byte mode. Figure Waveforms Sector Protection Timing Diagram
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Toggle with
Note: read from erase-suspended sector. Figure
FLOW CHART
Start
Write Program Command Sequence (See Below)
Data Polling Device
Verify Byte
Increment Address
Last Address
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
sequence applied mode. addresses differ from mode.
Figure
Embedded ProgramAlgorithm
Start
Write Erase Command Sequece (See Below) Data Polling Toggle from Device
Data Erasure Completed
Chip Erase Command Sequence* (Address/Command): 555H/AAH
Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands optional.
Sector Address/30H
sequence applied mode. addresses differ from mode.
Figure
Embedded EraseAlgorithm
Start
Read Byte (DQ0 DQ7) Addr.
Data? Read Byte (DQ0 DQ7) Addr.
=Address programming =Any sector addresses within sector being erased during sector erase multiple erases operation. =Any sector addresses within sector being protected during sector erase multiple sector erases operation.
Data? Fail
Pass
rechecked even because change simultaneously with DQ5. Figure Data Polling Algorithm
Start
Read (DQ0 DQ7) Addr.
Toggle Read Byte (DQ0 DQ7) Addr.
Toggle Fail
Pass
rechecked even because stop toggling same time changing "1". Figure Toggle Algorithm
Start
Setup Sector Addr. (A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT
VID, VIL,
Activate Pulse Increment PLSCNT
Time
VIH, should remain VID) Read from Sector VIH, VIL, Addr. VIL)* PLSCNT Remove from Write Reset Command Data 01H? Protect Another Sector? Device Failed Remove from Write Reset Command
Sector Protection Completed
byte mode. Figure Sector Protection Algorithm
Start
Temporary Unprotect Enable Command Write (Note
Perform Erase Program Operations
Temporary Unprotect Disable Command Write
Temporary Sector Unprotection Completed (Note
Notes: protected sectors unprotected. previously protected sectors protected once again.
Figure
Temporary Sector Unprotection Algorithm
Start
555H/AAH
2AAH/55H
Fast Mode
555H/20H
XXXXH/A0H
Program Address/Program Data
Fast Program
Data Polling Device
Verify Byte? Increment Address Last Address Programming Completed
XXXH/90H Reset Fast Mode XXXH/F0H
sequence applied mode. addresses differ from mode.
Figure
Embedded Programming Algorithm Fast Mode
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle 100,000 Typ. 12.6 Max. cycles Excludes programming time prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. 12.0 11.5 Unit
Note: Test conditions 25°C,
ORDERING INFORMATION
Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29PL160
PFTN
PACKAGE TYPE PFTN 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout =44-Pin Small Outline Package (SOP)
SPEED OPTION Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE sector Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29PL160 Mega-bit 8-Bit 16-Bit) CMOS Page Mode Flash Memory V-only Read, Write, Erase
PACKAGE DIMENSIONS
48-pin plastic TSOP (FPT-48P-M19)
LEAD
Resin protruction. (Each side: 0.15(.006) Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008)
12.00±0.20
(.472±.008) 11.50REF (.460) 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height)
0.10(.004)
0.50(.0197) 0.15±0.05 (.006±.002) 0.20±0.10 (.008±.004)
0.05(0.02)MIN (STAND OFF) 0.10(.004)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004)
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions (inches)
(Continued)
48-pin plastic TSOP (FPT-48P-M20)
LEAD
Resin protrusion. (Each side: 0.15(.006) Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 0.20±0.10 (.008±.004) 0.10(.004)
0.10(.004)
0.50(.0197)
0.05(0.02)MIN (STAND OFF)
1.10 -0.05
+0.10 +.004
18.40±0.20
(.724±.008) 20.00±0.20 (.787±.008)
11.50(.460)REF
.043 -.002 (Mounting height)
12.00±0.20(.472±.008)
1996 FUJITSU LIMITED F48030S-2C-2
Dimensions (inches)
(Continued)
44-pin plastic (FPT-44P-M16)
28.45 -0.20 1.120 -.008
+0.25
+.010
2.35±0.15(.093±.006) (Mounting height)
0.80±0.20 (.031±.008)
13.00±0.10 16.00±0.20 (.512±.004) (.630±.008)
14.40±0.20 (.567±.008)
INDEX
LEAD
1.27(.050)TYP
0.15±0.05 (.006±.002)
0.10(.004)
0.40 -0.05 .016 -.002 26.67(1.050)REF
+0.10 +.004
0.20 -0.15 .008 -.006 (Stand off)
+0.10
+.004
1998 FUJITSU LIMITED F44023S-4C-4
Dimensions (inches)
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inhereut chance inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9907 FUJITSU LIMITED Printed Japan

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