Pulse Width Modulators Independent Clock Rates 7-bit Duty Cycle Granul
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Pulse Width Modulators Independent Clock Rates 7-bit Duty Cycle Granularity Intelligent Auto Power Management 2.88MB Super Floppy Disk Controller Relocatable Different Addresses Options Options Open Drain Push-Pull Configurable Output Drivers Licensed CMOS 765B Floppy Disk Controller Advanced Digital Data Separator Software Register Compatible with SMC's Proprietary 82077AA Compatible Core Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes Reduced Power Consumption Supports Floppy Drives Directly Drivers Power CMOS Design Licensed CMOS 765B Floppy Disk Controller Core Supports Vertical Recording Format Byte Data FIFO 100% IBM® Compatibility Detects Overrun Underrun Conditions Drivers Schmitt Trigger Inputs Enable Logic Data Rate Drive Control Registers Enhanced Digital Data Separator
Cost Implementation Filter Components Required Mbps, Mbps, Kbps, Kbps, Kbps Data Rates Programmable Precompensation Modes Multi-ModeParallel Port with ChiProtect- Relocatable Different Addresses Options Options Enhanced Mode Standard Mode: PC/XT, PC/AT, PS/2Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible (IEEE 1284 Compliant) High Speed Mode Microsoft Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) Incorporates ChiProtectCircuitry Protection Against Damage Printer Power-On Output Drivers Serial Ports Relocatable Different Addresses Options High Speed NS16C550 Compatible UARTs with Send/Receive Byte FIFOs Programmable Baud Rate Generator Modem Control Circuitry Including 230K 460K Baud IrDA, HP-SIR, ASK-IR Support QFP/TQFP Package Options
TABLE CONTENTS
GENERAL DESCRIPTION CONFIGURATION DESCRIPTION FUNCTIONS ALTERNATE FUNCTION LIST BUFFER TYPE DESCRIPTIONS FUNCTIONAL DESCRIPTION AUTO POWER MANAGEMENT FLOPPY DISK CONTROLLER INSTRUCTION DATA TRANSFER COMMANDS CONTROL COMMANDS COMPATIBILITY SERIAL PORT (UART) REGISTER DESCRIPTION PROGRAMMABLE BAUD RATE GENERATOR FIFO INTERRUPT MODE OPERATION FIFO POLLED MODE OPERATION NOTES SERIAL PORT FIFO MODE OPERATION INFARED COMMUNICATIONS CONTROLLER (IRCC)
INTEGRATION IRCC LOGIC INTO ORION DEVICE IRRX IRTX ENABLE .106 REGISTERS LOGICAL DEVICE CHANNELS IRQS .108 PARALLEL PORT PARALLEL PORT INTERFACE MULTIPLEXOR .135 HOST (LEGACY) PARALLEL PORT INTERFACE (FDC37C957FR STANDARD) .136 PARALLEL PORT INTERFACE PARALLEL PORT 8051 CONTROL (FDC37C957FR STANDARD) .137 8051 EMBEDDED CONTROLLER FEATURES .138 8051 FUNCTIONAL OVERVIEW .138 8051 MEMORY 8051 CONTROL REGISTERS .147 WATCH TIMER .162 SHARED FLASH INTERFACE .164 8051 SYSTEM POWER MANAGEMENT KEYBOARD CONTROLLER .179 MAILBOX REGISTER INTERFACE PS/2 INTERFACE DESCRIPTION ACCESS INTERFACE DESCRIPTION .196
CONTROLS PULSE WIDTH MODULATORS .201 REAL TIME CLOCK CMOS ACCESS 8051 CONTROLLED PARALLEL PORT 8051 CONTROLLED PORT .207 GENERAL PURPOSE (GPIO) MULTIPLEXED PINS .214 REAL TIME CLOCK VCC1 .224 INTERNAL REGISTERS: .225 TIME CALENDAR ALARM .226 UPDATE CYCLE CONTROL STATUS REGISTERS INTERRUPTS FREQUENCY DIVIDER .233 PERIODIC INTERRUPT SELECTION POWER MANAGEMENT .234 ACCESS BACKGROUND REGISTER DESCRIPTION .236 PS/2 DEVICE INTERFACE .242 PS/2 LOGIC OVERVIEW .242
PS/2 EMULATION LOGIC REGISTER OPERATIONAL DESCRIPTION. .243 SERIAL INTERRUPTS .247 FDC37C957FR CONFIGURATION CONFIGURATION ELEMENTS .251 CONFIGURATION REGISTERS .254 OPEN MODE REGISTERS .277 TYPICAL SEQUENCE CONFIGURATION OPERATION APPENDIX (CONFIGURATION SECTION) .281 ELECTRICAL SPECIFICATIONS TIMING DIAGRAMS LOAD CAPACITANCE .290
GENERAL DESCRIPTION
FDC37C957FR incorporates 8051 based keyboard controller; Flash Interface; four PS/2 ports; real-time clock; SMC's true CMOS 765B floppy disk controller with advanced digital data separator byte data FIFO; 16C550 compatible UARTs, second UART contains Synchronous Communications Engine provide IrDA (Fast compliance; Multi-Mode parallel port which includes ChiProtectcircuitry plus support; 8584 style Access interface; Serial peripheral agent interface; General Purpose I/O; independent pulse width modulators; on-chip drivers floppy direct drive support. true CMOS 765B core provides 100% compatibility with PC/XT PC/AT architectures addition providing data overflow underflow protection. advanced digital data separator incorporates SMC's patented data separator technology, allowing ease testing use. Both onchip UARTs compatible with NS16C550. parallel port compatible with PC/AT architecture, well ECP. 8051 controller also take control parallel port interface provide remote diagnostics "Flashing" Flash memory. FDC37C957FR three separate power planes which allows provide "instant system power management functions. Additionally, FDC37C957FR incorporates sophisticated power control circuitry (PCC). supports multiple power down modes. FDC37C957FR's configuration register compatible with Plug-and-Play Standard (Version 1.0a) provides functionality support Windows '95. Through internal configuration registers, each FDC37C957FR's logical device's address, channel channel programmed. There address location options, options, channel options each logical device. FDC37C957FR does require external filter components therefore, easy offers lower system cost reduced board area. FDC37C957FR software register compatible with SMC's proprietary 82077AA core.
IBM, PC/XT PC/AT registered trademarks PS/2 trademark International Business Machines Corporation registered trademark Ultra I/O, ChiProtect, Multi-Mode trademarks Standard Microsystems Corporation
CONFIGURATION
VCC1_PWGD nRESET_OUT 32KHz_OUT 24MHz_OUT nPWR_LED PWRGD SLCT BUSY nACK VCC2 nSLCTIN nINIT nERROR nALF nSTB RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nDCD1 nRI1 GPIO15 GPIO14 GPIO8 GPIO9 VCC1 GPIO13 GPIO10 GPIO11 GPIO12 VCC0 VCC2 CLOCKI OUT7 SIRQ PSBDAT PSBCLK nMEMWR nMEMRD nROMCS IOCHRDY DRQ1 nDACK1 DRQ0 nDACK0 VCC2 nIOW nIOR nNOWS OUT4 OUT3 OUT2 OUT1 OUT0 SA15 SA14 SA13 SA12 SA11 SA10 GPIO21
XOSEL XTAL1 XTAL2 AGND FAD0 FAD1 FAD2 FAD3 FAD4 FAD5 FAD6 FAD7 FA10 FA11 FA12 FA13 VCC1 FA14 FA15 FA16 FA17 FALE nFRD nFWR GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 MODE AB_DATA AB_CLK nBAT_LED nFDD_LED OUT11 OUT10 OUT9 OUT8 IRRX IRTX VCC2 GPIO17 GPIO18 GPIO19
FDC37C957FR
PQFP/TQFP
OUT5 OUT6 DRVDEN0 DRVDEN1 nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWPROT nRDATA nDSKCHG MID_0 GPIO16 KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 VCC2 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 EMCLK EMDAT IMCLK IMDAT KBCLK KBDAT GPIO20
FIGURE FDC37C957FR CONFIGURATION
DESCRIPTION FUNCTIONS
Name Description HOST (ISA) INTERFACE 80:82, 84:88 54:69 91,93, 202, 90,92, 207, SA[0:15] nROMCS IOCHRDY DRQ[0:3]/ OUT9,8 nDACK[0:3]/ GPIO18,19 nIOR nIOW nMEMRD nMEMWR IRQ6(FDC)/ OUT0 nIRQ8/ OUT1 IRQ7(PP)/ OUT2 IRQ12(M)/ OUT3 IRQ1(KB)/ OUT4 nNOWS System Address Chip select Address Enable (DMA master control) Channel Ready Requests Acknowledge Terminal Count Read Write Memory Read Memory Write Floppy Disk Interrupt Request/ Generic Output Active Interrupt Request Generic Output Parallel Port Interrupt Request/ Generic Output Mouse Interrupt Request/ Generic Output Keyboard Interrupt Request/ Generic Output Wait State VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 OD24 OD24 SD[0:7] System Data VCC2 I/O24 Supply Voltage Type
Name
Description FLASH ROM/ Memory Interface
Supply Voltage
Type
161:166, 168:169 170:175, 177:180
FAD[0:7]
Flash Address/Data[7:0]
VCC1
I/O8
FA[8:17]
Flash Address[17:8]
VCC1
nFRD nFWR FALE
Flash READ Flash WRITE Flash Address latch Enable Keyboard
VCC1 VCC1 VCC1
36:30,28:
KSO[0:13]
Keyboard Scan Outputs(14*8=112) Configuring GPIO4 GPIO5 KSO14 KSO15 yields scan matrix 16x8=128.
VCC1
44:37
KSI[0:7] EMCLK EMDAT IMCLK IMDAT KBCLK KBDAT
Keyboard Scan Inputs External Access Serial Serial Data Serial Serial Data Serial Serial Data
VCC1 VCC1 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
I/OD I/OD I/OD I/OD I/OD I/OD
PS2CLK/ 8051RX/ GPIO[20]
Serial
VCC2
I/OD24
Name PS2DAT/ 8051TX/ GPIO[21]
Description Serial Data
Supply Voltage VCC2
Type
I/OD24
Serial UART IRQs SIRQ IRQ3(UA1) PSBCLK PSBDAT Serial Interrupt UART1 Interrupt Clock input UART2 Interrupt VCC2 VCC2 VCC2 I/O24 /O24 I/O24 /O24
INTERFACE following output pins configured either Open Drain outputs capable sinking 24mA (OD24) push-pull outputs capable driving 12mA sinking 24mA (O24). output pins must tristate when powerdown mode required that board designer provide external pull-up resistors these output pins). nRDATA nWGATE nWDATA nHDSEL nDIR Read Disk Data Write Gate Write Disk Data Head Select side Step Direction VCC2 VCC2 VCC2 VCC2 VCC2 OD24 OD24 OD24 OD24
nSTEP nDSKCHG
Step Pulse Disk Change
VCC2 VCC2
OD24
Name nDS0 nMTR0 nDS1 OUT5
Description Drive Select Motor Drive Select Output Motor Output Write Protected Track Index Pulse Input Drive Density Select [0:1] Media input. floppy enhanced mode this input media input. Media input. floppy enhanced mode this input media input. General Purpose Floppy Power Down output control. This output three power down modes floppy (3F4, auto-power down, config). SERIAL PORT INTERFACE
Supply Voltage VCC2 VCC2 VCC2
Type OD24 OD24 OD24
nMTR1 OUT6
VCC2
OD24
nWPROT nTRK0 nINDEX DRVDEN[0:1] MID[0]
VCC2 VCC2 VCC2 VCC2 VCC2
OD24
MID[1]/
VCC2
GPIO16
I/O8 VCC2
RXD1 TXD1
Receive Serial Data Transmit Serial Data
VCC2 VCC2
Name nRTS1 nCTS1 nDTR1 nDSR1 nDCD1 nRI1
Description Request Send Clear Send Data Terminal Ready Data Ready Data Carrier Detect Ring Indicator SERIAL PORT INTERFACE
Supply Voltage VCC2 VCC2 VCC2 VCC2 VCC2 VCC1
Type
RXD2 GPIO8 TXD2 GPIO9 nRTS2 GPIO10 nCTS2 GPIO11 nDTR2 GPIO12 nDSR2 GPIO13 nDCD2 GPIO14 nRI2 GPIO15
Receive Serial Data General Purpose Transmit Serial Data General Purpose Request Send General Purpose Clear Send General Purpose Data Terminal Ready2 General Purpose Data Ready General Purpose Data Carrier Detect General Purpose Ring Indicator General Purpose PARALLEL PORT INTERFACE
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8
124:121, 119:116
PD[0:7]
Parallel Port Data
VCC2
I/O24
nSLCTIN nINIT
Printer Select Initiate Output
VCC2 VCC2
OD24/ OD24/
Name nALF nSTB BUSY nACK SLCT nERROR
Description Auto Line Feed Strobe Signal Busy Signal Acknowledge Handshake Paper Printer Selected Error Printer
Supply Voltage VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
Type OD24/ OD24/
XTAL1 XTAL2
32Khz Crystal Input 32Khz Crystal Output Miscellaneous
VCC0 VCC0
ICLK2
OCLK2
nSMI OUT7
System Management Interrupt Output 32KHz 32KHz output enabled disabled setting clearing bit-0 Output Enable 8051 memory mapped register. When disabled 32KHz_OUT driven low. 32KHz_OUT defaults disabled state VCC1 POR. Programmable Clock Output. 1.8432MHz (default 24MHz 14.318MHz 16MHz 24MHz 48MHz
VCC2
32KHz_OUT
VCC1
24MHz_OUT
VCC2
Name CLOCKI AB_DATA AB_CLK MODE XOSEL
Description 14.318Mhz Clock Input Serial Data Clock Configuration register address Test Mode Enable Input Pin. XOSEL required qualify defined test modes. XOSEL prevents test modes from ever being invoked.
Supply Voltage VCC2 VCC1 VCC1 VCC1 VCC1
Type ICLK I/OD8 I/OD8
IRRX IRTX PWM0 OUT10
Infared Receive Infared Transmit Pulse Width Modulator Output Pulse Width Modulator Output VCC1 Power Good Input pin. trailing edge VCC1 released 20ms from assertion this pin. this pulled while VCC1 valid, then VCC1 will asserted held until 20ms from re-assertion this pin. This internal weak (90uA) pull-up VCC1. System reset (active low) Battery (0=on) Power (0=on)
VCC2 VCC2 VCC2
PWM1 OUT11
VCC2
VCC1_PWGD
VCC1
nRESET_OUT nBAT_LED nPWR_LED
VCC2 VCC1 VCC1
OD24 OD24
Name nFDD_LED
Description Floppy LED. This asserted whenever either DRVSEL1 DRVSEL0 asserted controlled 8051. (0=on) Powergood Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Wakeup event Interrupt event General Purpose Inputs/Outputs
Supply Voltage VCC1
Type OD24
184:191, 141:142, 145,146, 147, 144,140, 206:208 52:53
PWRGD WK_EE4 WK_EE2 WK_EE3 nGPWKUP WK_HL1 WK_HL2 WK_HL6 WK_EE1 WK_HL3 GPIO0 WK_HL4 GPIO1 WK_HL5 GPIO2 TRIGGER GPIO3 GPIO[0:7] GPIO[8:9,10] GPIO[11,12, GPIO[14,15] GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
I/O8 I/O8 I/O8 I/O8 I/O8
General Purpose Inputs/Outputs
VCC2
IS/O8 I/O8
General Purpose Inputs/Outputs
VCC2
OD24
70:72, 74:75, 102, 202:199 148:155
Name OUT5-OUT6 OUT0-OUT2, OUT3-OUT4, OUT7 OUT8 OUT11 IN0-IN7
Description Output Outputs 7-9,
Supply Voltage VCC2 VCC2
Type
Generic Inputs
VCC1
Table Power List Bias Pins 143,176 29,83,104, 120,205 107, 132, 167, AGND Analog Ground VCC0. Ground VCC0 VCC1 VCC2 Supply Voltage 8051 +4.7V Supply Voltage Core Supply Voltage
ALTERNATE FUNCTION LIST
Table Alternate Function List
Number Default OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 Function Alternate IRQ6 (FDC) nIRQ8 IRQ7 (PP) IRQ12(Mouse) IRQ1(KBD) nDS1 nMTR1 nSMI DRQ2 (note1) CPU_RESET DRQ3 (note1) PWM0 PWM1 WK_EE4 WK_EE2
WK_EE3
Type Default O124 O124 O124 O124 O124 O124 O124 O124 O124 O124 Alternate O124 O124 O124 O124 O124 O24/OD24 O24/OD24 O124 O124 O124 O124 O124
Control MISC0
Plane
VCC2
MISC5 MISC0 MISC10 MISC6 MISC11 MISC4 alternate input masked wake-up mask Register bits VCC1
GPIO0 GPIO1 GPIO2 GPIO3
nGPWKUP WK_HL1 WK_HL2 WK_HL6 WK_EE1 WK_HL3 WK_HL4 WK_HL5 TRIGGER
I/O8 I/O8 I/O8 I/O8
Masked INT1 mask register bit3. MISC9
VCC1
GPIO4 GPIO5 GPIO6 GPIO7
KSO14 KSO15 IR_MODE
I/O8 I/O8 I/O8 I/O8
MISC[14:13]
Number Default GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 SIRQ KSO12 KSO13
Function Alternate COM-RX COM-TX nRTS2 IR_MODE nCTS2 nDTR2 nDSR2 nDCD2 nRI2 MID1 GATEA20 nDACK2 (note1) nDACK3 (note1) PS2CLK 8051RX PS2DAT 8051TX IRQ3 (UA1) OUT8 GPIO18 Default I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 IS/O8 I/O8 I/O8 I/O8 I/OD24 I/OD24
Type Alternate (note2) (note1) (note2) I/OD24 I/OD24 OD24
Control MISC7
MISC[16:15]
Plane
MISC12
MISC8 MISC6 MISC17 MISC11 MISC1 MISC3 MISC0 MISC17 MISC17
VCC2
VCC1
Alternate Function Notes:
NOTE1 With inclusion Fast additional channel provided. NOTE2: When GPIO6, GPIO9, GPIO10 and/or GPIO12 configured IR_MODE, COM-TX, nRTS2|IR_MODE, and/or nDTR2 respectively POWERGOOD=0 (VCC2 low) then these pins will tri-state prevent back-biasing external circuitry.
Control Column Table lists Misc Bits which 8051 access through three Multiplexing registers. 8051 section this spec description Multiplexing registers.
Buffer Type Descriptions
ICLK ICLK2 OCLK2 O8SR OD16 OD24 OD48 Input, compatible. Input with Schmitt trigger Input with Schmitt trigger, 90uA pull-up. Input crystal oscillator circuit (CMOS levels) Crystal input Output external crystal Output, sink, source. Output, sink, source. Open Drain Output, sink. Output, sink, source with Slew Rate Limiting Output, 16mA sink, source. Open Drain Output, 16mA sink. Output, 24mA sink, 12mA source. Output, 9Open Drain, 24mA sink. Output, Open Drain, 48mA sink
FUNCTIONAL DESCRIPTION
VCC1(2) VCC2(5) GND(9) nIOR SA[0:15] SD[O:7] DRQ[0:1] nDACK[0:1] IRQ4 IRQ[1,6-8,12] (*2) IRQ[3] (*3), nSMI (*2) ICRY SIRQ/PSB MNGMN GNRL PURPOSEI/O
ADES
YRST
SPRT WRITE RDATA RCLOCK WCLOCK WDATA
nDT, TXD1,nRTS1,nDTR1 nRI1 nTRK0, nINDEX, MID0, MID1(*1) nWGATE, nHDSEL, nDIR, nSTEP, nDS0, nDS1(*2), nMTR0, nMRT1(*2), DRVDEN0, DRVDEN1(*2),
ADES
PITR
ADES
NRRD
TXD2(*1),nRTS2(*1),nDTR2(*1) RXD2(*1),nCTS2(*1),nDSR2(*1), nDCD2(*1), nRI2 (*1) PD[0:7] nSTB,nSLCTIN,nINIT,nALF SIRQ 33MHz_IN(PCICLK) OUT0-11 GPIO16-21 GPIO0-15 KSI[0:7] KS0[O:13] KSO[14:15](*2)
CONTROL ADES
CONTROL
KYOR
8051
(14.318MHz) two128Bbanks GNRT
8051 ETRA 256BExternal
PS/2PORTS
256BDirectRAM
28F020(2Mbit)
PWM0(*2),PWM1(*2) [0:7] FA[8:17],nFRD,nFWR,FALE
Ring Oscilator
GPIO multiplexed option multiplexed option *3-MuxedwithSIRQandPSBDATApins
FIGURE FUNCTIONAL BLOCK DIAGRAM
FDC37C957FR OPERATING REGISTERS address map, shown below Table shows operating registers addresses each logical blocks FDC37C957FR Ultra controller. base addresses FDC, Parallel, Serial Serial ports moved configuration registers. HOST PROCESSOR INTERFACE host processor communicates with FDC37C957FR through series read/write registers. range base port addresses these registers shown Table Register access accomplished through programmed transfers. registers bits. Most registers support zero wait-state access (NOWS). host interface output buffers capable sinking minimum Table FDC37C957FR OPERATING REGISTER ADDRESSES NOWS Fixed Cycle Logical Base Type Device Range Base Offsets (note3) [0x100:0x0FF8] BYTE BOUNDARIES MSR/DSR FIFO +7:DIR/CCR NOWS
Logical Device Number 0x00
0x03
Parallel Port
[0x100:0x0FFC] BYTE BOUNDARIES (EPP supported) [0x100:0x0FF8] BYTE BOUNDARIES (all modes supported, only available when base address 8byte boundary)
Data ecpAfifo +400h cfifo Control cnfgA Statustfifo ecpDfifo +401h cnfgB +402h
Logical Device Number
Logical Device
Base Range (note3)
Fixed Base Offsets Address Data Data
Cycle Type Std. NOWS
0x04
Serial Port
[0x100:0x0FF8] BYTE BOUNDARIES
RB/TB IIR/FCR LCR| NOWS
0x05
Serial Port
[0x100:0x0FF8] BYTE BOUNDARIES
RB/TB IIR/FCR LCR|
0x62, 0x63
[0x100:0x0FF8] BYTE BOUNDARIES
Register Block address Register Block address Register Block address Register Block address Register Block address Register Block address Register Block address USRT Master Control Reg.
Logical Device Number 0x06
Logical Device
Base Range (note3) Relocatable Fixed Base Address
Fixed Base Offsets 0x70, 0x74 Address Register 0x71, 0x76 Data Register
Cycle Type NOWS NOWS
0x07
KYBD
0x64 Command/Status Reg. Note Refer configuration register descriptions setting base address Note Serial Port supports Infrared.
Relocatable Fixed Base Address
0x60 Data Register
AUTO POWER MANAGEMENT
Auto Power management capabilities provided following logical devices: Floppy Disk, UART UART Parallel Port. each logical device, types power management provided; direct powerdown auto powerdown. System Power Management "8051 System Power Management" section details. Power Management Direct power management controlled through Global Configuration Register (CR22). Refer CR22 Configuration section more information. Auto Power Management enabled through bit-0 CR23. When set, this allows enter powerdown when following conditions have been met: motor enable pins FDC's register inactive (zero). part must idle; register =80h FDC's INTerrupt (INT high even polling interrupts). head unload timer must have expired. Auto powerdown timer (10msec) must have timed out.
internal timer initiated soon auto powerdown command enabled. part then powered down when conditions met. Disabling auto powerdown mode cancels timer holds block auto powerdown. From Powerdown Bit-6 FDC's register another powerdown bit. powerdown used when part auto powerdown, powerdown will override auto powerdown. However, when part awakened from powerdown, auto powerdown will once again become effective.
Wake From Auto Powerdown part enters powerdown state through auto powerdown mode, then part awakened reset appropriate access certain registers. hardware software reset used then part will through normal reset sequence. access through selected registers, then resumes operation though never powerdown. Besides activating RESET software reset bits registers, following register accesses will wake part: Enabling motor enable bits register (reading does awaken part). read from register. read write Data register. part will
Once awake, will reinitiate auto powerdown timer powerdown again when powerdown conditions satisfied. Register Behavior
Table reiterates PS/2 (including Model configuration registers available. also shows type access permitted. order maintain software transparency, access registers maintained. Table shows, sets registers distinguished based whether their access results part remaining powerdown state exiting Access other registers possible without awakening part. These registers accessed during powerdown without changing status part. read from these registers will reflect true status shown register description section. Writes these registers will result part retaining data subsequently reflecting when part awakens. Accessing part during powerdown cause increase power consumption part. part will revert back power mode when access been completed. Behavior FDC37C957FR specifically designed portable systems which power conservation primary concern. This makes behavior pins during powerdown very important. pins which interface floppy disk drive disabled that power will drawn through part result voltage applied within VCC2 power supply range. Most pins which interface system left active monitor system accesses that wake part.
System Interface Pins Table gives state system interface pins powerdown state. Pins unaffected powerdown labeled "Unchanged". Input pins "Disabled" prevent them from causing currents internal FDC37C957FR when they have indeterminate input values. Table PC/AT PS/2 Available Registers Base Address Available Registers Access Permitted PC-AT PS/2 (Model Access these registers DOES wake part -DOR -DSR -DIR Data -DSR -DIR Data
Access these registers wakes part
Note Writing does wake part, however, writing motor enable bits doing software reset (via reset bits) will wake part
Table State System Pins Auto Powerdown System Pins State Auto Powerdown Input Pins nIOR nIOW nMEMRD nMEMWR SA[15:0] SD[7:0] nNOWS nDACKx nROMCS RESET_OUT IRQx DB[0:7] DRQx IOCHRDY Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged(hi-Z) Unchanged Unchanged Unchanged Output Pins Unchanged Unchanged(low) Unchanged Unchanged(low) Unchange(n/a)
Interface Pins pins interface which connected directly floppy disk drive itself either DISABLED TRISTATED. Pins used local logic control part programming unaffected. Table depicts state floppy disk drive interface pins powerdown state. Power Down (FPD) Behavior used automatically shut power Floppy Disk Drive when required. active high output signal which driven based states Floppy Disk Controller. Whenever Shutdown (see Mode Register, bit-5 Configuration Register Section) goes high. Shutdown then will high whenever (see bit-0 Power Mgmt Register Configuration Section) entered auto-powerdown state described above. neither Shutdown then goes active "high" when Power Down (see bit-6 Data Rate Select Register [DSR] "low" when Power Down cleared. Refer Table
Table State Floppy Disk Drive Interface pins Powerdown Pins State Auto Powerdown Input Pins nRDATA nWPROT nTRK0 nINDEX nDSKCHG Output Pins nMTR[1:0] nDS[1:0] nDIR nSTEP nWDATA WGATE nHDSEL DRVDEN[1:0] Tristated Tristated Active Active Tristated Tristated Active Active Active Input Input Input Input Input
Table Behavior Power Down bit, bit, GCR23 bit-0 Shutdown bit, State DSR, bit-6 Auto Power Down Mode Register (note Note will active when Floppy Disk Controller auto powers down. Refer auto power management more details.
UART Power Management Direct power management controlled CR22. Refer CR22 Configuration Section more information. Auto Power Management enabled CR23 bit-4 bit-5. following auto power management operations: When set, these bits allow
transmitter enters auto powerdown when transmit buffer shift register empty. receiver enters powerdown when following conditions met: Receive FIFO empty receiver waiting start bit. While powerdown Ring Indicator interrupt still valid.
Note:
Exit Auto Powerdown transmitter exits powerdown write transmit buffer. receiver exits auto powerdown when changes state. Parallel Port Power Management Direct power management controlled CR22. Refer CR22 Configuration Section more information. Auto Power Management enabled CR23 bit-3. When set, this allows logical parallel port blocks placed into powerdown when being used. logic powerdown under following conditions: enabled configuration registers. selected through while mode.
logic powerdown under following conditions: enabled configuration registers. SPP, PS/2 Parallel port mode selected through while mode.
Exit Auto Powerdown parallel port logic change powerdown modes when mode changed through register when parallel port mode changed through configuration registers.
FLOPPY DISK CONTROLLER
Floppy Disk Controller (FDC) provides interface between host microprocessor floppy disk drives. integrates functions Formatter/Controller, Digital Data Separator, Write Precompensation Data Rate Selection logic XT/AT compatible FDC. true CMOS 765B core guarantees 100% XT/AT compatibility addition providing data overflow underflow protection. compatible 82077AA using SMC's proprietary floppy disk controller core. INTERNAL REGISTERS Floppy Disk Controller contains eight internal registers which facilitate interfacing between host microprocessor disk drive. shows addresses required access these registers. Registers other than ones shown supported.
Table Status, Data Control Registers PRIMARY BASE ADDRESS OFFSET REGISTER Status Register Status Register Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register
FIFO
STATUS REGISTER (SRA) Base Address 0x00 (READ ONLY) This register read-only monitors state Floppy Disk Controller's Interrupt several disk interface pins PS/2 Model modes. accessed time when PS/2 mode. PC/AT mode data pins held high impedance state read SRA. PS/2 Mode PENDING nDRV2 STEP nTRK0 HDSEL nINDX
RESET COND.
DIRECTION Active high status indicating direction head movement. logic indicates inward direction; logic indicates outward direction. nWRITE PROTECT Active status WRITE PROTECT disk interface input. logic indicates that disk write protected. nINDEX Active status INDEX disk interface input. HEAD SELECT Active high status HDSEL disk interface input. logic selects side logic selects side nTRACK Active status TRK0 disk interface input. STEP Active high status STEP output disk interface output pin. nDRV2 Active status DRV2 disk interface input pin, indicating that second drive been installed. INTERRUPT PENDING Active high indicating state Floppy Disk Interrupt output.
PS/2 Model Mode PENDING STEP TRK0 nHDSE INDX nDIR
RESET COND.
nDIRECTION Active status indicating direction head movement. logic indicates inward direction; logic indicates outward direction. WRITE PROTECT Active high status WRITE PROTECT disk interface input. logic indicates that disk write protected. INDEX Active high status INDEX disk interface input. nHEAD SELECT Active status HDSEL disk interface input. logic selects side logic selects side TRACK Active high status TRK0 disk interface input. STEP Active high status latched STEP disk interface output pin. This latched with STEP output going active, cleared with read from register, with hardware software reset. REQUEST Active high status Floppy Disk Controller's output pin. INTERRUPT PENDING Active high indicating state Floppy Disk Interrupt output.
STATUS REGISTER (SRB) Base Address 0x01 (READ ONLY) This register read-only monitors state several disk interface pins PS/2 Model modes. accessed time when PS/2 mode. PC/AT mode data pins held high impedance state read SRB. PS/2 Mode RESET COND. DRIVE SEL0 WDATA TOGGLE RDATA WGATE TOGGLE
MOTOR ENABLE Active high status MTR0 disk interface output pin. This after hardware reset unaffected software reset. MOTOR ENABLE Active high status MTR1 disk interface output pin. This after hardware reset unaffected software reset. WRITE GATE Active high status WGATE disk interface output. READ DATA TOGGLE Every inactive edge RDATA input causes this change state. WRITE DATA TOGGLE Every inactive edge WDATA output causes this change state. DRIVE SELECT Reflects status Drive Select (address This cleared after hardware reset unaffected software reset. RESERVED Always read logic "1". RESERVED Always read logic "1".
PS/2 Model Mode nDRV2 nDS1 RESET COND. nDS0 WDATA RDATA WGATE nDS3 nDS2
nDRIVE SELECT Active status disk interface output. nDRIVE SELECT Active status disk interface output. WRITE GATE Active high status latched WGATE output signal. This latched active going edge WGATE cleared read register. READ DATA Active high status latched RDATA input signal. This latched inactive going edge RDATA cleared read register. WRITE DATA Active high status latched WDATA output signal. This latched inactive going edge WDATA cleared read register. This gated with WGATE. nDRIVE SELECT Active status disk interface output. nDRIVE SELECT Active status disk interface output. nDRV2 Active status DRV2 disk interface input.
DIGITAL OUTPUT REGISTER (DOR) Base Address 0x02 (READ/WRITE) controls drive select motor enables disk interface outputs. also contains enable logic software reset bit. contents unaffected software reset. written time. DMAEN nRESE DRIVE SEL1 DRIVE SEL0
RESET COND.
DRIVE SELECT These bits binary encoded drive selects output pins nDS0 nDS1, thereby allowing only drive selected time. nRESET logic written this resets Floppy disk controller. This reset will remain active until logic written this bit. This software reset does affect registers, does affect other bits register. minimum reset duration required 100ns, therefore toggling this consecutive writes this register valid method issuing software reset. DMAEN PC/AT Model Mode: Writing this logic will enable FDC's nDACK inputs enable FDC's Interrupt outputs. This being logic will disable FDC's nDACK inputs, hold FDC's Interrupt outputs high impedance state. This logic after reset. PS/2 Mode: this mode FDC's DRQ, nDACK, Interrupt pins always enabled. During reset, DRQ, nDACK, Interrupt pins will remain enabled, this will cleared logic "0". MOTOR ENABLE This controls nMTR0 disk interface output. logic this will cause output assert. MOTOR ENABLE This controls nMTR1 disk interface output. logic this will cause output assert.
MOTOR ENABLE This controls nMTR2 disk interface output. logic this will cause output assert. MOTOR ENABLE This controls nMTR3 disk interface output. logic this will cause output assert. Table Drive Activation Values DRIVE VALUE
Table Internal Drive Decode Normal
DIGITAL OUTPUT REGISTER Bit1 DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 nDS0 MOTOR OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT
Table Internal Drive Decode Drives swapped
DIGITAL OUTPUT REGISTER Bit1 DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 nDS0 MOTOR OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT nBIT
TAPE DRIVE REGISTER (TDR) Base Address 0x03 (READ/WRITE) This register included 82077 software compatability. robust digital data separator used does require characteristics modified tape support. contents this register used internal device. unaffected software reset. Normal Floppy Mode Normal mode. Register contains only bits When this register read, bits high impedance. Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0
Table Tape Select Bits TAPE SEL1 Enhanced Floppy Mode (OS2) Register Enhanced Floppy Mode operation. Media Media Drive Type Floppy Boot Drive tape sel1 tape sel0 TAPE SEL2 DRIVE SELECTED None
this mode, MID[1:0] pins gated into bits register. These bits affected hard soft reset. MEDIA (READ ONLY) (Pin (See Table Media ID1) MEDIA (READ ONLY) (Pin (See Table
BITS Drive Type These bits reflect bits L0-CRF1 (Logical Device Configuration Register 0xF1). Which bits these depends last drive selected Digital Output Register. (See Table Table Media MEDIA L0-CRF1-B5 L0-CRF1-B5 L0-CRF1-B5 Logical Device Configuration Register Input
Note:
BITS Floppy Boot Drive These bits reflect bits L0-CRF1. L0-CRF1-B7. L0-CRF1-B6. Bits Tape Drive Select (READ/WRITE) Same Normal Enhanced Floppy Mode
Table Media MEDIA CRF1-B4 CRF1-B4 Input
Table Drive Type Digital Output Register Register Drive Type L0-CRF2 L0-CRF2 L0-CRF2 L0-CRF2 L0-CRF2 L0-CRF2 L0-CRF2 L0-CRF2 Note: L0-CRF2-Bx Logical Device Configuration Register
DATA RATE SELECT REGISTER (DSR) Base Address 0x04 (WRITE ONLY) This register write only. used program data rate, amount write precompensation, power down status, software reset. data rate programmed using Configuration Control Register (CCR) DSR, PC/AT PS/2 Model Microchannel applications. Other applications data rate DSR. data rate floppy controller most recent write either CCR. unaffected software reset. hardware reset will 02H, which corresponds default precompensation setting Kbps.
RESET COND.
RESET
POWER DOWN
PRECOMP2
PRECOMP1
PRECOMP0
DRATE SEL1
DRATE SEL0
DATA RATE SELECT These bits control data rate floppy controller. Table settings corresponding individual data rates. data rate select bits unaffected software reset, Kbps after hardware reset. through PRECOMPENSATION SELECT These three bits select value write precompensation that will applied WDATA output signal. Table shows precompensation values combination these bits settings. Track default starting track number start precompensation. this starting track number changed configure command. UNDEFINED Should written logic "0". POWER logic written this will floppy controller into manual power mode. floppy controller clock data separator circuits will turned off. controller will come manual power mode after software reset access Data Register Main Status Register. SOFTWARE RESET This active high same function RESET (DOR except that this self clearing.
Table Precompensation Delays PRECOMP PRECOMPENSATION DELAY (nsec) <2Mbps 2Mbps 0.00 20.8 41.67 41.7 83.34 62.5 125.00 83.3 166.67 104.2 208.33 250.00 Default Default Default: Table Table Data Rates DATA RATE DATA RATE DENSEL DRT1 DRT0 SEL1 SEL0 1Meg 1Meg 1Meg 2Meg -250 -250 -250 -125
DRIVE RATE
DRATE(1)
Drive Rate Table (Recommended) 360K, 1.2M, 720K, 1.44M 2.88M Vertical Format 3-Mode Drive Tape Note DRATE DENSEL values mapped onto DRIVEDEN pins.
Table DRVDEN Mapping DRVDEN1 DRVDEN0 DRIVE TYPE DRATE0 DENSEL 4/2/1 3.5" 5.25" FDDS 2/1.6/1 3.5" (3-MODE) DRATE0 DRATE1 DRATE0 nDENSEL PS/2 DRATE1 DRATE0
Table Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 20.8 Mbps 41.67 Mbps Kbps Kbps Kbps Mbps data rate only available
MAIN STATUS REGISTER Base Address 0x04 (READ ONLY) Main Status Register read-only register indicates status disk controller. Main Status Register read time. indicates when disk controller ready receive data Data Register. should read before each byte transferring from data register except mode. delay required when reading after data transfer. BUSY DRV3 BUSY DRV2 BUSY DRV1 BUSY DRV0 BUSY
DRVx BUSY These bits when drive seek portion command, including implied overlapped seeks recalibrates. COMMAND BUSY This when command progress. This will active after command byte been accepted goes inactive results phase. there result phase (Seek, Recalibrate commands), this returned after last command byte. NON-DMA This mode selected SPECIFY command will during execution phase command. This polled data transfers helps differentiate between data transfer phase reading result bytes. Indicates direction data transfer once set. indicates read indicates write required. Indicates that host transfer data access permitted DATA REGISTER (FIFO) Base Address 0x05 (READ/WRITE) command parameter information, disk data result status transferred between host processor floppy disk controller through Data Register. Data transfers governed bits Main Status Register. Data Register defaults FIFO disabled mode after form reset. This maintains PC/AT hardware compatibility. default values changed through Configure command (enable full FIFO operation with threshold control). advantage FIFO that allows system larger latency without causing disk error. Table gives several examples delays with FIFO. data based upon following formula:
Threshold [8/DATA RATE] 1.5ms Delay start command, FIFO action always disabled command parameters must sent based upon settings. command execution phase entered, FIFO cleared data ensure that invalid data transferred. overrun underrun will terminate current command transfer data. Disk writes will complete current sector generating pattern valid CRC. Reads require host remove remaining data that result phase entered. Table FIFO Service Delay FIFO THRESHOLD MAXIMUM DELAY SERVICING EXAMPLES Mbps* DATA RATE byte bytes 30.5 bytes 58.5 bytes FIFO THRESHOLD EXAMPLES byte bytes bytes bytes MAXIMUM DELAY SERVICING Mbps DATA RATE 14.5 62.5 118.5
FIFO THRESHOLD MAXIMUM DELAY SERVICING EXAMPLES Kbps DATA RATE byte 14.5 bytes 30.5 bytes 126.5 bytes 238.5 Mbps data rate only available nominal.
DIGITAL INPUT REGISTER (DIR) Base Address 0x07 (READ ONLY) This register read-only modes. PC-AT Mode
RESET COND.
UNDEFINED data outputs will remain high impedance state during read this register. DSKCHG This monitors same name reflects opposite value seen disk cable. PS/2 Mode RESET COND. DRATE SEL1 DRATE SEL0 nHIGH DENS
nHIGH DENS This whenever Kbps Mbps data rates selected, high when Kbps Kbps selected. BITS DATA RATE SELECT These bits control data rate floppy controller. Table settings corresponding individual data rates. data rate select bits unaffected software reset, Kbps after hardware reset. BITS UNDEFINED Always read logic DSKCHG This monitors same name reflects opposite value seen disk cable.
Model Mode DMAEN NOPREC DRATE SEL1 DRATE SEL0
RESET COND.
BITS DATA RATE SELECT These bits control data rate floppy controller. Table settings corresponding individual data rates. data rate select bits unaffected software reset, Kbps after hardware reset. NOPREC This reflects value NOPREC register. DMAEN This reflects value DMAEN register BITS UNDEFINED Always read logic DSKCHG This monitors same name reflects opposite value seen pin.
CONFIGURATION CONTROL REGISTER (CCR) Base Address 0x07 (WRITE ONLY) PC/AT PS/2 Mode DRATE SEL1 DRATE SEL0
RESET COND.
DATA RATE SELECT These bits determine data rate floppy controller. Table appropriate values. RESERVED Should logical PS/2 Model Mode NOPREC DRATE SEL1 DRATE SEL0
RESET COND.
DATA RATE SELECT These bits determine data rate floppy controller. Table appropriate values. PRECOMPENSATION This software, functionality. read when Model register mode. Unaffected software reset. RESERVED Should logical Table shows state DENSEL pin. DENSEL high after hardware reset unaffected resets.
STATUS REGISTER ENCODING During Result Phase certain commands, Data Register contains data bytes that give status command just executed. Table Status Register NAME DESCRIPTION Interrupt Code Normal termination command. specified command properly executed completed without error. Abnormal termination command. Command execution started, successfully completed. Invalid command. requested command could executed. Abnormal termination caused Polling. Seek completed Seek, Relative Seek Recalibrate command (used during Sense Interrupt Command). Equipment TRK0 failed become after: Check step pulses Recalibrate command. Relative Seek command caused step outward beyond Track Unused. This always "0". Head Address current head address. Drive Select current selected drive.
SYMBOL
DS1,0
Table Status Register SYMBOL NAME DESCRIPTION Cylinder tried access sector beyond final sector track (255D). Will issued after Read Write Data command. Unused. This always "0". Data Error detected error either field data field sector. Overrun/ Becomes does receive Underrun service within required time interval, resulting data overrun underrun. Unused. This always "0". Data following: Read Data, Read Deleted Data command find specified sector. Read command cannot read field without error. Read Track command cannot find proper sector sequence. Writable became while executing Write Data, Write Deleted Data, Format Track command. Missing Address following: Mark detect address mark specified track after encountering index pulse from twice. cannot detect data address mark deleted data address mark specified track.
SYMBOL
Table Status Register DESCRIPTION Unused. This always "0". Control Mark following: Read Data command encountered deleted data address mark. Read Deleted Data command encountered data address mark. Data Error detected error data field. Data Field Wrong track address from sector field different Cylinder from track address maintained inside FDC. Unused. This always "0". Unused. This always "0". Cylinder track address from sector field different from track address maintained inside equal hex, which indicates track with hard error according soft-sectored format. Missing Data cannot detect data address mark Address Mark deleted data address mark. NAME
SYMBOL DS1,0
Table Status Register NAME DESCRIPTION Unused. This always "0". Write Protected Indicates status pin. Unused. This always "1". Track Indicates status TRK0 pin. Unused. This always "1". Head Address Indicates status HDSEL pin. Drive Select Indicates status nDS1, nDS0 pins.
RESET There three sources system reset FDC: iRESET_OUT 8051's Output enable Register (which controls RESET_OUT/nRESET_OUT pins ORION); reset generated DOR; reset generated DSR. VCC2 power VCC2 Power Reset initializes FDC. resets take power down state. operations terminated upon RESET, enters idle state. reset while disk write progress will corrupt data CRC.
exiting reset state, various internal registers cleared, including Configure command information, waits command. Drive polling will start unless disabled Configure command. RESET_OUT (Hardware Reset) RESET_OUT global reset clears registers except those programmed Specify command. reset enabled must cleared host exit reset state. Reset Reset (Software Reset) These resets functionally same. Both will reset core, which affects drive status information FIFO circuits. reset clears itself automatically while reset requires host manually clear reset precedence over reset. reset automatically upon RESET_OUT reset. user must manually clear this reset exit reset state. MODES OPERATION three modes operation, PC/AT mode, PS/2 mode Model mode. These determined state IDENT MFM, bits[3] respectively L0-CRF0. PC/AT mode (IDENT high, "don't care") PC/AT register enabled, enable becomes valid (The FDC's hi-Z), DENSEL become active high signals. PS/2 mode (IDENT low, high) This mode supports PS/2 models 50/60/80 configuration register set. becomes "don't care", (The FDC's always valid), DENSEL become active low. Model mode (IDENT low, low) This mode supports PS/2 Model configuration register set. enable becomes valid (The FDC's hi-Z), active high DENSEL active low. TRANSFERS transfers enabled with Specify command initiated activating during data transfer command. FIFO enabled directly asserting nDACK addresses need valid. Note that controller (i.e. 8237A) programmed function verify mode, pseudo read performed based only nDACK. This mode only available when been configured into byte mode (FIFO disabled) programmed read. With FIFO
enabled, perform above operation using Verify command; operation needed. CONTROLLER PHASES simplicity, command handling divided into three phases: Execution, Result. Each phase described following sections. Command Phase After reset, enters command phase ready accept command from host. each commands, defined command code bytes parameter bytes written before command phase complete. (Please refer Table command descriptions.) These bytes data must transferred order prescribed. Before writing FDC, host must examine bits Main Status Register. must equal respectively before command bytes written. false after each write cycle until received byte processed. asserts again request each parameter byte command unless illegal command condition detected. After last parameter byte received, remains automatically enters next phase defined command definition. FIFO disabled during command phase provide proper handling "Invalid Command" condition. Execution Phase data transfers from occur during execution phase, which proceed non-DMA mode indicated Specify command. After reset, FIFO disabled. Each data byte transferred depending mode. Configure command enable FIFO FIFO threshold value. following paragraphs detail operation FIFO flow control. these descriptions, <threshold> defined number bytes available when service requested from host ranges from parameter FIFOTHR, which user programs, less ranges from threshold value (i.e. results longer periods time between service requests, requires faster servicing request both read write cases. host reads (writes) from (to) FIFO until empty (full), then transfer request goes inactive. host must very responsive service request. This desired case with "fast" system. high value threshold (i.e. used with "sluggish" system affording long latency period after service request, results more frequent service requests. Command,
Non-DMA Mode Transfers from FIFO Host FDC's bits Main Status Register activated when FIFO contains (16-<threshold>) bytes last bytes full sector have been placed FIFO. FDC's used interrupt-driven systems, used polled systems. host must respond request reading data from FIFO. This process repeated until last byte transferred FIFO. will deactivate FDC's when FIFO becomes empty. Non-DMA Mode Transfers from Host FIFO FDC's Main Status Register activated upon entering execution phase data transfer commands. host must respond request writing data into FIFO. FDC's remain true until FIFO becomes full. They true again when FIFO <threshold> bytes remaining FIFO. FDC's will also deactivated nDACK both inactive. enters result phase after last byte taken from FIFO (i.e. FIFO empty condition). Mode Transfers from FIFO Host activates FDC's when FIFO contains <threshold>) bytes, last byte full sector transfer been placed FIFO. controller must respond request reading data from FIFO. will deactivate FDC's when FIFO becomes empty. FDC's goes inactive after nDACK goes active last byte data transfer active edge nIOR, last byte, edge present nDACK). data underrun occur FDC's removed time prevent unwanted cycle. Mode Transfers from Host FIFO activates FDC's when entering execution phase data transfer commands. controller must respond activating nDACK nIOW pins placing data FIFO. FDC's remains active until FIFO becomes full. FDC's again true when FIFO <threshold> bytes remaining FIFO. will also deactivate FDC's when becomes true (qualified nDACK), indicating that more data required. FDC's goes inactive after nDACK goes active last byte data transfer active edge nIOW last byte, edge present nDACK). data overrun occur FDC's removed time prevent unwanted cycle. Data Transfer Termination supports terminal count explicitly through implicitly through underrun/overrun end-of-track (EOT) functions. full sector transfers, parameter define last sector transferred single multi-sector transfer.
last sector transferred partial sector, host stop transferring data midsector, will continue complete sector hardware received. only difference between these implicit functions that they return "abnormal termination" result status. Such status indications ignored they were expected. Note that when host sending data FIFO FDC, internal sector count will complete when reads last byte from side FIFO. There delay removal transfer request signal time taken read last bytes from FIFO. host must tolerate this delay. Result Phase generation FDC's determines beginning result phase. each commands, defined result bytes read from before result phase complete. These bytes data must read another command start. must both equal before result bytes read. After result bytes have been read, bits switch respectively, cleared, indicating that ready accept next command. COMMAND SET/DESCRIPTIONS Commands written whenever command phase. Each command unique needed parameters status results. checks that first byte valid command and, valid, proceeds with command. invalid, interrupt issued. user sends Sense Interrupt Status command which returns invalid command error. Refer Table explanations various symbols used. Table lists required parameters results associated with each command that capable performing.
Table Description Command Symbols NAME DESCRIPTION Cylinder Address currently selected address; 255. Data Pattern pattern written each sector data field during formatting. Drive Select Designates which drives perpendicular drives Perpendicular Mode Command. indicates perpendicular drive. Direction Control this then head will step from spindle during relative seek. head will step toward spindle. DS0, Disk Drive Select DRIVE SYMBOL Special Sector Size drive drive drive drive
EFIFO
Enable Count Enable FIFO Enable Implied Seek
H/HDS
Track Length Head Address Head Load Time
setting zero (00), used control number bytes transferred disk read/write commands. sector size 128. actual sector diskette) larger than DTL, remainder actual sector read passed host during read commands; during write commands, remainder actual sector written with zero bytes. check code calculated with actual sector. When zero, meaning should HEX. When this "DTL" parameter Verify command becomes (number sectors track). This active when enables FIFO. disables FIFO (default). When set, seek operation will performed before executing read write command that requires parameter command phase. disables implied seek. final sector number current track. Alters length when using Perpendicular Mode. size. (Gap space between sectors excluding synchronization field). Selected head: (disk side encoded sector field. time interval that waits after loading head before initializing read write operation. Refer Specify command actual delays.
SYMBOL
NAME Head Unload Time
LOCK
DESCRIPTION time interval from execution phase read write command) until head unloaded. Refer Specify command actual delays. Lock defines whether EFIFO, FIFOTHR, PRETRK parameters CONFIGURE COMMAND reset their default values "software Reset". reset caused writing appropriate bits either DOR) MFM/FM Mode selects double density (MFM) mode. zero Selector selects single density (FM) mode. Multi-Track When set, this flag selects multi-track operating mode. Selector this mode, treats complete cylinder under head single track. operates this expanded track started first sector under head ended last sector under head With this flag set, multitrack read write operation will automatically continue first sector under head when finishes operating last sector under head Sector Size Code This specifies number bytes sector. this parameter "00", then sector size bytes. number bytes transferred determined parameter. Otherwise sector size raised "N'th" power) times 128. values "07" allowable. "07"h would equal sector size 16k. user's responsibility select combinations that possible with drive. SECTOR SIZE bytes bytes bytes 1024 bytes Kbytes
Cylinder Number Non-DMA Mode Flag
desired cylinder number. When indicates that operate non-DMA mode. this mode, host interrupted each data transfer. When operates mode, interfacing controller means nDACK signals. bits D0-D3 Perpendicular Mode Command only modified defined Lock command.
Overwrite
SYMBOL POLL PRETRK
WGATE
DESCRIPTION current position head completion Sense Interrupt Status command. When set, internal polling routine disabled. When clear, polling enabled. Precompensation Programmable from track FFH. Start Track Number Sector Address sector number read written. multi-sector transfers, this parameter specifies sector number first sector read written. Relative Cylinder Relative cylinder offset from present cylinder used Number Relative Seek command. number sectors track initialized Number Format command. number sectors track Sectors verified during Verify command when set. Track Skip Flag When sectors containing deleted data address mark will automatically skipped during execution Read Data. Read Deleted executed, only sectors with deleted address mark will accessed. When "0", sector read written same read write commands. Step Rate time interval between step pulses issued FDC. Interval Programmable from milliseconds increments Mbit data rate. Refer SPECIFY command actual delays. Status Registers within which store status information after Status command been executed. This status information Status available host during result phase after command Status execution. Write Gate Alters timing allow pre-erase loads perpendicular drives.
NAME Present Cylinder Number Polling Disable
INSTRUCTION
Table Instruction READ DATA DATA PHASE Command Execution Result Sector information after Command execution. Data transfer between system. Status information after Command execution. Command Codes REMARKS
Sector information prior Command execution.
READ DELETED DATA DATA PHASE Command Execution Result Sector information after Command execution. Data transfer between system. Status information after Command execution. Command Codes REMARKS
Sector information prior Command execution.
WRITE DATA DATA PHASE Command Execution Result Sector information after Command execution. Data transfer between system. Status information after Command execution. Command Codes REMARKS
Sector information prior Command execution.
WRITE DELETED DATA DATA PHASE Command Sector information prior Command execution. Command Codes REMARKS
Execution Result
Data transfer between system. Sector information after Command execution. Status information after Command execution.
READ TRACK DATA PHASE Command Sector information prior Command execution. Command Codes REMARKS
Execution
Data transfer between system. reads cylinders' contents from index hole EOT.
Result
Status information after Command execution.
Sector information after Command execution.
VERIFY
DATA PHASE Command Sector information prior Command execution. Command Codes REMARKS
Execution Result
DTL/SC data transfer takes place. Sector information after Command execution. Status information after Command execution.
VERSION
DATA PHASE Command Result Command Code Enhanced Controller REMARKS
FORMAT TRACK
DATA PHASE Command Execution Each Sector Repeat: Bytes/Sector Sectors/Cylinder Filler Byte Input Sector Parameters Command Codes REMARKS
formats entire cylinder
Result
Undefined Undefined Undefined Undefined
Status information after Command execution
RECALIBRATE
DATA PHASE Command Execution Head retracted Track Interrupt. Command Codes REMARKS
SENSE INTERRUPT STATUS
DATA PHASE Command Result Command Codes Status information each seek operation. REMARKS
SPECIFY
DATA PHASE Command Command Codes REMARKS
SENSE DRIVE STATUS
DATA PHASE Command Result Status information about Command Codes REMARKS
SEEK
DATA PHASE Command Execution Head positioned over proper cylinder diskette. Command Codes REMARKS
CONFIGURE DATA PHASE Command Execution POLL PRETRK RELATIVE SEEK DATA PHASE Command REMARKS Configure Information REMARKS
EFIFO
FIFOTHR
DUMPREG DATA PHASE Command *Note: Registers placed FIFO REMARKS
Execution Result LOCK SC/EOT FIFOTHR WGATE EFIFO POLL PRETRK PCN-Drive PCN-Drive PCN-Drive PCN-Drive
READ DATA PHASE Command Execution first correct information Cylinder stored Data Register Status information after Command execution. Commands REMARKS
Result
Disk status after Command completed PERPENDICULAR MODE DATA PHASE Command WGATE Command Codes REMARKS
INVALID CODES DATA PHASE Command Invalid Command Codes (NoOp goes into Standby State) Invalid Codes REMARKS
Result
LOCK DATA PHASE Command Result LOCK LOCK Command Codes REMARKS
returned last command that issued Format command. returned last command Read Write. NOTE: These bits used internally only. They reflected Drive Select pins. user's responsibility maintain correspondence between these bits Drive Select pins (DOR).
DATA TRANSFER COMMANDS
Read Data, Write Data Verify type commands same parameter bytes return same results information, only difference being coding bits first byte. implied seek will executed feature enabled Configure command. This seek completely transparent user. Drive Busy drive will active Main Status Register during seek portion command. seek portion fails, will reflected results status normally returned Read/Write Data command. Status Register (ST0) would contain error code would contain cylinder which seek failed. Read Data nine bytes required place Read Data Mode. After Read Data command been issued, loads head unloaded state), waits specified head settling time (defined Specify command), begins reading Address Marks fields. When sector address read diskette matches with sector address specified command, reads sector's data field transfers data FIFO. After completion read operation from current sector, sector address incremented data from next logical sector read output FIFO. This continuous read function called "Multi-Sector Read Operation". Upon receipt implied (FIFO overrun/underrun), stops sending data will continue read data from current sector, check bytes, sector, terminate Read Data Command. determines number bytes sector (see Table below). zero, sector size 128. value determines number bytes transferred. less than 128, transfers specified number bytes host. reads, continues read entire 128-byte sector checks errors. writes, completes 128-byte sector filling zeros. Hex, should impact number bytes transferred. Table Sector Sizes SECTOR SIZE bytes bytes bytes 1024 bytes Kbytes
amount data which handled with single command depends upon (multi-track) (number bytes/sector).
Multi-Track function (MT) allows read data from both sides diskette. particular cylinder, data will transferred starting Sector Side completing last sector same track Side host terminates read write operation FDC, information result phase dependent upon state byte. completion Read Data command, head unloaded until after Head Unload Time Interval (specified Specify command) elapsed. host issues another command before head unloads, then head settling time saved between subsequent reads. detects pulse nINDEX twice without finding specified sector (meaning that diskette's index hole passes through index detect logic drive twice), sets code Status Register "01" indicating abnormal termination, sets Status Register indicating sector found, terminates Read Data Command. After reading Data Fields each sector, checks bytes. error occurs data field, sets code Status Register "01" indicating abnormal termination, sets flag Status Register "1", sets Status Register incorrect field, terminates Read Data Command. Table describes effect Read Data command execution results. Except where noted Table value sector address automatically incremented (see Table 30). Table Effects Bits MAXIMUM TRANSFER FINAL SECTOR READ CAPACITY FROM DISK 6,656 13,312 7,680 15,360 1024 8,192 1024 16,384 side side side side side side
VALUE
Table Skip Data Command RESULTS DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR DESCRIPTION READ? SET? RESULTS Normal Data Deleted Data Normal termination. Address incremented. Next sector searched for. Normal termination. Normal termination. Sector read ("skipped").
Normal Data Deleted Data
Read Deleted Data This command same Read Data command, only operates sectors that contain Deleted Data Address Mark beginning Data Field. Table describes effect Read Deleted Data command execution results. Except where noted Table value sector address automatically incremented (see Table 30). Table Skip Read Deleted Data Command DATA ADDRESS RESULTS MARK TYPE VALUE ENCOUNTERED SECTOR DESCRIPTION READ? SET? RESULTS Normal Data Address incremented. Next sector searched for. Normal termination. Normal termination. Sector read
Deleted Data Normal Data
VALUE
DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ?
RESULTS
SET?
DESCRIPTION RESULTS ("skipped"). Normal termination.
Deleted Data
Read Track This command similar Read Data command except that entire data field read continuously from each sectors track. Immediately after encountering pulse nINDEX pin, starts read data fields track continuous blocks data without regard logical sector numbers. finds error DATA check bytes, continues read data from track sets appropriate error bits command. compares information read from each sector with specified value command sets flag Status Register there comparison. Multi-track skip operations allowed with this command. bits (bits first command byte respectively) should always "0". This command terminates when specified number sectors been read. does find Address Mark diskette after second occurrence pulse pin, then sets code Status Register "01" (abnormal termination), sets Status Register "1", terminates command.
HEAD
Table Result Phase Table INFORMATION RESULT PHASE FINAL SECTOR TRANSFERRED HOST Less than
Equal Less than Equal Less than Equal Less than Equal
Change, same value beginning command execution. LSB: Least Significant Bit, complemented. Write Data After Write Data command been issued, loads head unloaded state), waits specified head load time unloaded (defined Specify command), begins reading fields. When sector address read from diskette matches sector address specified command, reads data from host FIFO writes sector's data field. After writing data into current sector, computes value writes into field sector transfer. Sector Number stored incremented one, continues writing next data field. continues this "Multi-Sector Write Operation". Upon receipt terminal count signal FIFO over/under occurs while data field being written, then remainder data field filled with zeros. reads field each sector checks bytes. detects error fields, sets code Status Register "01" (abnormal termination), sets Status Register "1", terminates Write Data command.
Write Data command operates much same manner Read Data command. following items same. Please refer Read Data Command details: Transfer Capacity (End Cylinder) Data) Head Load, Unload Time Interval information when host terminates command Definition when when does
Write Deleted Data This command almost same Write Data command except that Deleted Data Address Mark written beginning Data Field instead normal Data Address Mark. This command typically used mark sector containing error floppy disk. Verify Verify command used verify data stored disk. This command acts exactly like Read Data command except that data transferred host. Data read from disk computed checked against previously-stored value. Because data transferred host, (pin cannot used terminate this command. setting "1", implicit will issued FDC. This implicit will occur when value decremented value will verify sectors). This command also terminated setting value equal final sector checked. "0", DTL/SC should programmed 0FFH. Refer Table Table information concerning values versus value. Definitions: Sectors Side Number formatted sectors each side disk. Sectors Remaining Number formatted sectors left which read, including side disk "1".
Table Verify Command Result Phase Table SC/EOT VALUE TERMINATION RESULT Sectors Side Sectors Side Sectors Remaining Sectors Side Sectors Remaining Sectors Side Sectors Side Sectors Side Sectors Remaining Sectors Side Sectors Remaining Sectors Side Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid
NOTE: value greater than number remaining formatted sectors Side verifying will continue Side disk. Format Track Format command allows entire track formatted. After pulse from detected, starts writing data disk including gaps, address marks, fields, data fields System 3740 format (MFM respectively). particular values that will written data field controlled values programmed into GPL, which specified host during command phase. data field sector filled with data byte specified field each sector supplied host; that four data bytes sector needed (cylinder, head, sector number sector size respectively). After formatting each sector, host must send values next sector track. value (sector number) only value that must changed host after each sector formatted. This allows disk formatted with nonsequential sector addresses (interleaving). This incrementing formatting continues whole track until encounters pulse again terminates command. Table contains typical values fields which dependent upon size sector number sectors each track. Actual values vary drive electronics.
Table Diskette Format Fields SYSTEM (DOUBLE DENSITY) FORMAT
GAP4a SYNC GAP1 SYNC IDAM GAP2 SYNC DATA DATA GAP3
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a SYNC GAP1 SYNC IDAM GAP2 SYNC DATA DATA GAP3
PERPENDICULAR FORMAT
GAP4a SYNC GAP1 SYNC IDAM GAP2 SYNC DATA DATA GAP3
Table Typical Values Formatting FORMA SECTOR GPL1 SIZE 1024 2048 4096 512* 1024 2048 4096 512** 1024
GPL2
5.25" Drives
3.5" Drives
GPL1 suggested values Read Write commands avoid splice point between data field field contiguous sections. GPL2 suggested value Format Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with drives. NOTE: values except sector size hex.
CONTROL COMMANDS
Control commands differ from other commands that data transfer takes place. Three commands generate interrupt when complete: Read Recalibrate, Seek. other control commands generate interrupt. Read Read command used find present position recording heads. stores values from first field able read into registers. does find address mark diskette after second occurrence pulse nINDEX pin, then sets code Status Register "01" (abnormal termination), sets Status Register "1", terminates command. following commands will generate interrupt upon completion. They return result bytes. highly recommended that control commands followed Sense Interrupt Status command. Otherwise, valuable interrupt status information will lost. Recalibrate This command causes read/write head within retract track position. clears contents counter checks status nTR0 from FDD. long nTR0 low, remains step pulses issued. When nTR0 goes high, Status Register command terminated. nTR0 still after step pulses have been issued, sets bits Status Register terminates command. Disks capable handling more than tracks side require more than Recalibrate command return head back physical Track Recalibrate command does have result phase. Sense Interrupt Status command must issued after Recalibrate command effectively terminate provide verification head position (PCN). During command phase recalibrate operation, BUSY state, during execution phase NON-BUSY state. this time, another Recalibrate command issued, this manner parallel Recalibrate operations done four drives once. Upon power software must issue Recalibrate command properly initialize drives controller.
Seek read/write head within drive moved from track track under control Seek command. compares PCN, which current head position, with performs following operation there difference: NCN: Direction signal drive (step issues step pulses. NCN: Direction signal drive (step out) issues step pulses. rate which step pulses issued controlled (Stepping Rate Time) Specify command. After each step pulse issued, compared against PCN, when Status Register command terminated. During command phase seek recalibrate operation, BUSY state, during execution phase NON-BUSY state. this time, another Seek Recalibrate command issued, this manner, parallel seek operations done four drives once. Note that implied seek enabled, read write commands should preceded Seek command Step proper track Sense Interrupt Status command Terminate Seek command Read Verify head proper track Issue Read/Write command.
Seek command does have result phase. Therefore, highly recommended that Sense Interrupt Status command issued after Seek command terminate provide verification head position (PCN). (Head Address) will always return "0". When exiting POWERDOWN mode, clears value status information zero. Prior issuing POWERDOWN command, highly recommended that user service pending interrupts through Sense Interrupt Status command. Sense Interrupt Status interrupt signal FDC's generated following reasons: Upon entering Result Phase Read Data command Read Track command Read command Read Deleted Data command Write Data command Format Track command Write Deleted Data command Verify command
Seek, Relative Seek, Recalibrate command requires data transfer during execution phase non-DMA mode Sense Interrupt Status command resets interrupt signal and, code Status Register identifies cause interrupt.
Table Interrupt Identification INTERRUPT Polling Normal termination Seek Recalibrate command Abnormal termination Seek Recalibrate command
Seek, Relative Seek, Recalibrate commands have result phase. Sense Interrupt Status command must issued immediately after these commands terminate them provide verification head position (PCN). (Head Address) will always return "0". Sense Interrupt Status issued, drive will continue BUSY affect operation next command. Sense Drive Status Sense Drive Status obtains drive status information. execution phase goes directly result phase from command phase. Status Register contains drive status information.
Specify Specify command sets initial values each three internal times. (Head Unload Time) defines time from execution phase read/write commands head unload state. (Step Rate Time) defines time interval between adjacent step pulses. Note that spacing between first second step pulses shorter than remaining step pulses. (Head Load Time) defines time between when Head Load signal goes high read/write operation starts. values change with data rate speed selection documented Table Drive Control Delays(ms) values same Table Drive Control Delays(ms) 500K 300K 26.7 250K 3.75 0.25 63.5 500K 300K 250K
500K 300K 26.7 3.33 1.67 250K
choice non-DMA operations made bit. When this "1", non-DMA mode selected, when "0", mode selected. mode, data transfers signalled FDC's pin. Non-DMA mode uses FDC's signal data transfers.
Configure Configure command issued select special features FDC. Configure command need issued default values meet system requirements. Configure Default Values: Implied Seeks EFIFO FIFO Disabled POLL Polling Enabled FIFOTHR FIFO Threshold Byte PRETRK Pre-Compensation Track Enable Implied Seek. When "1", will perform Seek operation before executing read write command. Defaults implied seek. EFIFO disables FIFO (default). This means data transfers asked byte-by-byte basis. Defaults "1", FIFO disabled. threshold defaults "1". POLL Disable polling drives. Defaults "0", polling enabled. When enabled, single interrupt generated after reset. polling performed while drive head loaded head unload delay expired. FIFOTHR FIFO threshold execution phase read write commands. This programmable from bytes. Defaults byte. "00" selects byte; "0F" selects bytes. PRETRK Pre-Compensation Start Track Number. Programmable from track 255. Defaults track "00" selects track "FF" selects track 255. Version Version command checks controller enhanced type older type (765A). value returned result byte.
Relative Seek command coded same Seek, except first byte bit. ACTION Step Head Step Head Head Step Direction Control Relative Cylinder Number that determines many tracks step head from current track number.
Relative Seek command differs from Seek command that steps head absolute number tracks specified command instead making comparison against internal register. Seek command good drives that support maximum tracks. Relative Seeks cannot overlapped with other Relative Seeks. Only Relative Seek active time. Relative Seeks overlapped with Seeks Recalibrates. Status Register (EC) will Relative Seek attempts step outward beyond Track example, assume that floppy drive useable tracks. host needs read track head track (0-255). Seek command issued, head will stop track 255. Relative Seek command issued, will move head specified number tracks, regardless internal cylinder position register (but will increment register). head track (d), maximum track that could position head using Relative Seek will (D), initial track (D). maximum count that head moved with single Relative Seek command (D). internal register, PCN, will overflow cylinder number crosses track will contain (D). resulting value thus (RCN PCN) 256. Functionally, starts counting from again track number goes above (D). user's responsibility compensate functions (precompensation track number) when accessing tracks greater than 255. does keep track that working "extended track area" (greater than 255). command issued will current value except Recalibrate command, which only looks TRACK0 signal. Recalibrate will return error head farther than limitation issuing maximum step pulses. user simply needs issue second Recalibrate command. Seek command implied seeks will function correctly within track (299255) area "extended track area". user's responsibility issue track position that will exceed maximum track that present extended area. return standard floppy range (0-255) tracks, Relative Seek should issued cross track boundary. Relative Seek used instead normal Seek, host required calculate difference between current head location (target) head location. This require host issue Read command ensure that head physically track that software assumes Different commands will return different cylinder results which difficult keep track with software without Read command.
Perpendicular Mode Perpendicular Mode command should issued prior executing Read/Write/Format commands that access disk drive with perpendicular recording capability. With this command, length Gap2 field enable timing altered accommodate unique requirements these drives. Table describes effects WGATE bits Perpendicular Mode command. Upon reset, will default conventional mode (WGATE Selection Kbps Mbps perpendicular modes independent actual data rate selected Data Rate Select Register. user must ensure that these data rates remain consistent. Gap2 timing requirements perpendicular recording type drives dictated design read/write head. design this head, pre-erase head precedes normal read/write head distance micrometers. This works about bytes Mbps recording density. Whenever write head enabled Write Gate signal, pre-erase head also activated same time. Thus, when write head initially turned flux transitions recorded media first bytes will preconditioned with pre-erase head since been activated. accommodate this head activation deactivation time, Gap2 field expanded length bytes. format field illustrates change Gap2 field size perpendicular format. read back FDC, controller must begin synchronization beginning sync field. conventional mode, internal enabled (VCOEN) approximately bytes from start Gap2 field. But, when controller operates Mbps perpendicular mode (WGATE VCOEN goes active after bytes accommodate increased Gap2 field size. both cases, approximate two-byte cushion maintained from beginning sync field purposes avoiding write splices presence motor speed variation. Write Data case, activates Write Gate beginning sync field under conventional mode. controller then writes sync field, data address mark, data field, CRC. With pre-erase head perpendicular drive, write head must activated Gap2 field insure proper write sync field. Mbps perpendicular mode (WGATE bytes will written Gap2 space. Since density proportional data rate, bytes will written Gap2 field Kbps perpendicular mode (WGATE =0). should noted that none alterations Gap2 size, timing, Write Gate timing affect normal program flow. information provided here just background purposes needed normal operation. Once Perpendicular Mode command invoked, software behavior from user standpoint unchanged. perpendicular mode command enhanced allow specific drives designated Perpendicular recording drives. This enhancement allows data transfers between Conventional
Perpendicular drives without having issue Perpendicular mode commands between accesses different drive types, having change write pre-compensation values. When both WGATE bits PERPENDICULAR MODE COMMAND both programmed (Conventional mode), then programmed independently that drive automatically Perpendicular mode. this mode following conditions also apply: GAP2 written perpendicular drive during write operation will depend upon programmed data rate. write pre-compensation given perpendicular mode drive will 0ns. D0-D3 programmed conventional mode drives data written will currently programmed write pre-compensation. Note: Bits D0-D3 only overwritten when programmed "1". either WGATE then D0-D3 ignored. Software hardware resets have following effect PERPENDICULAR MODE COMMAND: "Software" resets (via registers) will only clear WGATE bits "0". D0-D3 unaffected retain their previous value. "Hardware" resets will clear bits GAP, WGATE D0-D3) "0", conventional mode. Table Effects WGATE Bits PORTION LENGTH WRITTEN GAP2 WRITE DATA WGATE MODE FORMAT OPERATION FIELD Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular Mbps) Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes
LOCK order protect systems with long latencies against older application software that disable FIFO LOCK Command been added. This command should only used routines, application software should refrain from using application calls FIFO disabled then CONFIGURE command should used. LOCK command defines whether EFIFO, FIFOTHR, PRETRK parameters CONFIGURE command RESET registers. When LOCK logic subsequent "software RESETS registers will change previously parameters their default values. "hardware" RESET from RESET will LOCK logic return EFIFO, FIFOTHR, PRETRK their default values. status byte returned immediately after issuing LOCK command. This byte reflects value LOCK command byte. ENHANCED DUMPREG DUMPREG command designed support system run-time diagnostics application software development debug. accommodate LOCK command enhanced PERPENDICULAR MODE command eighth byte DUMPREG command been modified contain additional data from these commands.
COMPATIBILITY
FDC37C957FR designed with software compatibility mind. fully backwardscompatible solution with older generation 765A/B disk controllers. also implements onboard registers compatibility with PS/2, well PC/AT PC/XT, floppy disk controller subsystems. After hardware reset FDC, registers, functions enhancements default PC/AT, PS/2 PS/2 Model compatible operating mode, depending IDENT bits configured system BIOS. Parallel Port Floppy Disk Controller Refer Parallel Port Section details. Swapable Capability output pins will tri-state whenever Logical Device powered-down activated. addition setting bit-7 Mode Configuration register (LD0_CRF0) will tri-state output pins. Bit-7 only affects standard interface, effect Parallel Port Floppy Interface.
following table illustrates state Parallel Port pins combinations Output Control bit; Activate bit; power-down state. Mode Register, Activate Power pins Parallel Port Bit[7] Down pins Hi-Z Hi-Z Hi-Z Hi-Z Active Active Hi-Z Active When disabled, powered down inactive output pins will tri-state allowing `HotSwapping' Floppy Disk Drive. following table lists five control/configuration mechanisms that power down deactivate logical device. Mechanism
Tri-State Tri-State
Output pins State
Tri-State Tri-State Note: down overrides auto down. Tri-State Note: outputs tristate only required auto power down conditions met, otherwise outputs active. Auto Power Management Section Data Sheet.
Logical Activate deactivated activated Refer description Logical Device Configuration register 0x30 Configuration section Orion Specification. Logical Base Address 0x100 Base 0x0FF8: Base Address Valid. 0xFFF Base 0x100: Base Address Invalid.
INVALID BASE ADDRES
VALID BASE ADDRES
VALID BASE ADDRESS
VALID BASE ADDRESS
Mechanism
Refer description Base Address registers Configuration section Orion Specification. 0x22 bit-0 (FDC Power) Power Power Refer description Global Config Register 0x22 Configuration section Orion Specification. DSR, bit-6 (pwr down) Normal Manual down Refer description Floppy Disk Controller section Super Ultra data sheet. 0x23 bit-0 (FDC auto power management) Mngnt Mngnt Refer description Global Config Register 0x23 Configuration section Orion Specification.
Output pins State
Note: Output pins nWDATA, DRVDEN0, nHDSELm nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.
SERIAL PORT (UART)
FDC37C957FR incorporates full function UARTs. They compatible with NS16450, 16450 registers NS16550A. UARTS perform serial-to-parallel conversion received characters parallel-to-serial conversion transmit characters. data rates independently programmable from 460.8K baud down baud. character options programmable start; stop bits; even, odd, sticky parity; prioritized interrupts. UARTs each contain programmable baud rate generator that capable dividing input clock crystal number from 65535. UARTs also capable supporting MIDI data rate. Refer Configuration Registers information disabling, power down changing base address UARTs. interrupt from UART enabled programming OUT2 that UART logic "1". OUT2 being logic disables that UART's interrupt. second UART also supports IrDA, HP-SIR ASK-IR infrared modes operation.
REGISTER DESCRIPTION
Addressing accessible registers Serial Port shown below. base addresses serial ports defined configuration registers (see Configuration section). Serial Port registers located sequentially increasing addresses above these base addresses. FDC37C957FR contains serial ports, each which contain register described below. Table Addressing Serial Port
DLAB* REGISTER NAME Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor (read/write) Divisor (read/write
NOTE: DLAB Line Control Register following section describes operation registers.
RECEIVE BUFFER REGISTER (RB) Address Offset DLAB READ ONLY This register holds received incoming data byte. least significant bit, which transmitted received first. Received data double buffered; this uses additional shift register receive serial data stream convert parallel word which transferred Receive Buffer register. shift register accessible. TRANSMIT BUFFER REGISTER (TB) Address Offset DLAB WRITE ONLY This register contains data byte transmitted. transmit buffer double buffered, utilizing additional shift register (not accessible) convert data word serial format. This shift register loaded from Transmit Buffer when transmission previous byte complete. INTERRUPT ENABLE REGISTER (IER) Address Offset DLAB READ/WRITE lower four bits this register control enables five interrupt sources Serial Port interrupt. possible totally disable interrupt system resetting bits through this register. Similarly, setting appropriate bits this register high, selected interrupts enabled. Disabling interrupt system inhibits Interrupt Identification Register disables Serial Port interrupt FDC37C957FR. other system functions operate their normal manner, including Line Status MODEM Status Registers. contents Interrupt Enable Register described below. This enables Received Data Available Interrupt (and timeout interrupts FIFO mode) when logic "1". This enables Transmitter Holding Register Empty Interrupt when logic "1". This enables Received Line Status Interrupt when logic "1". error sources causing interrupt Overrun, Parity, Framing Break. Line Status Register must read determine source. This enables MODEM Status Interrupt when logic "1". This caused when Modem Status Register bits changes state. Bits through These bits always logic "0".
FIFO CONTROL REGISTER (FCR) Address Offset DLAB WRITE This write only register same location IIR. This register used enable clear FIFOs, RCVR FIFO trigger level. Note: supported. Setting this logic enables both XMIT RCVR FIFOs. Clearing this logic disables both XMIT RCVR FIFOs clears bytes from both FIFOs. When changing from FIFO Mode non-FIFO (16450) mode, data automatically cleared from FIFOs. This must when other bits this register written they will properly programmed. Setting this logic clears bytes RCVR FIFO resets counter logic shift register cleared. This self-clearing. Setting this logic clears bytes XMIT FIFO resets counter logic shift register cleared. This self-clearing. Writting this effect operation UART. RXRDY TXRDY pins available this chip. Reserved These bits used trigger level RCVR FIFO interrupt. RCVR FIFO TRIGGER LEVEL (BYTES)
INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset DLAB READ accessing this register, host determine highest priority interrupt source. Four levels priority interrupt exist. They descending order priority: Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
Information indicating that prioritized interrupt pending source that interrupt stored Interrupt Identification Register (refer Interrupt Control Table). When accesses IIR, Serial Port freezes interrupts indicates highest priority pending interrupt CPU. During this access, even Serial Port records interrupts, current indication does change until access completed. contents described below. This used either hardwired prioritized polled environment indicate whether interrupt pending. When logic "0", interrupt pending contents used pointer appropriate internal service routine. When logic "1", interrupt pending. Bits These bits used identify highest priority interrupt pending indicated Interrupt Control Table.
non-FIFO mode, this logic "0". FIFO mode this along with when timeout interrupt pending. Bits These bits always logic "0". Bits These bits when FIFO CONTROL Register equals Table Interrupt Control Table FIFO MODE ONLY INTERRUPT IDENTIFICATION REGISTER
INTERRUPT RESET FUNCTIONS PRIORITY LEVEL Highest INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None INTERRUPT RESET CONTROL
Overrun Error, Reading Line Parity Error, Status Register Framing Error Break Interrupt Receiver Data Available Read Receiver Buffer FIFO drops below trigger level. Reading Receiver Buffer Register
Second
Received Data Available
Second
Character Timeout Indication
Characters Have Been Removed From Input RCVR FIFO during last Char times there least char during this time
FIFO MODE ONLY
INTERRUPT IDENTIFICATION REGISTER
INTERRUPT RESET FUNCTIONS PRIORITY LEVEL Third INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL
Reading Transmitter Transmitter Holding Register Holding Register Register Source Empty Empty Interrupt) Writing Transmitter Holding Register MODEM Status Clear Send Reading Data Ready MODEM Status Ring Indicator Register Data Carrier Detect
Fourth
LINE CONTROL REGISTER (LCR) Address Offset DLAB READ/WRITE This register contains format information serial line. definitions are: Bits These bits specify number bits each transmitted received serial character. encoding bits follows: WORD LENGTH Bits Bits Bits Bits
Start, Stop Parity bits included word length. This specifies number stop bits each transmitted received serial character. table following page summarizes information.
WORD LENGTH bits bits bits bits
NUMBER STOP BITS
Note: receiver will ignore stop bits beyond first, regardless number used transmitting. Parity Enable bit. When logic "1", parity generated (transmit data) checked (receive data) between last data word first stop serial data. (The parity used generate even number when data word bits parity summed). Even Parity Select bit. When logic logic "0", number logic "1"'s transmitted checked data word bits parity bit. When logic logic even number bits transmitted checked. Stick Parity bit. When logic logic "1", parity transmitted then detected receiver opposite state indicated Break Control bit. When logic "1", transmit data output (TXD) forced Spacing logic state remains there (until reset level regardless other transmitter activity. This feature enables Serial Port alert terminal communications system. Divisor Latch Access (DLAB). must high (logic "1") access Divisor Latches Baud Rate Generator during read write operations. must (logic "0") access Receiver Buffer Register, Transmitter Holding Register, Interrupt Enable Register.
MODEM CONTROL REGISTER (MCR) Address Offset DLAB READ/WRITE This register controls interface with MODEM data device emulating MODEM). contents MODEM control register described below. This controls Data Terminal Ready (nDTR) output. When logic "1", nDTR output forced logic "0". When logic "0", nDTR output forced logic "1". This controls Request Send (nRTS) output. affects nRTS output manner identical that described above This controls Output (OUT1) bit. This does have output only read written CPU. Output (OUT2). This used enable UART interrupt. When OUT2 logic "0", serial port interrupt output forced high impedance state disabled. When OUT2 logic "1", serial port interrupt outputs enabled. This provides loopback feature diagnostic testing Serial Port. When logic "1", following occur: Marking State(logic "1"). receiver Serial Input (RXD) disconnected. output Transmitter Shift Register "looped back" into Receiver Shift Register input. MODEM Control inputs (nCTS, nDSR, nDCD) disconnected. four MODEM Control outputs (nDTR, nRTS, OUT1 OUT2) internally connected four MODEM Control inputs (nDSR, nCTS, DCD). Modem Control output pins forced inactive high. Data that transmitted immediately received. This feature allows processor verify transmit receive data paths Serial Port. diagnostic mode, receiver transmitter interrupts fully operational. MODEM Control Interrupts also operational interrupts' sources lower four bits MODEM Control Register instead MODEM Control inputs. interrupts still controlled Interrupt Enable Register. Bits through These bits permanently logic zero.
LINE STATUS REGISTER (LSR) Address Offset DLAB READ/WRITE Data Ready (DR). logic whenever complete incoming character been received transferred into Receiver Buffer Register FIFO. reset logic reading data Receive Buffer Register FIFO. Overrun Error (OE). indicates that data Receiver Buffer Register read before next character transferred into register, thereby destroying previous character. FIFO mode, overrunn error will occur only when FIFO full next character been completely received shift register, character shift register overwritten transferred FIFO. indicator logic immediately upon detection overrun condition, reset whenever Line Status Register read. Parity Error (PE). indicates that received data character does have correct even parity, selected even parity select bit. logic upon detection parity error reset logic whenever Line Status Register read. FIFO mode this error associated with particular character FIFO applies This error indicated when associated character FIFO. Framing Error (FE). indicates that received character have valid stop bit. logic whenever stop following last data parity detected zero (Spacing level). reset logic whenever Line Status Register read. FIFO mode this error associated with particular character FIFO applies This error indicated when associated character FIFO. Serial Port will resynchronize after framing error. this, assumes that framing error next start bit, samples this 'start' twice then takes 'data'. Break Interrupt (BI). logic whenever received data input held Spacing state (logic "0") longer than full word transmission time (that total time start data bits parity bits stop bits). reset after reads contents Line Status Register. FIFO mode this error associated with particular character FIFO applies This error indicated when associated character FIFO. When break occurs only zero character loaded into FIFO. Restarting after break received, requires serial data (RXD) logic least time. Note: Bits through error conditions that produce Receiver Line Status Interrupt whenever corresponding conditions detected interrupt enabled.
Transmitter Holding Register Empty (THRE). indicates that Serial Port ready accept character transmission. addition, this causes Serial Port issue interrupt when Transmitter Holding Register interrupt enable high. THRE logic when character transferred from Transmitter Holding Register into Transmitter Shift Register. reset logic whenever loads Transmitter Holding Register. FIFO mode this when XMIT FIFO empty, cleared when least byte written XMIT FIFO. read only bit. Transmitter Empty (TEMT). logic whenever Transmitter Holding Register (THR) Transmitter Shift Register (TSR) both empty. reset logic whenever either contains data character. read only bit. FIFO mode this whenever both empty, This permanently logic mode. FIFO mode, this logic when there least parity error, framing error break indication FIFO. This cleared when read there subsequent errors FIFO. MODEM STATUS REGISTER (MSR) Address Offset DLAB READ/WRITE This register provides current state control lines from MODEM peripheral device). addition this current state information, four bits MODEM Status Register (MSR) provide change information. These bits logic whenever control input from MODEM changes state. They reset logic whenever MODEM Status Register read. Delta Clear Send (DCTS). indicates that nCTS input chip changed state since last time read. Delta Data Ready (DDSR). indicates that nDSR input changed state since last time read. Trailing Edge Ring Indicator (TERI). indicates that input changed from logic logic "1". Delta Data Carrier Detect (DDCD). indicates that nDCD input chip changed state. NOTE: Whenever logic "1", MODEM Status Interrupt generated. This complement Clear Send (nCTS) input. logic "1", this equivalent nRTS MCR.
This complement Data Ready (nDSR) input. logic "1", this equivalent MCR. This complement Ring Indicator (nRI) input. logic "1", this equivalent OUT1 MCR. This complement Data Carrier Detect (nDCD) input. logic "1", this equivalent OUT2 MCR. SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB READ/WRITE This read/write register effect operation Serial Port. intended scratchpad register used programmer hold data temporarily.
PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL) Serial Port contains programmable Baud Rate Generator that capable taking clock input MHz) dividing divisor from 65535. This output frequency Baud Rate Generator Baud rate. latches store divisor binary format. These Divisor Latches must loaded during initialization order insure desired operation Baud Rate Generator. Upon loading either Divisor Latches, Baud counter immediately loaded. This prevents long counts initial load. loaded into registers output divides clock number loaded output inverse input oscillator. loaded output divide signal with duty cycle. greater loaded output bits high remainder count. input clock crystal divided giving 1.8462 clock. Table shows baud rates possible with 1.8462 crystal.
Table UART Baud Rates DESIRED DIVISOR USED PERCENT ERROR DIFFERENCE CRxx: BAUD RATE GENERATE CLOCK BETWEEN DESIRED ACTUAL* 2304 0.001 1536 1047 134.5 0.004 1200 1800 2000 0.005 2400 3600 4800 7200 9600 19200 38400 0.030 57600 0.16 115200 0.16 230400 32770 0.16 460800 32769 0.16 *Note: percentage error baud rates, except where indicated otherwise, 0.2%. Baud Rates Using 1.8462 Clock <=38.4; Using 1.843 Clock 115.2k; Using 3.6864 Clock 230.4k; Using 7.3728 Clock 460.8k
FIFO INTERRUPT MODE OPERATION
When RCVR FIFO receiver interrupts enabled (FCR "1", "1"), RCVR interrupts occur follows: receive data available interrupt will issued when FIFO reached programmed trigger level; cleared soon FIFO drops below programmed trigger level. receive data available indication also occurs when FIFO trigger level reached. cleared when FIFO drops below trigger level. receiver line status interrupt (IIR=06H), higher priority than received data available (IIR=04H) interrupt. data ready (LSR 0)is soon character transferred from shift register RCVR FIFO. reset when FIFO empty. When RCVR FIFO receiver interrupts enabled, RCVR FIFO timeout interrupts occur follows: FIFO timeout interrupt occurs following conditions exist: least character FIFO most recent serial character received longer than continuous character times ago. stop bits programmed, second included this time delay.) most recent read FIFO longer than continuous character times ago. This will cause maximum character received interrupt issued delay msec BAUD with character. Character times calculated using RCLK input clock signal (this makes delay proportional baudrate). When timeout interrupt occurred cleared timer reset when reads character from RCVR FIFO. When timeout interrupt occurred timeout timer reset after character received after reads RCVR FIFO. When XMIT FIFO transmitter interrupts enabled (FCR "1", "1"), XMIT interrupts occur follows: transmitter holding register interrupt (02H) occurs when XMIT FIFO empty; cleared soon transmitter holding register written characters written XMIT FIFO while servicing this interrupt) read.
transmitter FIFO empty indications will delayed character time minus last stop time whenever following occurs: THRE=1 there have been least bytes same time transmitter FIFO since last THRE=1. transmitter interrupt after changing FCR0 will immediate, enabled. Character timeout RCVR FIFO trigger level interrupts have same priority current received data available interrupt; XMIT FIFO empty same priority current transmitter holding register empty interrupt.
FIFO POLLED MODE OPERATION
With resetting bits zero puts UART FIFO Polled Mode operation. Since RCVR XMITTER controlled separately, either both polled mode operation. this mode, user's program will check RCVR XMITTER status LSR. definitions FIFO Polled Mode follows: long there byte RCVR FIFO. Bits specify which error(s) have occurred. Character error status handled same when interrupt mode, affected since 2=0. indicates when XMIT FIFO empty. indicates that both XMIT FIFO shift register empty. indicates whether there errors RCVR FIFO. There trigger level reached timeout condition indicated FIFO Polled Mode, however, RCVR XMIT FIFOs still fully capable holding characters. Effect Reset Register File Reset Function Table (Table details effect Vcc2 nRESET_OUT each registers Serial Port.
REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO
Table Reset Function Table RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read RESET/ReadIIR/Write RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0
RESET STATE
bits high; Bits bits bits bits bits except high Bits low; Bits input High High High High High Bits Bits
INTRPT (RCVR Data Ready) RESET/Read
Table Register Summary Individual UART Channel
REGISTER ADDRESS* ADDR DLAB ADDR DLAB ADDR DLAB REGISTER NAME Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register REGISTER SYMBOL Data (Note Data Enable Received Data Available Interrupt (ERDAI) Interrupt Pending FIFO Enable Word Length Select (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear Send (DCTS) Data Data Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt RCVR FIFO Reset Word Length Select (WLS1) Request Send (RTS)
ADDR
Interrupt Ident. Register (Read Only)
ADDR ADDR
FIFO Control Register (Write Only) Line Control Register
ADDR
MODEM Control Register
ADDR ADDR
Line Status Register MODEM Status Register
Overrun Error (OE) Delta Data Ready (DDSR)
ADDR
Scratch Register (Note
ADDR Divisor Latch (LS) DLAB ADDR Divisor Latch (MS) DLAB *DLAB Line Control Register (ADDR Note least significant bit. first serially transmitted received. Note When operating mode, this will time that transmitter shift register empty.
Table Register Summary Individual UART Channel (continued) Data Data Data Data Data Data Data Data Data Data Data Data Enable Enable MODEM Receiver Line Status Status Interrupt Interrupt (EMSI) (ELSI) FIFOs Interrupt Interrupt FIFOs Enabled (Note Enabled (Note (Note Reserved RCVR RCVR XMIT FIFO Mode Reserved Trigger Trigger Reset Select (Note Divisor Even Parity Stick Parity Break Parity Number Latch Select Enable Stop Bits Access (EPS) (PEN) (STB) (DLAB) OUT1 OUT2 Loop (Note (Note Parity Error Framing Break Transmitter Transmitter Error (PE) Error (FE) Interrupt Holding Empty RCVR FIFO (BI) Register (TEMT) (Note (THRE) (Note Trailing Delta Data Clear Data Ring Data Carrier Edge Ring Carrier Send (CTS) Ready Indicator Detect Indicator Detect (DSR) (RI) (DCD) (TERI) (DDCD) Note Note Note Note
This longer associated with When operating mode, this register available. These bits always zero non-FIFO mode. Writing this effect. modes supported this chip.
UART Register Summary Notes: *DLAB Line Control Register (ADDR Note least significant bit. first serially transmitted received. Note When operating mode, this will time that transmitter shift register empty. Note This longer associated with Note When operating mode, this register available. Note These bits always zero non-FIFO mode. Note Writing this effect. modes supported this chip.
NOTES SERIAL PORT FIFO MODE OPERATION
GENERAL RCVR FIFO will hold bytes regardless which trigger level selected. FIFO OPERATION portion UART transmits data through soon loads byte into FIFO. UART will prevent loads FIFO currently holds characters. Loading FIFO will again enabled soon next character transferred shift register. These capabilities account largely autonomous operation UART starts above operations typically with interrupt. chip issues interrupt whenever FIFO empty interrupt enabled, except following instance. Assume that FIFO empty starts load When first byte enters FIFO FIFO empty interrupt will transition from active inactive. Depending execution speed service routine software, UART able transfer this byte from FIFO shift register before loads another byte. this happens, FIFO will empty again typically UART's interrupt line would transition active state. This could cause system with interrupt control unit record FIFO empty condition, even though currently servicing that interrupt. Therefore, after first byte been loaded into FIFO UART will wait serial character transmission time before issuing FIFO empty interrupt. This character interrupt delay will remain active until least bytes have been loaded into FIFO, concurrently. When FIFO empties after this condition, interrupt will activated without character delay. support functions operation quite different from those described transmitter. FIFO receives data until number bytes FIFO equals selected interrupt trigger level. that time interrupts enabled, UART will issue interrupt CPU. FIFO will continue store bytes until holds them. will accept more data when full. more data entering shift register will Overrun Error flag. Normally, FIFO depth programmable trigger levels will give ample time empty FIFO before overrun occurs.
side-effect having FIFO that selected interrupt trigger level above data level FIFO. This could occur when data block contains fewer bytes than trigger level. interrupt would issued data would remain UART. prevent software from having check this situation chip incorporates timeout interrupt. timeout interrupt activated when there least byte FIFO, neither shift register accessed FIFO within character times last byte. timeout interrupt cleared reset when reads FIFO another character enters These FIFO related features allow optimization CPU/UART transactions especially useful given higer baud rate capability (256 kbaud).
Infared Communications Controller (IrCC)
Infared Communications Controller fully compliant IrDA Specification Version which includes data rates 4Mbps meaning that IrDA-SIRA, IrDA-SIRB, IrDA-HDLC IrDA-FIR modes supported. addition IrCC provides support ASK-IR, Consumer remote) RAW-IR (Host controller direct access stream from/to transceiver module). important note that IrCC block superset UART2. Thus IrCC comprises UART2 Asynchronous Communications Engine (ACE) separate Synchronous Communications Engine (SCE) provide full modes well standard UART mode. IrCC block details fully described SMC's specification titled "Infared Communications Controller" 1.30 dated November 1995. information this section specification will provide details integration logic block into FDC37C957FR device. infrared interface provides two-way wireless communications port using infrared transmission medium. transmission standard UART2 pins optional IRTX2 IRRX2 pins. These selected through configuration registers. IrDA-SIR allows serial communication baud rates 115K Baud. Each word sent serially beginning with zero value start bit. zero signaled sending single pulse beginning serial time. signaled sending pulse during time. Please refer timing parameters these pulses IrDA waveform. Amplitude Shift Keyed allows serial communication baud rates 19.2K Baud. Each word sent serially beginning with zero value start bit. zero signaled sending 500KHz waveform duration serial time. signaled sending transmission time. Please refer timing parameters ASK-IR waveform. Half Duplex option chosen, there time-out when direction transmission changed. This time-out starts last transfered during transmission blocks receiver input until time-out expires. transmit buffer loaded with more data before time-out expires, timer restarted after byte transmitted. data loaded into transmit buffer while character being received, transmission will start until time-out expires after last receive been received. start another character received during this time-out, timer restarted after character received. time-out four character times. character time defined times regardless actual word length being used.
Integration IrCC Logic into Orion Device IrCC Block IrDA G.P. Data FAST_BIT nRTS2 nCTS2 nDTR2 nDSR2 nDCD2 nRI2
FAST HP_MODE MISC[14:13] MISC[16:15] GPIO9_IN GPIO9_OUT GPIO8_OUT MISC7 MISC2 "FRx" Data bit-0 Data bit-1 FRX_SEL GPIO10_OUT "IR_MODE" GPIO6_OUT
GPIO9
GPIO8
IRTX IRRX GPIO6
GPIO10
GPIO11
GPIO[11-15]
GPIO12 GPIO13 GPIO14 GPIO15
MISC[12]
HP_MODE (MISC[14:13] [1:0]]) (MISC[16:15] [1:0]) FRX_SEL (MISC[14:13] [1:0]])
IRRX IRTX Enable
When MISC2=0 IRRX IRTX pins enabled when UART2 (LD5) Activated enabled IrCC Output Port, otherwise IRTX tri-stated. When MISC2=1, IRRX IRTX pins always enabled they banged through DATA Register, bits respectively.
Registers Logical Device
Configuration Registers Overview order support Infared Communications Controller four configuration registers added Logical Device (commonly known UART2). These registers consist Fast Base Address registers 0x62 0x63; IrCC channel select register 0x74; Half Duplex Timeout register 0xF2. Refer Configuration section this specification details. Base Addresses UART Table Asynchronous Communications Engine (UART) Registers Fixed Register Base Offsets Register Base Range Index 0x60,0x61 [0x100:0x0FF8] RB/TB IIR/FCR LCR|
BYTE Register 0x60 stores 0x61BOUNDARIES 550-UART's 16-bit Base Address.
Fast IR/USRT Table Synchronous Communications Engine (SCE) Registers Register Index Base Range Fixed Register Base Offsets
0x62,0x63
[0x100:0x0FF8]
Register Block address USRT Master address Register BlockControl Reg.1
BYTE BOUNDARIES Register 0x62 stores 0x63 55
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